JP3178277B2 - Direct conversion receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct conversion receiver for digital radio communication.

[0002]

2. Description of the Related Art Recently, frequency shift keying (FSK: Frequency Shift Key) on a radio frequency carrier.
For example, as a receiver of a digital modulation signal such as frequency-shifting keying, a direct conversion receiver is being studied as a configuration suitable for integration into an integrated circuit.

[0003] For example, a configuration described in Japanese Patent Application Laid-Open No. 55-14701 is known. Hereinafter, a conventional FSK data demodulator will be briefly described with reference to FIG.

In FIG. 8, a FSK reception signal received by an antenna 1 is supplied to a mixer 7 at the same time as being supplied to a mixer 7 as a signal 3 whose amplitude is amplified by a signal amplifier 2. The signal 5 having the same frequency as the carrier of the FSK reception signal supplied from the local oscillator 4 is supplied to the mixer 7,
After being supplied to the mixer 8 through the 90-degree phase shifter 6 and mixed with the amplified FSK reception signal 3, each of the signals is passed through the low-pass filters 9 and 10 that pass only the baseband signal. Then, an I (in-phase verse band) signal 11 and a Q (quadrature baseband) signal 12 are obtained, whose phase delay relations are inverted by the frequency shift of the FSK signal.

The I signal 11 and the Q signal 12 are passed through amplitude limiting amplifiers 13 and 14, respectively, to output digital signals 15 and 16 respectively.
Get. Then, the digital signals 15 and 16 are supplied to the D input terminal and the clock input terminal of the D flip-flop 50, and the final demodulation result is obtained using the output signal 51 of the D flip-flop 50.

[0006]

The direct conversion receiver has a structure suitable for reduction in size and weight due to integration into an integrated circuit, and is therefore being used in mobile radio terminals and the like. In recent years, the demand for increasing the communication capacity in mobile wireless communication has been increasing, and it has been necessary to increase the communication data rate and narrow the communication frequency band. In an FSK modulated signal, the ratio between the data rate and the FSK frequency shift is called a modulation index. Conventionally, a FSK modulation format having a modulation index of 5 or more has been mainly used. A modulation format may be used.

When demodulating a high-speed, narrow-band FSK format having a modulation index of 2 or less in a direct conversion receiver configuration as shown in the conventional example, accurate demodulation can be achieved by delay in phase detection between I and Q signals. Have difficulty.

[0008] Further, even when the frequency of the local oscillator signal is deviated, the deterioration of the reception characteristic due to the influence of the delay in the phase detection becomes large, so that the signal source needs to have high frequency accuracy. there were.

In view of the above prior art, the present invention provides a direct conversion receiver, which enables high-speed reception of an FSK signal, which was impossible with a conventional digital demodulation system, and local transmission. It is an object of the present invention to increase the tolerance for the frequency deviation of the device signal, to realize the components by digital circuit elements, to easily integrate, and to cope with the miniaturization and low price of the receiver by IC.

[0010]

In order to achieve the above object, the technical solution of the present invention is based on the orthogonality of the I and Q signals. By comparing the sign of the I signal with the signal obtained by shifting the signal by 90 degrees, a first demodulation result is obtained.
A second demodulation result is obtained by comparing the sign of the Q signal with the signal obtained by shifting the phase of the I signal by 90 degrees by taking in the sign of the I signal at the sign change point of the signal, and obtaining the first and second demodulated results.
From the demodulation result of the above, the final demodulation result is obtained by the early arrival signal judging means which outputs the demodulation result in the early arrival order, so that the delay time in the code judgment can be reduced as compared with the conventional direct conversion receiver. It is intended.

[0011]

According to the present invention, since the detection delay time in the code determination can be shortened by the above configuration, a higher speed and narrower band F
It becomes possible to receive the SK signal. In addition, a receiver configuration having higher sensitivity and greater tolerance to a local oscillator frequency deviation than the conventional FSK receiver can be realized.

Further, by applying the early arrival signal judging means in the present invention to a demodulated signal synthesizing section in a conventional two-path direct conversion receiver, the above-mentioned effect can be easily obtained.

Further, since the configuration of the present invention is relatively simple and can be realized by a digital signal processing circuit,
The integration of the entire demodulator becomes easy, and the miniaturization and low power consumption of the receiver can be realized at the same time.

[0014]

【Example】

(Embodiment 1) Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a circuit diagram of a main part of a direct conversion receiver according to a first embodiment of the present invention.

In FIG. 1, 1 is a receiving antenna, 2 is an amplifier of a received signal, 3 is a received FSK signal whose amplitude has been increased in the amplifier 2, and 4 is a local signal 5 having a frequency substantially equal to the carrier of the received FSK signal 3. A local oscillator for generating, 6 is a 90-degree phase shifter for shifting the phase of the local signal 5 by 90 degrees, 7 is first signal mixing means for mixing the reception FSK signal 3 and the output signal of the local signal 5, and 8 is reception. Second signal mixing means 9 and 10 for mixing the FSK signal 3 and the output signal of the 90-degree phase shifter 6 are first and second signal mixing means 7 and 8, respectively.
, A low-pass filter that extracts only a desired FSK modulation component, 11 and 12 denote I and Q baseband signals extracted by the low-pass filters 9 and 10, and 13 and 14 denote I and Q baseband signals. , Q baseband signals 11, 1
First and second amplitude limiting amplifiers for outputting signals 15 and 16 obtained by binarizing 2; 17, first edge detecting means for detecting a sign change point of the signal 16; 18 for the signal 15 as a data input; A D-type flip-flop which outputs the signal 19 by using the detection signal of the edge detecting means 17 as a clock input and 20 is a first exclusive OR operation circuit for obtaining a demodulation result 21 from the exclusive OR of the signal 19 and the signal 16. .

Here, in FIG. 2, (a) shows an example of a transmission signal, and (b) to (g) show examples of signal waveforms in a demodulation process inside the receiver having the above-described configuration, each of which is shown in FIG. (b)
~ (G).

The operation of the above configuration will be described below. First, the F received by the receiving antenna 1
The amplitude of the SK modulated signal is amplified by the amplifier 2 and supplied to the mixers 7 and 8. Here, the local signal 5 having a frequency substantially equal to the carrier of the FSK modulated signal generated from the first local oscillator 4 is mixed with the FSK signal by the mixer 7, and the band is limited by the low-pass filter 9. , FSK-modulated signal 11 is obtained.

This signal 11 is generally called an I signal.
The local signal 5 has a phase of 90 degrees by a 90-degree phase shifter 6.
After the phase shift, the FSK modulated signal 3
, And the band is limited by the low-pass filter 10, whereby a signal 12 having the same FSK modulation component as the signal 11 is obtained. Generally, the signal 12 is called a Q signal.

FIG. 2A shows a transmission code, and FIG. 2B shows an I signal 1
FIG. 2C shows an example of the signal waveform of the Q signal 12. As is well known, the I signal 11 and the Q signal 12 have a property that their phases are orthogonal to each other, and the phase delay relationship is reversed due to a code change of a transmission code.

The I signal 11 and the Q signal 12 are orthogonal in phase. Therefore, the signal 15 and the signal 16 (FIGS. 2 (d) and 2 (e)), which have been binarized, always maintain a phase difference of 90 degrees. It occurs at a timing shifted by 90 degrees from the change point. Therefore, by taking in the sign of the signal 15 at the sign change point of the signal 16, a binary signal 19 delayed 90 degrees in phase from the signal 15 can be obtained. That is, the edge detecting means 17 generates a short pulse when the sign change point is detected in the signal 16 and uses the signal as the clock signal of the first flip-flop 18 so as to capture the signal 15 at the sign change point of the signal 16. , A signal 19 which is artificially delayed by 90 degrees from the signal 15 is obtained as an output.

Here, if the Q signal 12 is delayed by 90 degrees from the I signal 11, the signal 19 (FIG. 2 (f)) obtained by delaying the signal 15 by 90 degrees becomes in phase with the signal 16. , The phase comparison result 2 in the first exclusive OR circuit 20
1 (FIG. 2 (g)) becomes 0. Conversely, compared to I signal 11, Q
If signal 12 is advanced by 90 degrees, signal 15 is
Since the signal 16 is advanced by 180 degrees as compared with the signal delayed by 180 degrees, the signal 16 has the opposite phase. Therefore, in this case, the phase comparison result 21 in the first exclusive OR circuit 20 is
It becomes 1. By these operations, the phase relationship between the I and Q signals caused by the sign change of the transmission data can be detected. As described above, the sign change in the transmission signal can be detected based on this result, that is, demodulation is performed.

Here, a specific circuit example of the edge detecting means 17 used in the configuration of the receiver will be described with reference to FIGS.

FIG. 3 is a circuit diagram showing a first embodiment of the edge detecting means 17. In FIG. 5, 40 is an exclusive OR operation circuit, 41 is a resistance element, and 42 is a capacitance element. The exclusive OR operation circuit 40 supplies the input signal of the edge detecting means 17 to one of the two input terminals, and grounds the other through the capacitor 42. A resistance element 41 is provided between the input terminals of the exclusive OR operation circuit 40,
A capacitance element and a signal delay circuit are formed. With this configuration, when a sign change occurs in the input signal of the edge detecting means 17, the input terminal of the exclusive OR operation circuit 40 provided with the resistor and the capacitor is delayed by the resistor 41 and the capacitor 42. A signal is supplied, and a sign change occurs at the other input terminal without delay.

Therefore, the delayed time causes a difference in sign between the two input terminals of the exclusive OR operation circuit 40,
A signal is generated as an edge detection signal.

FIG. 4 is a circuit diagram showing a second embodiment of the edge detecting means. In FIG. 4, reference numeral 43 denotes an exclusive OR operation circuit, and reference numeral 42 denotes an even number of signal inversion circuits. In the embodiment shown in FIG. 4, the edge detecting means 1 shown in FIG.
7, a delay circuit configured using the resistance element and the capacitance element
It is replaced by an even number of signal inversion circuits 42, and the operation is the same as that of the configuration example of FIG.

Since it is often difficult to form a capacitive element by an integrated circuit, the use of the edge detecting means having the configuration shown in FIG. 4 facilitates integration into a circuit.

(Embodiment 2) Hereinafter, referring to FIG.
A second embodiment of the present invention will be described. FIG. 5 is a circuit diagram of a main part of a direct conversion receiver according to a second embodiment of the present invention.

In FIG. 5, 1 is a receiving antenna, 2 is an amplifier of a received signal, 3 is a received FSK signal whose amplitude has been increased in the amplifier 2, and 4 is a local signal 5 having a frequency substantially equal to the carrier of the received FSK signal 3. A local oscillator for generating, 6 is a 90-degree phase shifter for shifting the phase of the local signal 5 by 90 degrees, 7 is first signal mixing means for mixing the reception FSK signal 3 and the output signal of the local signal 5, and 8 is reception. Second signal mixing means 9 and 10 for mixing the FSK signal 3 and the output signal of the 90-degree phase shifter 6 are first and second signal mixing means 7 and 8, respectively.
, A low-pass filter for extracting only a desired FSK modulation component, 11 and 12 denote I and Q baseband signals extracted by the low-pass filter,
Reference numerals 13 and 14 denote first and second amplitude limiting amplifiers for outputting signals 15 and 16 obtained by binarizing the I and Q baseband signals 11 and 12, and reference numeral 17 denotes a first edge for detecting a sign change point of the signal 16. The detecting means 18 is a D-type flip-flop which outputs the signal 19 by using the signal 15 as a data input and the detection signal of the edge detecting means 17 as a clock input, and obtains a demodulation result 21 from an exclusive OR of the signal 19 and the signal 16. This is a first exclusive OR operation circuit, and the above configuration is the same as that of FIG.

FIG. 2 is different from FIG.
Edge detecting means 2 for detecting a sign change point in
3 and the signal 16 as the data input to the second edge detecting means 2
3 as a clock input, a second exclusive OR operation circuit for obtaining an exclusive OR 27 of the output signal of the D flip-flop 24 and the signal 15, and a signal 21 + An addition / subtraction circuit 28 for obtaining a final demodulation result 29 with the input 27 and the signal 27 as a negative input is newly provided.

The outline of the demodulation operation in the second embodiment shown in FIG. 5 is the same as that of the configuration in FIG.
The difference will be described with reference to FIG.

In the first embodiment, the sign of the I signal (FIG. 2D) at the sign change point of the Q signal (FIG. 2E) is detected by the D-type flip-flop 18 so that the I signal (FIG. A signal (FIG. 2 (f)) obtained by pseudo-delaying FIG. 2 (d) by 90 degrees is obtained, and a demodulation result (FIG. 2 (g)) is obtained by comparison with the Q signal (FIG. 2 (e)). Was.

That is, in the configuration shown in FIG. 1, the phase relationship between the I signal and the Q signal is detected only at the sign change point of the Q signal. Here, the I signal and the Q signal are relatively 90
Since the signals have the same frequency and different phases, the I signal and the Q signal are exchanged in the description of the first embodiment, thereby detecting the phase relationship between the I signal and the Q signal at the sign change point of the I signal. be able to. This allows
At the sign change points of the I signal and the Q signal that occur alternately, it is possible to detect the respective phase relationships, and the delay time in the phase detection is reduced by almost half.

In the configuration of FIG. 5, in addition to the operation of the second embodiment, a short pulse is generated when the edge detecting means 23 detects a sign change point of the I signal 11, and the clock signal of the second flip-flop 24 is generated. By doing
At the sign change point of the binarized I signal 15 (FIG. 2 (d)), the binarized Q signal 16 (FIG. 2 (e)) is taken in, and the signal 16 (FIG. 2 (e)) is simulated as an output. A signal 25 (FIG. 2 (h)), which is delayed by 90 degrees, is obtained. The signal 25 (FIG. 2)
(h)) and the exclusive OR circuit 2 of the signal 15 (FIG. 2 (d))
The second demodulation result 27 (FIG. 2)
(i)) is obtained.

That is, compared to the I signal 11, the Q signal 12
Is delayed by 90 degrees, the signal 25 obtained by pseudo-delaying the signal 16 obtained by binarizing the Q signal 12 by 90 degrees is delayed by 180 degrees from the signal 15 obtained by binarizing the I signal 11. Therefore, the phase becomes opposite, and the phase comparison result 27 in the second exclusive OR operation circuit 26 becomes 1.

Conversely, the Q signal 12 is 90
If the signal has advanced by one degree, the signal 16 obtained by delaying the signal 11 by 90 degrees and the signal 16 have the same phase. Therefore, in this case, the phase comparison result 27 in the second exclusive OR operation circuit 26 is
It becomes 0. By these operations, it is possible to detect the phase relationship between the I and Q signals caused by the sign change of the transmission data.

However, the second demodulation result 2 obtained here
Since the positive / negative relationship in 7 is opposite to that of the first demodulation result 21, the addition / subtraction circuit 28 reverses and combines them to obtain the final demodulation result 29 (FIG. 2 (j)).

By performing demodulation with the above configuration, I
The update of the demodulation result is performed at the code change point that occurs alternately in the signal 11 and the Q signal 12. Therefore,
Since the number of times of detection of the phase between the I signal 11 and the Q signal 12 almost doubles as compared with the case of the first embodiment, the delay of the phase detection in demodulation, that is, the demodulation error is almost halved.

Since the reduction of the demodulation error directly leads to the improvement of the receiving sensitivity, the receiving sensitivity is improved. In addition, since the amount of delay in phase detection in demodulation is reduced, high-speed F
It becomes possible to receive the SK signal.

(Embodiment 3) Hereinafter, referring to FIG.
A third embodiment of the present invention will be described. FIG. 6 is a circuit diagram of a main part of a receiver to which the FSK demodulator according to the third embodiment of the present invention is applied.

In FIG. 6, 1 is a receiving antenna, 2 is an amplifier of a received signal, 3 is a received FSK signal whose amplitude has been increased in the amplifier 2, and 4 is a local signal 5 having a frequency substantially equal to the carrier of the received FSK signal 3. A local oscillator for generating, 6 is a 90-degree phase shifter for shifting the phase of the local signal 5 by 90 degrees, 7 is first signal mixing means for mixing the reception FSK signal 3 and the output signal of the local signal 5, and 8 is reception. Second signal mixing means 9 and 10 for mixing the FSK signal 3 and the output signal of the 90-degree phase shifter 6 are first and second signal mixing means 7 and 8, respectively.
, A low-pass filter that extracts only a desired FSK modulation component, 11 and 12 denote I and Q baseband signals extracted by the low-pass filters 9 and 10, and 13 and 14 denote I and Q baseband signals. , Q baseband signals 11, 1
First and second amplitude limiting amplifiers for outputting signals 15 and 16 obtained by binarizing 2; 17, first edge detecting means for detecting a sign change point of the signal 16; 18 for the signal 15 as a data input; A first D-type flip-flop which outputs a signal 19 by using a detection signal of the edge detection means 17 as a clock input;
Is a first exclusive OR operation circuit for obtaining a first demodulation result 21 from the exclusive OR of the signal 19 and the signal 16, 23 is a second edge detecting means for detecting a sign change point in the signal 15, and 24 is A second D-type flip-flop 26 which uses the signal 16 as a data input and the output signal of the second edge detecting means 23 as a clock input, and 26 is a second D-type flip-flop 24
The exclusive OR of the output signal 25 and the signal 15 is calculated and the second
This is the second exclusive OR operation circuit that obtains the demodulation result 27 of the above. The above configuration is the same as that of FIG.

The configuration of FIG. 6 differs from the configuration of FIG. 5 in that a sign inversion circuit 30 for inverting the sign of the second demodulation result 27 and a first demodulation result 2
1 and an early arrival signal judging means 31 for outputting a signal in the early arrival order among the output signals of the sign inversion circuit 30 to obtain a final demodulation result 32.

The outline of the demodulation operation in the third embodiment shown in FIG. 6 is similar to that of the configuration in FIG.
The difference will be described with reference to FIG.

As described in the second embodiment, the first demodulation result 21 (FIG. 2 (g)) and the second demodulation result 27
Since FIG. 2 (i) has an opposite sign, here, the sign inversion circuit 30 inverts the sign of the second demodulation result 27 to provide consistency, and arrives early together with the first demodulation result 21. The signal is supplied to the signal determination means 31. Since the first demodulation result and the second demodulation result alternately change the demodulation result, if there is a code change in the transmission signal, one is detected first and the other is subsequently detected. Therefore, the transmission code changes, and among the first and second demodulation results,
When only one of them is detected, the demodulation results are contradictory, and the final demodulation result (FIG. 2 (j)) in the second embodiment has an indefinite code area.

The early arrival signal judging means 31 is provided in order to suppress the occurrence of a code indefinite area in the demodulation result. When two input signals have the same sign, a signal having the same sign as the input signal is provided. Is output. Then, when a sign change occurs in one of the two input signals, the signal that detects the sign change is prioritized, and the output sign is changed. This operation eliminates the indefinite region of the code at the code change point in the final demodulation result obtained in the second embodiment shown in FIG. 2 (j), thereby reducing the determination delay in the demodulation result.

FIG. 7 shows an embodiment of a specific circuit configuration of the early arrival signal judging means 31. In FIG. 7, reference numeral 45 denotes an exclusive OR operation circuit which receives two input signals of the early arrival signal determination means and detects a sign change in one of the input signals, and 46 denotes an exclusive OR operation circuit 45 A sign inverting circuit 47 for inverting the sign of the output signal of D. A D-type flip-flop 47 receives one of the two input signals of the early arrival signal determination means 31 as a data input and the output signal of the sign inverting circuit 46 as a clock input. And 48, the output signal of the exclusive OR operation circuit 45 as an input,
This is an exclusive OR operation circuit that inverts the output signal of the D-type flip-flop 47 when a sign change in one of the two input signals 1 is detected.

As described above, the signals (g) and (i) shown in FIG. 7 have one sign change after the other. FIG. 7 illustrates a case where the sign change of the signal (i) occurs after the sign change of the signal (g). The operation will be described below in order based on the changes in the signals (g) and (i). 1) When the signal (i) changes following the sign of the signal (g), the output signal (k) of the exclusive OR circuit 45 becomes 0 and the output signal of the sign inverting circuit 46 becomes 1. At this time, since the rising pulse is input to the clock input, the D-type flip-flop 47 outputs the sign of the data input as the output signal (l). Since the input signal (k) of the exclusive OR operation circuit 48 is 0, the output signal (m) is
A signal having the same sign as (l) is output. This is the input
It has the same sign as (g) and (i). 2) Next, when a sign change occurs only in the signal (g), the output signal (k) of the exclusive OR 45 becomes 1, and the exclusive OR operation circuit 48 outputs a signal obtained by inverting the sign of the input signal (l). Is output. This is the same sign as the changed (g) signal. The case where the signal (i) changes following the signal (g) is as described in 1). By the above operation,
Among the signals (g) and (i), the sign of the previously changed signal is output. For this reason, the output signal of the first-come-first-served signal determination means 31 shown in (m) of FIG. 7 has no indefinite area of the code in the demodulation result as shown in (j) of FIG.
The demodulation error in the demodulation result is also reduced.

A relatively slow FS with a modulation index of 5 or more
When the K signal is received, there is no significant difference in performance between the configurations in the second and third embodiments. However, when receiving a high-speed FSK signal having a modulation index of 3 or less, the characteristics may be degraded unless the configuration shown in this embodiment is used.

In addition, due to the reduction of the delay error in the demodulation as described above, it is advantageous in terms of tolerance when the frequency of the local oscillator signal is shifted.

[0049]

As described above, according to the present invention,
In the configuration of the direct conversion receiver, high-speed FS that was impossible with the conventional digital demodulation system
It becomes possible to receive the K signal. At the same time, the tolerance for the frequency deviation of the local oscillator signal can be increased. In addition, since the components can be realized by digital circuit elements, integration is easy, and miniaturization and low price of a receiver by adopting an IC can be supported, so that the industrial effect is large.

[Brief description of the drawings]

FIG. 1 is a block diagram of a main part of a direct conversion receiver according to a first embodiment of the present invention.

FIG. 2 is a main part block waveform diagram of the direct conversion receiver in the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of an edge detecting unit which is a main part of the direct conversion receiver according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of an edge detecting means which is a main part of the direct conversion receiver according to the first embodiment of the present invention.

FIG. 5 is a block diagram of a main part of a direct conversion receiver according to a second embodiment of the present invention.

FIG. 6 is a block diagram of a main part of a direct conversion receiver according to a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of an early arrival signal determination unit that is a main part of a direct conversion receiver according to a third embodiment of the present invention.

FIG. 8 is a circuit diagram showing a main part of a receiver to which a conventional FSK demodulator is applied.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Receiving antenna 2 Amplifier 3 Received FSK signal 4 First local oscillator 5 Local signal 6 90-degree phase shifter 7, 8 First and second signal mixing means 9, 10 Low-pass filter 11 I Baseband signal 12 Q Baseband signal 13, 14 First and second amplitude limiting amplifier 17, 23 First and second edge detecting means 18, 24 D-type flip-flop 20, 26 First and second exclusive OR operation circuit 30 Sign inverting circuit 31 Early arrival signal determination means

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Katsushi Yokozaki 4-3-1 Tsunashima, Kohoku-ku, Yokohama-shi, Kanagawa Prefecture Inside Matsushita Communication Industrial Co., Ltd. (56) References JP-A-5-191463 (JP, A) JP-A-3-82248 (JP, A) JP-A-3-101445 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 27/14

Claims (7)

(57) [Claims] 1. The method according to claim 1, wherein the received FSK signal is converted to an I baseband signal.
Direct conversion means for quadrature demodulation to signal and Q baseband signals
And the I baseband signal and the Q baseband signal
An amplitude limiting amplifier for converting a signal into a binary signal;
For detecting the sign change point of the extracted Q baseband signal
Detection means, and a clock input to the output of the edge detection means
And input the binary I baseband signal as data.
A D-type flip-flop as the force,
Output signal and the binarized Q baseband signal
Exclusive logical operation circuit for calculating exclusive OR with
Direct conversion receiver . 2. A local oscillator for generating a local signal having a frequency substantially equal to a carrier frequency of a received FSK modulated signal, and a signal having the same frequency as that of the local signal and having a phase shifted by 90 degrees from the local signal. A 90-degree phase shifter, a first signal mixer for mixing the local signal and the received FSK modulated signal, and a signal obtained by phase-shifting the local signal by the 90-degree phase shifter and the received FSK modulated signal A second low-pass filter that removes high-frequency components in the signal from the first signal mixer and extracts an I baseband signal that is a modulation component; A second low-pass filter for extracting a Q baseband signal from a signal from the signal mixer, a first amplitude limiting amplifier for converting the I baseband signal into a binary signal, A second amplitude limiting amplifier for converting a baseband signal into a binary signal; a first edge detecting means for detecting a sign change point from an output signal of the second amplitude limiting amplifier; and a first edge detecting means. Is output as a clock input, and the output signal from the first amplitude limiting amplifier is used as a data input. By detecting the I signal at a change point of the Q baseband signal, A first D-type flip-flop for generating a signal delayed by 90 degrees in a pseudo manner;
A direct conversion receiver having a first exclusive OR operation circuit that receives an output signal of a flip-flop and an output signal of the second amplitude limiting amplifier and obtains a demodulation code determination result as an output. 3. A second amplitude limiting amplifier, comprising: a second edge detecting means for detecting a sign change point from an output signal of the first amplitude limiter; and an output signal of the second edge detecting means as a clock input. Is output as a data input, and a Q baseband signal is detected at a change point of the I baseband signal.
A second D-type flip-flop that generates a signal delayed by 0 degrees, a second exclusive flip-flop that receives an output signal of the second D-type flip-flop and an output signal of the first amplitude limiting amplifier; And the output signal of the first exclusive-OR operation circuit and the output signal of the second exclusive-OR operation circuit are set as a negative input.
3. The direct conversion receiver according to claim 2, further comprising an addition / subtraction circuit for outputting a demodulation code determination result obtained by subtracting an input. 4. A first sign inversion circuit for inverting a sign of an output signal of a second exclusive OR operation circuit, a first exclusive OR operation circuit, and the first exclusive OR operation circuit instead of the addition / subtraction circuit. 4. The direct conversion receiver according to claim 3, further comprising: an early arrival signal judging means for receiving an output signal of the sign inverting circuit as an input and outputting a signal having a sign change among the respective input signals in an early arrival order. 5. A third exclusive-OR circuit for detecting two signs of the early arrival signal as input signals and detecting a sign change in one of the input signals. A second sign inverting circuit for inverting the sign of the output signal of the third exclusive OR operation circuit;
A third D-type flip-flop having one of the two input signals of the early arrival signal determination means as a data input and an output signal of a second sign inverting circuit as a clock input; The output signal of the D-type flip-flop of
An output signal of the third exclusive OR circuit is input, and an output signal of the third D-type flip-flop is detected as a sign change in one of two input signals of the early arrival signal determination means. provided a fourth exclusive OR operation circuit that inverts when is performed, according to claim 4, wherein the output signal of the fourth exclusive OR operation circuit as the output signal of the early arrival signal determining means Direct conversion receiver. 6. An edge detecting means having a fourth exclusive OR operation circuit, wherein an input signal of said edge detecting means is supplied to one of two input terminals of said fourth exclusive OR operation circuit. And the other input terminal is grounded through a capacitive element, and a resistance element is provided between the two input terminals of the fourth exclusive-OR operation circuit, whereby the fourth exclusive-OR operation is performed. A delay is given to one of the input signals of the arithmetic circuit, and in the input signal of the edge detection means,
5. The direct conversion receiver according to claim 2, wherein a short pulse-like output signal is obtained when a sign change occurs. 7. A delay circuit comprising a fifth exclusive OR operation circuit and an even number of sign inversion circuits as edge detection means.
And inputting the input signal of the edge detecting means to the fifth
And the other input terminal of the exclusive OR operation circuit is connected to the edge detection circuit.
Supplying a signal obtained by delaying the input signal of the means by the delay circuit
The direct conversion receiver according to any one of claims 2, 3, and 4 .