JP3373960B2 - Direct conversion receiver - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver for receiving a phase-modulated digital radio signal, and more particularly to improvement of a demodulation circuit by a direct conversion system.

[0002]

2. Description of the Related Art Conventionally, most radio receivers have adopted a heterodyne system. This is a high frequency band received signal from the antenna is amplified by a preamplifier, and then mixed with a signal from a local oscillator to be converted into an intermediate frequency signal,
This is amplified or passed through a band-pass filter, sometimes further converted into second and third intermediate frequency signals and subjected to similar processing, and finally a base band signal is obtained.

In the heterodyne system, amplification and channel selection are performed in several stages at different frequencies, so that they have advantages such as difficulty in oscillation even at high gain and good selectivity characteristics.

On the other hand, since the structure is complicated and the selection filter is in the intermediate frequency band, there are problems that spurious interference is likely to occur, which is an obstacle to miniaturization, low power consumption, and low price. .

For this reason, the direct conversion system has been attracting attention for mobile communication wireless devices, which are particularly required to be miniaturized. This is characterized in that a signal in a high frequency band is amplified by a preamplifier, then directly converted into a base band by a local oscillation signal having the same frequency as the signal, and amplification or channel selection is performed in the base band. Since it is composed mainly of a baseband amplifier and a low-pass filter without using an intermediate frequency signal, this method is suitable for IC implementation.

When receiving and demodulating a phase-modulated signal such as BPSK, QPSK, π / 4 shift QPSK, which is frequently used in digital radio communication, by such a direct conversion system, conventionally, for example, Japanese Patent Laid-Open No. 2-39.
As described in Japanese Patent No. 652 (H04L27 / 22), the structure shown in FIG. 5 was adopted.

In FIG. 5, the signal received from the antenna 20 is amplified by the preamplifier circuit 21 and then mixed by the mixing circuit 2.
At 2, it is mixed with the signal generated by the orthogonal signal generation circuit 23. After passing through the low-pass filter 24, the limiter circuit 27 applies a limiter to the demodulation circuit 28.
Demodulated at. In this system, here, the antenna 2
In order to keep the phase relationship between the phase-modulated signal received at 0 and the signal generated by the quadrature signal generation circuit 23 constant, the phase error detection circuit 26 outputs a voltage substantially proportional to the phase difference between these two signals. Then, by varying the oscillation frequency of the voltage controlled oscillator 25 with this output, the phase of the quadrature signal generation circuit 23 is feedback-controlled.

The phase error detection circuit 26 in this system
Includes a plurality of multiplication circuits as disclosed in Japanese Patent Laid-Open No. 2-39652. However, the input of the phase error detection circuit 26 is generally weak and is subject to level fluctuation due to the influence of fading, so that it is difficult to configure a multiplication circuit. Further, in order to stabilize the operation of the phase control, the output of the phase error detection circuit 26 should not be affected by the input level. Therefore, in the embodiment of JP-A-2-39652, the AGC is introduced in the high frequency stage. However, in general, the strength of received radio waves in mobile communication has a very wide dynamic range, and therefore, fluctuations cannot be sufficiently absorbed by an AGC having only a high frequency stage.

Further, as shown in FIG. 6, there is also a configuration method in which a loop for keeping the phase relationship between the quadrature signal generation circuit and the received signal constant is not provided. In the figure, a signal received from an antenna 29 is amplified by a preamplifier circuit 30 and then mixed by a mixer circuit 31 with a signal generated by a quadrature signal generator circuit 32. Then, after passing through the low pass filter 33, it is sent to the voltage control amplifier circuit 34.

In this embodiment, the two signals in the base band are digitized by the AD conversion circuit 35 and demodulated by digital signal processing. In this case, it is necessary to extract the AGC voltage and add it to the voltage control amplifier circuit 34 so that the signal falls within the appropriate input voltage range of the AD conversion circuit 35. However, also here, the input of the voltage control amplifier circuit 34 is weak and has a wide dynamic range, and the characteristics of the two voltage control amplifier circuits 34 must be well balanced, so that it is difficult to realize such a circuit. . In addition, the power consumption of the AD conversion circuit and the digital signal processing circuit often leads to an increase in cost.

[0011]

In view of the above-mentioned problems of the prior art, the present invention does not require a multiplication circuit for a weak signal and a wide dynamic range AGC loop with uniform characteristics. An object is to provide a system receiver.

[0012]

A direct conversion type receiver according to the present invention is a receiver of an N-value phase-modulated digital radio signal, in which two signals whose frequency is equal to that of a received carrier and whose phase difference is orthogonal to each other. A quadrature signal generating circuit, two mixing circuits that take the product of each of the two signals and the received high frequency signal, and a cutoff frequency that is connected to the outputs of the two multiplying circuits and has a cutoff frequency approximately equal to the signal bandwidth. The two low-pass filters that are provided, a matrix circuit that linearly combines the outputs of the two low-pass filters to obtain N outputs, and the N outputs of the matrix circuits are amplitude-limited and amplified. Based on N limiter circuits that obtain a digital value of 1 or 0 and the output patterns of the N limiter circuits, the phase plane is 2N at intervals of π / N.
From the phase determination circuit that obtains information indicating the divided area and the information indicating the area obtained by dividing the phase plane by 2N at π / N intervals,
A conversion circuit that determines the demodulated data and the phase plane are set to π / N.
A phase error detection circuit for extracting a phase error signal from information indicating a 2N-divided region and a voltage controlled oscillator for generating a frequency reference of the quadrature signal generation circuit whose frequency is controlled by the phase error signal. However, in the matrix circuit, the two inputs are regarded as complex numbers, and π / N
After rotating each of the N types of rotation angles set at intervals, the real part is taken, and an operation is performed so as to output by multiplying an appropriate positive number set for each of the N types of rotation angles. It is a feature.

Further, in the direct conversion type receiver according to the present invention, whether the signal phase is in an even-numbered area from the information indicating the area in which the phase error detection circuit divides the phase plane by 2N at intervals of π / N. The phase error signal is generated by obtaining a digital signal of 1 or 0 depending on whether it is in an odd-numbered area and smoothing the digital signal by a low-pass filter.

[0014]

Operation: N 1's obtained from the output of the limiter circuit
Alternatively, as described in detail in the embodiments below, 2N types of signal patterns are possible, and these are in a one-to-one correspondence with 2N regions divided at π / N intervals on the phase plane. Correspond. Further, from the information of the areas thus obtained, it is possible to check whether the signal is biased to even-numbered areas or odd-numbered areas on average. Therefore, if the phase error signal is generated such that the sign is biased, and the magnitude is approximately proportional to the degree of the bias, and negative feedback is applied to the phase of the quadrature signal generation circuit, It is possible to control so that the phase point of the received signal stays on the even-numbered boundary of the 2N areas or on the boundary of the odd-numbered area on the phase plane. In this method, since the phase error signal is obtained from the output of the limiter circuit, a weak signal multiplication circuit is not required.

Now, the operation of rotating the phase angle of the complex signal by N kinds of rotation angles set at intervals of π / N can be realized only by the addition circuit which can be weighted by positive and negative, and the multiplication circuit is required here as well. Not. Also, since the limiter is applied immediately after the rotation operation, even if the level of the input signal changes,
Not affected.

Thus, according to the present invention, a weak signal multiplication circuit and an AGC loop are not required.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The operation of the embodiment in the case of N = 4, that is, the case of constructing a receiver of a QPSK signal will be described in further detail below with reference to FIG.

In this embodiment, the signals received through the antenna 1 and the preamplifier circuit 2 are multiplied by the quadrature high-frequency signal generated by the quadrature signal generation circuit 4 in the two mixing circuits 3 and two low-pass signals are passed. By extracting the low-frequency component by the filter 5, two baseband signals are obtained. In addition,
The cutoff frequencies of the two low-pass filters 5 are set to be substantially equal to the bandwidth of the signal, so that other channel signals and noise in the received signal are removed.

The matrix circuit 6 inputs the two baseband signals P and Q as a complex signal, and inputs them as 0, π /
It is rotated by 4, π / 2, 3π / 4, and the real part is taken and output. That is, the four outputs of the matrix circuit 6 are

[0020]

[Equation 1]

[0021]

FIG. 2 shows the circuit configuration of the matrix circuit 6, in which 12 is a buffer amplifier circuit.
Reference numeral 13 is an inverting circuit, and 14 is an adder.

Of the baseband signals P and Q, the P signal is input to one buffer amplifier circuit 12a and then branched into three paths, one of which is output to the limiter circuit 7 as it is, and the other is output. One adder 14a, and the last 1
One is input to the other adder 14b via the inverting circuit 13. The Q signal is also input to the other buffer amplifier circuit 12b and then branched into three paths, one of which is one adder 1
4a, the other one is directly output to the limiter circuit 7, and the other one is the other adder 14b.
Entered in. Then, from one adder 14a, P +
Q and -P + Q from the other adder 14b are output to the limiter circuit 7, respectively.

Since only the sign matters in the limiter circuit 7, the result is the same even if the equations (2) and (4) are multiplied by an arbitrary positive number. In the present embodiment,

[0025]

[Equation 2]

The circuit configuration is simplified by dividing by.

Returning to FIG. 1, the four outputs of the matrix circuit 6 are respectively applied to the limiter circuit 7 and become four digital values of 1 or 0 depending on the sign. The phase determination circuit 8 determines in which area on the phase plane the received signal is located from the pattern of the digital value. The method of the determination is shown in FIG.

As shown in FIG. 3 (a), consider a complex plane in which P is a real part and Q is an imaginary part.
Divide into 8 regions (numbered 0 to 7). now,
It is assumed that the signal point changes its phase from 0 to 2π. Figure 2
The four signals s0, sl, s2, s3 at are in the right or left half of the complex plane after rotating the signal points by 0, π / 4, π / 2, 3π / 4 respectively. Depending on whether it is a value of 1 or 0 is output. Therefore, they change as shown in FIG. 3B according to the phase angle of the signal point. From this figure, there are a total of eight possible patterns of the values of s0, sl, s2, and s3, and it is possible to uniquely determine in which region 0 to 7 the signal points are located by that pattern.

In this way, the phase determination circuit 8 of the embodiment shown in FIG. 1 outputs the eight signals shown corresponding to the region where the signal points exist. Of these eight signals, only one of them takes a value of 1 and the other signals become 0 at any time. From this signal, the conversion circuit 9 performs a reverse operation of the coding rule at the time of modulation (for example, Gray code mapping and sum conversion) to obtain demodulated data.

In the phase error detection circuit 10 composed of the OR gate 10a and the low-pass filter 10b, only the odd number (or even number) of the eight outputs of the phase determination circuit 8 is taken out and the logical sum is obtained. To take. This OR signal is 1 when the signal point is in the odd (or even) area of the phase plane and 0 when it is in the even area.
Therefore, the signal smoothed by the low-pass filter indicates which one of the odd-numbered region and the even-numbered region the signal points are biased to exist. Therefore, by changing the oscillation frequency of the voltage controlled oscillator 11 by this phase error signal and correcting the phase of the high frequency signal generated by the quadrature signal generation circuit 4, the phase of the signal point is π except noise and interference components. / 4,3π / 4,5π / 4,7π
It is possible to control so that it stays at the / 4 position.

In this embodiment, in order to make the explanation easy to understand, the phase determination circuit 8, the conversion circuit 9, and the phase error detection circuit 1 are included.
Although the operation of 0 is separated, it is also possible to configure these as one circuit block which performs an equivalent operation. The rotation angle in the matrix circuit 6 is 0, π / 4,
We chose π / 2, 3π / 4, but generally π / 4
Any angle may be used as long as it is set at four angles with an interval of.

In the above embodiment, BPSK (N = 2),
It can be easily extended to 8-PSK (N = 8) or π / 4 shift QPSK which is considered to be a special case of 8-PSK.

FIG. 4 shows another embodiment showing the internal structure of the matrix circuit when N = 8.

The matrix circuit of the present embodiment inputs two baseband signals P and Q as complex signals, and outputs them as 0,
π / 8, π / 4, 3π / 8, π / 2, 5π / 8, 3π /
Rotate by 4,7π / 8, take the real part and output. That is, the eight outputs of the matrix circuit of this embodiment are

[0035]

[Equation 3]

It becomes

In the figure, 16 is a buffer amplifier circuit, 17 is an inverting circuit, and 18 is an adder.

Of the baseband signals P and Q, the P signal is input to one buffer amplification circuit 16a and then branched into seven paths. One of them is the limiter circuit 19 as it is.
Is output to. The signals passing through the other paths are the adders 18a, 1
8b and 18c, and the other path is input to the inverting circuit 1
It is input to the adders 18d, 18e and 18f via 7. The Q signal is also input to the other buffer amplifier circuit 16b and then branched into seven paths, three of which are adders 18a, 18
b, 18c, one of which is the limiter circuit 1 as it is
9 and the remaining three adders 18d, 18e, 1
It is input to 8f.

Then, in each of the adders 18a to 18f, the coefficients α, β and γ shown in the figure are multiplied and then added, and output to the limiter circuit 19 in accordance with the above equations (5) to (12). To be done.

As described above, the adder group 19 performs addition operation with various weights. Generally, in the manufacture of integrated circuits, the resistance ratio can be controlled with high accuracy based on the absolute value of the resistance, and thus such a weighting circuit is suitable for IC implementation.

[0041]

The present invention provides a direct conversion type receiver that does not require a weak signal multiplication circuit or a wide dynamic range AGC loop with uniform characteristics. It is effective for cost reduction and price reduction.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a matrix circuit in the present invention when N = 4.

FIG. 3 is a diagram illustrating an operation of a phase determination circuit according to the present invention. (A) The figure which shows division | segmentation of a phase plane and a region. (B) A diagram showing the relationship between the phase of the signal point and the output of the limiter circuit.

FIG. 4 is a diagram illustrating a configuration of a matrix circuit according to the present invention when N = 8.

FIG. 5 is a diagram showing a first conventional example.

FIG. 6 is a diagram showing a second conventional example.

[Explanation of symbols]

1 antenna 2 Preamplifier circuit 3 Two mixed circuits 4 Quadrature signal generation circuit 5 Two low pass filters 6 matrix circuit 7 4 limiter circuits 8 Phase determination circuit 9 Conversion circuit 10 Phase error detection circuit 11 Voltage controlled oscillator 12 Two buffer amplifier circuits 13 Inversion circuit 14 Adder group 16 Two buffer amplifier circuits 17 Inversion circuit 18 adder group 19 8 limiter circuits

Continuation of the front page (56) References JP 59-50646 (JP, A) JP 7-273824 (JP, A) JP 50-159660 (JP, A) JP 3-262235 (JP , A) JP-A-2-253748 (JP, A) JP-A-4-372248 (JP, A) JP-A-6-181477 (JP, A) JP-A-8-97875 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 27/22

Claims (2)

(57) [Claims] 1. A receiver of an N-value phase-modulated digital radio signal, a quadrature signal generation circuit for generating two signals having a frequency equal to that of a reception carrier wave and a phase difference in a quadrature relationship with each other, and a quadrature signal generation circuit for the two signals. Two mixing circuits that take the product of each and the received high-frequency signal, two low-pass filters that are respectively connected to the outputs of the two multiplication circuits and that have a cutoff frequency approximately equal to the signal bandwidth, and the two low-pass filters. A matrix circuit for linearly combining the outputs of the pass filters to obtain N outputs; and N limiter circuits for obtaining a digital value of 1 or 0 by amplitude limiting and amplifying the N outputs of the matrix circuit. , From the output patterns of the N limiter circuits,
A phase determination circuit that obtains information indicating a region obtained by dividing the phase plane into 2N at π / N intervals, a conversion circuit that determines demodulated data from information indicating a region obtained by dividing the phase plane into 2N at π / N intervals, and A phase error detection circuit that extracts a phase error signal from information indicating a region obtained by dividing the phase plane by 2N at π / N intervals, and a frequency is controlled by the phase error signal to generate a frequency reference of the quadrature signal generation circuit. The matrix circuit comprises a voltage-controlled oscillator, the two inputs are regarded as complex numbers, each of them is rotated by N kinds of rotation angles set at π / N intervals, and then a real part is taken, and A direct conversion type receiver, which operates so as to output by multiplying an appropriate positive number set for each of N types of rotation angles. 2. The phase error detection circuit determines whether the signal phase is in an even-numbered area or an odd-numbered area based on information indicating an area obtained by dividing the phase plane by 2N at intervals of π / N. By obtaining a digital signal of 1 or 0 and smoothing the digital signal with a low-pass filter,
2. The phase error signal is generated.
Direct conversion method receiver described.