JPS6093862A - Delay detector - Google Patents

Abstract

PURPOSE:To correct a cause to fluctuation by giving a phase shift in response to a phase error decreasing a quantized value where (2pi/k) of a phase difference is taken as a step size to a phase of a present reception signal or a phase of a phase difference detecting value or a reception signal before one symbol. CONSTITUTION:The phase difference between the present reception signal and the reception signal before one symbol is given to a detector 1 to detect a k-phase modulation information. A quantized value taking the (2pi/k) of the phase difference as a step size is decreased from the phase difference by a phase error detector 4. An output of the detector 4 is smoothed by a low pass filter 5. A phase shifter 52 conducting phase shift in response to an output phase amount of a low-pass filter output to any of the phase of the present reception signal, the phase of the phase difference detector output and the phase of the reception signal before one symbol is provided to detect the k-phase modulation information.

Description

[Detailed description of the invention] The present invention relates to a delay detector that demodulates a phase modulated signal.

Synchronous detection and delayed detection are widely used for demodulating phase keyed signals (PSK). In particular, since the latter does not require carrier signal regeneration, a simple demodulator can be constructed by allowing some deterioration (about 1.4 dB). However, since there is no carrier phase synchronization function, the delay time error of the delay line (To seconds: normal value is symbol period T),
Temperature change (G/dog) and intermediate frequency f0 (RF
Assuming that F is a variable phase error, a steady phase error O·[rad] is generated as shown by the following equation.

0・≧2πchiX (Operating temperature range) x G XT +
2 w fg ・Ts+ΔWIF11T Therefore, it cannot be used in places where these various quantities fluctuate rapidly. In particular, in the narrowband communication system of satellite communication (% formula %), the previous ΔW□a is large compared to the transmission relay (RK), and the deterioration in conventional delay detection circuits is extremely large.

An object of the present invention is to provide a delay detector that can correct these fluctuation factors.

According to the invention, the current received signal and one sympho.

A phase difference detector that detects k-phase phase modulation information by detecting the phase difference with the previous received signal, and a quantum detector whose step Φ size is (7) of the phase difference from the previous 2π configuration phase difference. a phase error detector for reducing the phase error detector; a low-frequency F-wave generator for smoothing the output of the phase error detector; and a phase difference t of the current received signal or the phase difference detector output.
detecting phase modulation information, including a phase shifter that shifts the phase according to the output phase amount of the low-band P-wave device output in any one of the phases with respect to the received signal one symbol before. A characteristic delayed detector is obtained.

Next, the present invention will be explained in detail with reference to the drawings. FIG. 1 is a block diagram of a conventionally known delay detector. In the figure, 2 is a delay circuit with a symbol period T, and 1 is a phase difference detector that detects the phase difference between the current received signal (terminal 203) and the received signal one symbol before (terminal 204).

Terminal 100 is a received signal input terminal, and terminal 101 is a differential detection output terminal.

In recent years, digitalization of demodulators has progressed, and delay detection methods based on digital processing have come into use.

In this case, the transmitted signal undergoes multiplicative detection at almost the same frequency as the -H transmitted carrier to obtain a complex baseband signal
kT) (k = integer), and then delayed detection is performed by digital processing. FIG. 2 shows a block diagram of the product detector 3. In the figure, 35 is an oscillator having the same frequency as the transmission carrier, 30 and 31 are double balanced mixers (multipliers), 32 is a π/2 phase shifter, 33,
34 is a low-frequency F-wave device, and 36 and 37 are ~Φ converters. A complex digital signal X is output from output terminals 102 and 103.
Real part of (kT).

Since the imaginary parts are output respectively, both terminals are connected to terminal 10.
Let's express it as 4.

Figure 3 is a block diagram of a circuit that receives a complex digital signal x (kT) and performs delay detection using digital processing. -Uses memory. 1 is a phase difference detector, which outputs the current received signal X (kT) and the received signal one symbol before ((k-1)T) to a terminal 203.2.
04, X((k-1)T) is its complex conjugate value X
*((k-1)T) (only inverts the polarity of the imaginary part) to 1
1's conjugate circuit (when the input is ZB 0)°X, the output is ZB-j 'T) is obtained using the complex multiplier 10. Output terminal 105
A vector V is output to. Identification of vector F and transmission code carbonization is performed as follows, where arg(F)
is ・′ of vector i. Indicates the declination angle from.

The above table is illustrated in the 1m4 diagram. The identification circuit corresponding to this figure is a read-only memory (Raad ONLY) which uses the complex digital value F at the terminal 105 as an address and outputs the phase change identification value of the corresponding transmission code.
Memory; ROM) is consumed.

FIG. 5 is a block diagram of an embodiment of the present invention.

Reference numbers 1 and 2 in the figure are the same as 1 and 2 in FIG. 1, respectively. When a 4-phase PSK wave is input to the circuit shown in FIG. 1, the output terminal 101 receives #, +t+ = -H-1+ΔWxvIIT C1=o
, x, -t, 2) is obtained. Here, Hiro considered only ∆WIF as a factor in the deterioration of delayed detection. 4 in Figure 5
is a phase error detector that detects only the above equation ~·T, and is composed of the identification circuit 40 shown in FIG. 4 and a phase difference detector r that obtains the phase difference between its input and output signals. 4 (Since the value of the first term on the right side of tl is the same as the output of the identification circuit 40, the output 0e of the phase difference detector r is θ・=−1+ΔW□2・T−−,,=m□,T Become.

If the received signal is undistorted and has no noise, #O obtained in and ~ corresponds to a steady phase error, but there is also distortion in the general Ku received input signal, and there is no noise. Therefore, the steady phase error needs to be calculated from the average value [(#jt)) of θdt>.

The low-pass P wave unit 50 performs the averaging. As a result, the polarity of 9E(θeH)) is reversed by the inverter 51, and becomes -E(θeH), which is 0X(kT) and X
Since there is a steady phase error of E(oJ) between X(kT) and
It turns out that it is better to turn only l). Therefore, the phase is rotated (added) by the inverter output value using the phase shifter 52.
It's a good idea to let them do it. This brings us to reference number 52.
t, 40. It can be seen from FIG. 5 that r, 50.51 constitutes a first-order feedback control system. In this case #1.
In order to make θe(tl) due to T zero, the feedback control system must include a perfect integrator in the loop.

For this reason, it is desirable that the low-pass p-wave converter 50 be a perfect integrator. Although block 5 in FIG. 5 is a block diagram drawn on a phase basis, in a complex digital value pace block 5 would look like FIG. 6. That is, the output of block f is e
'θ-1). Therefore, 7 fJ @
ftl = CD! e Jl + j ”0m1t)
The imaginary part extractor 55 extracts only the imaginary part of
n f) a (t) ~ θ5 (tl is extracted, this output is integrated by 50 real input integrating circuits, and the output is inverted by an inverter to become −E(Odt))). 54 is RO
M outputs -zl(θpe1)). 53 is a complex multiplier in which the input signal
The phase of X(kT) will be rotated by -E(θeTtl).

7 and 8 are block diagrams of another embodiment of the present invention. Components in each figure correspond to the same numbered components in FIG. The difference between FIG. 5, FIG. 7, and FIG. 8 is the position of the phase shifter 52.

10 Since the phase difference detector is a subtracter that detects a phase difference, even if the phase shifter 52, which also works as a mere adder, is moved to its output side (Fig. 7), it is also possible to change the polarity to the other input terminal. Change (omit inverter 51) and move 4
(Fig. 8) Exactly the same function can be realized.

As described above, according to the present invention, narrow band (S
ingle Channel per Carrier
), where the carrier frequency changes by ~% compared to the transmission baud rate, carrier frequency control (AIi'c) must be applied to each channel separately, but this becomes unnecessary. . Therefore, narrowband 5cpc with frequency offsets independent of each other
This makes it possible to perform group demodulation in which the signal is simultaneously demodulated using a zero converter and a signal processor.

[Brief explanation of drawings]

! Figure s1 is a block diagram of a conventional delay detection circuit, Figure 2 is a block diagram of a multiplicative detector for demodulating by digital processing, Figure 3 is a block diagram of a delay detection circuit for complex digital signals, and Figure 4. 1 is a diagram for explaining a detection output identification circuit for four-phase PSK, and FIGS. 5, 6, 7, and 8 are block diagrams for explaining an embodiment of the present invention. In the figure, 1 is a phase difference detector, 2 is a delay circuit, 4 is a phase error detector, 50 is a low-frequency p-wave device, 51 is an inverter, and 52 is a phase shifter. (9) Tokukai Sho Go-938G2 (5)

Claims (1)

[Scope of Claims] A phase difference detector that detects JK phase position modulation information by detecting a phase difference between a current received signal and a received signal one symbol before; a phase error detector for reducing a quantized value with (-T-) as a step size; a low-pass F wave generator for smoothing the output of the phase difference detector; and a phase shifter that shifts the phase of the output of the phase difference detector or the phase of the received signal one symbol before in accordance with the output phase amount of the output of the low-frequency F-wave device. Delay detection 4 characterized by detecting phase modulation information