JPS6366108B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an 8-phase phase demodulator, and particularly to a communication line based on an 8-phase phase keying (hereinafter referred to as "8PSK") system, in which carrier synchronization and automatic gain of an 8PSK demodulator provided on the receiving side are provided. Concerning improvements related to control and intersymbol interference.

In general, a multi-phase PSK (especially 8-phase or more) type synchronous detection demodulator requires stable and accurate carrier recovery and automatic gain control (hereinafter referred to as "AGC") functions, and on the other hand, transmission over communication lines. From the viewpoint of effectively utilizing the band, there is a desire to suppress the transmission bandwidth as much as possible and maintain the quality of the transmitted communication signal at a predetermined level.

In conventional polyphase phase demodulators, a baseband processing type Costas loop (for example, Japanese Patent Application No. 53-156124) is well known as a carrier wave recovery method. However, this method requires a complicated circuit configuration;
It has problems such as high power consumption and troublesome adjustment, and also causes intersymbol interference between modulated signals in the transmission signal due to fluctuations in transmission characteristics and transmission distortion in the transmission path. There is also the problem of deteriorating the quality.

FIG. 1 is a block diagram showing the main parts of a conventional 8PSK demodulator. This 8PSK demodulator is described in the aforementioned Japanese Patent Application No. 53-156124. An intermediate frequency input signal is inputted from a terminal 101, branched into two by a signal branching circuit 1, and its output is inputted to phase detectors 2 and 3. The output of the voltage controlled oscillator (hereinafter referred to as "VCO") 6 is branched into two by a signal branching circuit 5, one of which is directly input to the phase detector 2, and the other is input to the π/2 phase shifter 4 and then input to the π/2 phase shifter 4.
The signal is given a phase shift of 2 and input to the phase detector 3, and each of the two branched intermediate frequency signals is subjected to orthogonal synchronous detection. This detection output is subjected to binary discrimination in binary discriminators 10 and 13, and the sum and difference thereof are calculated in addition circuit 8 and subtraction circuit 9, respectively. The outputs of the adder circuit 8 and the subtracter circuit 9 are π/4 and 3π/, respectively, with respect to the carrier phase supplied to the phase detector 2.
A signal equivalent to that obtained by synchronous detection using a carrier phase whose phase is advanced by 4 is obtained. The outputs of the addition circuit 8 and the subtraction circuit 9 are subjected to binary discrimination in binary discriminators 11 and 12, respectively. Binary classifier 1
The outputs of 0, 11, 12 and 13 are subjected to code conversion and differential conversion in a code converter 14, and are output as final data via terminals 102, 103 and 104.

In the carrier synchronization method, the outputs of the phase detectors 2 and 3, the adder circuit 8, and the subtracter circuit 9 are input to full-wave rectifiers 18, 17, 16, and 15, respectively, and are subjected to full-wave rectification. Furthermore, the outputs of full-wave rectifiers 15 and 16 are summed in addition circuit 19, and the outputs of full-wave rectification circuits 17 and 18 are summed in addition circuit 20, respectively. The outputs of the adder circuits 19 and 20 are subtracted by a subtracter circuit 21. Binary classifiers 10, 11, 12 and 13
The four outputs are subjected to an exclusive OR in an exclusive OR circuit 23, and according to the result, the polarity of the signal from the subtraction circuit 21 is inverted in a switch 22 to perform automatic phase control (hereinafter referred to as "automatic phase control") for carrier synchronization. ``APC'') signal, and the low frequency filter 7
Control VCO6 via.

However, this method requires four full-wave rectifiers 15,
In order to perform analog processing on the outputs of 16, 17, and 18, it is necessary to adjust the amplitude and DC balance of each full-wave rectifier output in detail, which increases the number of adjustment steps. Since the circuit does not have AGC function,
This method requires a separate AGC circuit, which increases the scale of the circuit structure and increases power consumption. Furthermore, since there is no means for dealing with intersymbol interference caused by fluctuations in transmission characteristics in the transmission path, transmission distortion, etc., it also has the disadvantage of deteriorating signal quality.

An object of the present invention is to eliminate the above-mentioned drawbacks, and to reduce the circuit size by applying digital circuit means and a transversal type equalizer.
The object of the present invention is to provide a relatively inexpensive 8PSK demodulator that has both AGC and APC functions and improves signal quality deterioration due to intersymbol interference.

The 8-phase phase demodulator of the present invention includes a signal branching circuit into which the 8-phase phase modulated wave is input, a voltage controlled oscillator controlled by an automatic phase control signal for carrier synchronization,
a first phase detector that performs orthogonal synchronous detection of one output signal of the signal branch circuit using the output of the voltage controlled oscillator; and a first phase detector that performs orthogonal synchronous detection of one output signal of the signal branch circuit with the output of the voltage controlled oscillator; a second phase detector that performs orthogonal synchronous detection at its output; an adder circuit that adds the output of the first phase detector and the output of the second phase detector; and the output of the first phase detector. a subtraction circuit that subtracts the output of the second phase detector, and first to fourth binary identification to which the outputs of the first and second phase detectors, the addition circuit, and the subtraction circuit are connected, respectively. The outputs of these binary discriminators D ₁ , D ₂ , D ₄ ,
In an 8-phase phase demodulator that converts the code of D ₃ and outputs it, a first transversal equalizer is connected before the signal branching circuit 1 or a stage after the first and second phase detectors. and a second transversal equalizer connected to the second transversal equalizer, and the output signals of the first and second phase detection or the second The error signal in the x direction along the x axis in the phase plane is obtained by inputting the first and second output signals of the transversal equalizer.
first circuit means for generating E _PU and E _PL and error signals E _QU and E _QL in the y direction along the y axis in the phase plane; and each of said error signals E _PU , E _PL , E _QU , E _QL and second circuit means for generating signals _Y'P , _Y'Q from said output signals _D2 , _D4 ; and said two signals _Y'P ,
From Y′ _Q and the output signals D ₁ , D ₃ , the signals Y _P , Y _Q ,
third circuit means for generating C ₁ , C ₃ and said signals;
means for subtracting Y _P and Y _Q from each other and supplying the resultant signal as a control signal for an automatic phase control circuit that controls the voltage controlled oscillator; inputting the signals C ₁ and C ₃ and the output signals D ₁ and D ₃ ; and a first or second control signal generation circuit that supplies a control signal to the first or second transversal type equalizer.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 2 is a block diagram showing the main structure of the first embodiment of the present invention. As shown in Figure 2,
This embodiment includes a first transversal equalizer 40, signal branching circuits 1 and 5, first and second phase detectors 2 and 3, a π/2 phase shifter 4, and a VCO 6. , a low frequency filter 7, an addition circuit 8, a subtraction circuit 9 and 38, and first to eighth binary discriminators 10 to 13 and 24 to 27,
Full-wave rectifiers 17 and 18 and code converter 14
, AND circuits 28 to 31, OR circuits 32 and 33, and exclusive OR circuits 34 to 37 and 39
and a first control signal generation circuit 41.

In FIG. 2, an intermediate frequency signal inputted from a terminal 105 is transmitted to a first transversal equalizer whose tap coefficient is automatically controlled by a control signal inputted from a first control signal generation circuit 41. 40, which is subjected to correction processing to avoid intersymbol interference at the signal sampling point caused by fluctuations in transmission characteristics in the transmission path, transmission distortion, etc., and then branched into two via the signal branching circuit 1. The signals are input to first and second phase detectors 2 and 3, respectively. The output of the VCO 6 where the intermediate frequency input signal branched into two by the signal branching circuit 1 is input to the first and second phase detectors 2 and 3 via the signal branching circuit 5 and the π/2 phase shifter 4. The output signals D ₁ , D 2 , D 4 are mixed with the signals, subjected to orthogonal synchronous detection, and outputted through the addition circuit 8, subtraction circuit 9, and first to _fourth binary discriminators 10 to _13.
and _D3 , which are output from terminals 106 to 108 via code converter 14. This operating process is similar to that of the prior art example described above, except for the action of the first transversal equalizer. The detection output of the first phase detector 2 is input to the first binary discriminator 10, the addition circuit 8, and the subtraction circuit 9 as described above, and is also input to the full-wave rectifier 17.
and its outputs are input to fifth and sixth binary discriminators 24 and 25 to generate error signals E _PU and E _PL , respectively. Similarly, the detection output of the second phase detector 3 is input to the fourth binary discriminator 13, addition circuit 8, and subtraction circuit 9 as described above, as well as to the full-wave rectifier 18, and its output further includes seventh and eighth binary discriminators 26
and 27, respectively, and the error signal E _QU
and generate E _QL . On the other hand, the output signals D 2 and ₂ of the second and third binary discriminators 11 and 12
D ₄ is input to the exclusive OR circuit 39, this output is input to the AND circuits 28 and 31, and
This inverted output is input to AND circuits 29 and 30. In the AND circuits 28 to 31, the corresponding error signals E _PU , E _PL , E _QU and E _QL ,
The output from the exclusive OR circuit 39 described above is input, and each AND output is input to the corresponding OR circuit 3.
2 and 33. OR circuits 32 and 3
3, AND circuits 28 and 2, respectively.
9's OR output _Y'P and AND circuits 30 and 31.
Outputs the OR output Y′ _Q. This signal Y′ _P is the first
The output signal D ₁ of the binary discriminator 10 is input to the exclusive OR circuit 34 in the form of a pair, and the signal C ₁ is generated and input to the first control signal generation circuit 41. It is input to the circuit 36 as one signal. Similarly, the signal _Y'Q is input to the exclusive OR circuit 35 in the form of a pair with the output signal _D3 of the fourth binary discriminator 13, and generates the signal _C3 , which generates the first control signal. The signal is input to the circuit 41 and is also input to the exclusive OR circuit 37 as one signal. In the exclusive OR circuit 36, the signal
It inputs _C1 and signal _D3 and generates and outputs signal _YP . Similarly, the exclusive OR circuit 37 inputs the signal C ₃ and the signal D ₁ and generates and outputs the signal Y _Q. These signals Y _P and Y _Q are input to a subtraction circuit 38, and the mutual difference is taken and output.
The signal is sent to the VCO 6 via the low frequency converter 7. Also,
In the first control signal generation circuit 41, the
C ₁ , C ₃ , D ₁ and D ₃ are input, and a control signal corresponding to N (an integer greater than 1) tap is output and sent to the first transversal equalizer.

Next, the detection outputs of the first and second phase detectors 2 and 3 and the output signals D ₁ , D ₂ , D ₄ and D ₃ of the first to fourth binary discriminators 10 to 13 are combined. Now, the principle of operation for generating the APC signal and the signals C ₁ and C ₃ for the first control signal generation circuit 41 will be explained.

From the first and second phase detectors 2 and 3,
The waveform of the detection output input to the full-wave rectifier circuits 17 and 18, respectively, and the full-wave rectifier circuit 17
and 18 output waveforms are shown in FIGS. 5A and 5B, respectively. The previously mentioned error signals E _PU , E _PL , E _QU and
E _QL is the reference value of E _PU (E _QU ) and E _PL (E _QL ) for the input waveforms to the fifth to eighth binary discriminators 24 to 27 shown in FIG. 5B. As shown, these are digital signals output as α and β, respectively. In addition, E _PU (E _QU ) is shown in Figure 6.
and how to generate E _QU (E _QL ).

On the other hand, the outputs D ₂ D ₄ and _{2 4} of the exclusive OR circuit 39 correspond to the error signals E _PU , E _PL , E _QU and E _QL in the AND circuits 28 and 31 and the AND circuits 29 and 30, respectively. The outputs are logically added in corresponding OR circuits 32 and 33 to generate signals _Y'P and _Y'Q , respectively. Y′ _P and Y′ _Q are expressed by the following logical formula.

Y′ _P = E _PU・(D ₂ D ₄ )+E _PL・( _{2 4} ) Y′ _Q = E _QU・( _{2 4} )+E _QL・(D ₂ D ₄ ) Next, exclusive OR circuits 34 to 37 From the signals Y′ _P , Y′ _Q and the output signals D ₁ , D ₂ , the signals Y _P , Y _Q , C ₁ and C _{3 are}
is generated. These digital signals Y _P , Y _Q ,
C ₁ and C ₃ are expressed by the following logical formula.

Y _P = Y' _P D ₁ D ₃ Y _Q = Y' _Q D ₁ D ₃ C ₁ = Y' _P D ₁ C ₃ = Y' _Q D _3These signals Y _P and Y _Q are The difference is taken and the output signal is passed to the low frequency filter 7.
The frequency of the VCO 6 is controlled via the VCO 6 to reproduce a predetermined carrier wave.

FIG. 7 shows the phase region (a ₁ to
_a8 ), D ₁ , D ₂ , D ₃ , D ₄ , D ₂ D ₄ , D ₁
The respective waveforms of _D3 are shown. D ₁ to _{D 4} are equivalent to phase synchronized detection using carrier waves having phases l ₁ to _{l 4} shown in FIG. 8.

The operating principle related to _the APC of the present invention is that, on the phase plane shown in _FIG . ) is divided into four small regions by two lines parallel to l ₁ and l ₃ (indicated by broken lines in Fig. 8), and each of these phase regions is divided into _four small regions with
The objective is to generate error signal components in the three directions (direction) and _l3 direction (y direction), and to generate control signals related to APC.

Now, in each small region on the phase plane, Y _P
Define the correspondence between and Y _Q as (Y _P , Y _Q ),
When (Y _P , Y _Q ) in each of the small regions is illustrated, it is expressed as shown in FIG. As for the APC function,
Only the small area corresponding to the error signal (1, 0), (0, 1) is valid, and in the small area corresponding to (0, 0), (1, 1), the difference between Y _P and Y _Q is valid. the difference disappears
It does not act as a control signal for APC. In FIG. 9, when the common phase displacement points from the respective regular pull-in points in the phase region (a ₁ to a ₈ ) are illustrated with cross marks, it is clear that a common error signal (1, 0) is generated. . Further, in each of the phase regions, an error signal (0, 1) is generated in a small region corresponding to a portion opposite to the phase displacement point (x mark) with respect to each normal pull-in point. Therefore, as mentioned above, the difference between Y _P and Y _Q is taken as a control signal for APC, and is fed back to the VCO 6 via the low frequency converter 7, thereby forming a phase synchronization system and regenerating the carrier wave. The gain is obvious.

Note that the demodulated baseband signal in the 8PSK system has four levels, but the phases l ₁ and l ₃ shown in FIG.
There is a certain relationship between the two signals that have been orthogonally synchronously detected by is always at a small level. This property is a major difference from the case of 16 (4×4) quadrature amplitude modulation (hereinafter referred to as "16QAM"). As is clear from the above logical formulas of Y _P and Y _Q , for example, when D ₂ D ₄ = 1, Y _P = E _PU ... large level detection Y _Q = E _QL ... small level detection, and it is clear that The difference between 8PSK and 16QAM is incorporated into the error calculation. Due to this,
The eight pseudo pull-in points shown in FIG. 10 (marked with ● in FIG. 10) are completely removed, making it possible to always perform stable phase demodulation via regular pull-in points. Note that the arrow in FIG. 10 indicates the vector position corresponding to the regular pull-in point.

On the other hand, as described above, the digital correlation signals C ₁ (=Y′ _P D ₁ ) and C ₃ (Y′ _Q D ₃ ) output from the exclusive OR circuits 34 and 35 are as follows:
It is input to the first control signal generation circuit 41 together with the output signals D ₁ and D ₃ . The first control signal generation circuit 41 is a first transversal equalizer 4
0 as well as an adaptive transversal equalizer (for example, Japanese Patent Application
11664), and in particular, the first transversal equalizer 40 has N (an integer greater than 1).
The tap configuration is designed to improve equalization ability. The first control signal generation circuit 41 inputs C ₁ , C ₂ , D ₁ and D ₃ and uses a predetermined algorithm to detect the level fluctuations caused by the level fluctuations of the input signal itself or the level fluctuations due to intersymbol interference. By correlating the error signal with the signal in the same time slot in both x and y directions, a control signal is generated to eliminate level fluctuations and intersymbol interference in the input signal. This control signal is input to a variable weighting circuit corresponding to each tap of the first transversal equalizer 40 having an N-tap configuration, and controls the corresponding signal level, so that, as described above,
Eliminate level fluctuations and intersymbol interference in the input signal. The adaptive transversal equalizer is described in detail in the Japanese Patent Application No. 11664/1983.

Next, a second embodiment of the present invention will be described.
FIG. 3 is a block diagram showing the main structure of a second embodiment of the present invention. As is clear with reference to FIG. 3, the difference between the second embodiment and the first embodiment described above is that the first and second phase detectors 2 and 3
The configuration of the first circuit means inputs the output signal of and generates the error signals E _PU and E _PL in the x direction and the error signals E _QU and E _QL in the y direction, and the other components are as follows. , are completely equivalent in the first and second embodiments.

As shown in FIG.
The circuit means includes the ninth to sixteenth binary discriminators 44 to
51, and exclusive OR circuits 52-55. The configuration contents other than this first circuit means are the same as those of the first embodiment as described above.

In FIG. 3, since the operations other than the first circuit means have already been described in detail in the first embodiment, only the operation of the first circuit means will be described. The signals output from the first and second phase detectors 2 and 3 are transmitted to the ninth to twelfth binary discriminators 44 to 47 and the thirteenth binary discriminator, respectively.
to the 16th binary discriminator 48 to 51, and the signals E _P1 , E _P2 , E _P3 and E _P4 and
Output E _Q1 , E _Q2 , E _Q3 , E _Q4 . In Figure 6, the above
E _P1 (E _Q1 ), E _P2 (E _Q2 ), E _P3 (E _Q3 ) and E _P4 (E _Q4 )
The reference values α′, β′, γ′ and δ′ corresponding to are shown.
These output signals are E _P1 and E _P4 , E _P2 and E _P3 , E _Q1 and
E _Q4 , E _Q2 and E _Q3 are divided into four sets, which are input in pairs to exclusive OR circuits 52, 53, 54 and 55, respectively, and error signals E _PU , E _PL are output as respective inverted outputs. , generate E _QU and E _QL . The logical formula in this case is defined by the following formula.

E _PU = _{P1 P4} E _PL = _{P2 P3} E _QU = _{Q1 Q4} E _QL = _{Q2 Q3} These error signals E _PU , E _PL , E _QU and E _QL are:
The error signals E _PU , E PL , E _PL , in the first embodiment described above
It is a signal exactly equivalent to E _QU and E _QL , and therefore,
Although the first and second embodiments have different internal configurations of their respective first circuit means, their operations are completely equivalent. Therefore, the second embodiment has the same APC characteristics as the first embodiment.
AGC characteristics and intersymbol interference characteristics can be improved.

Next, a third embodiment of the present invention will be described.
FIG. 4 is a block diagram showing the main structure of a second embodiment of the present invention. As shown in FIG. 4, this embodiment includes signal branching circuits 1 and 5, first and second phase detectors 2 and 3, π/2 phase shifter 4, VCO 6, and low frequency wave generator 7, second transversal type equalizer wave generator 42, addition circuit 8, subtraction circuits 9 and 38, and first to eighth
binary discriminators 10 to 13 and 24 to 27, first and second full wave rectifiers 17 and 18, code converter 14, AND circuits 28 to 31, OR circuits 32 and 33, exclusive OR circuit 34-3
7 and 39, and a second control signal generation circuit 43.

As is clear from FIG. 4, the difference between the third embodiment and the first embodiment is that in the third embodiment, the second embodiment is used as a component of the adaptive transversal equalizer. Transversal equalizer 42
are arranged at the output stage of the first and second phase detectors 2 and 3, and a second control signal generation circuit 43 is provided. That is, the transversal equalizer operates at the intermediate frequency signal stage in the first embodiment, and operates at the baseband signal stage in the third embodiment. This third
Also in the embodiment, the operation contents of the second transversal equalizer 42 and the second control signal generation circuit 43 forming the adaptive transversal equalizer are the same as in the first embodiment. The same is true for . Furthermore, regarding the APC characteristics other than the AGC characteristics and intersymbol interference characteristics of the adaptive transversal equalizer, all related circuit configurations are the same as those of the first embodiment, and in all aspects, the APC characteristics are the same as those of the first embodiment. The same performance improvement as in the first embodiment can be expected.

In the third embodiment, the first and second output signals of the second transversal equalizer 42 are output, and the error signals E PU and E PL in the x direction and the error signals E _PU and E _PL in the y direction are The first circuit means for generating the error signals E _QU and E _QL includes the first and second full-wave rectifier circuits 17 and 18 and the fifth to eighth circuits, as in the first embodiment. Binary discriminator 24-2
7 as a constituent element, but as in the case of the second embodiment described above, in the third embodiment, the 9th
Even if the first circuit means including the sixteenth binary discriminators 44 to 51 and the exclusive OR circuits 52 to 55 are applied, completely equivalent AGC characteristics,
Needless to say, performance improvements in APC characteristics and intersymbol interference characteristics can be expected.

As explained in detail above, the present invention
By using digital circuit means as a means to generate an error signal and applying an adaptive transversal equalizer, APC characteristics, AGC characteristics, and intersymbol interference characteristics are improved, and the circuit size is relatively small and consumption is reduced. This has the effect of realizing a stable 8-phase demodulator with low power consumption.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main configuration of a conventional 8-phase phase demodulator, and FIGS. 2, 3, and 4 are main configurations of the first, second, and third embodiments of the present invention, respectively. FIG. 5 is a diagram showing the demodulated waveform and full-wave rectification waveform, FIG. 6 is a diagram explaining the error signal generation method, FIG. 7 is a diagram showing the identification signal, and FIG. 8 is a diagram showing the phase plane region division. 9 is a diagram showing the arrangement of APC signals, and FIG. 10 is a diagram showing pseudo pull-in points according to the conventional error signal generation method. In the figure, 1, 5...signal branch circuit, 2...
First phase detector, 3...Second phase detector, 4
...π/2 phase shifter, 6...VCO, 7...Low frequency generator, 8, 19, 20...Addition circuit, 9, 2
1, 38... Subtraction circuit, 10-13... First to fourth binary discriminator, 14... Code converter, 15
~18...Full wave rectifier circuit, 22...Switch, 2
3, 34-37, 39, 52-55...exclusive OR circuit, 24-27...fifth to eighth binary discriminator, 28-31...AND circuit, 32-33
...OR circuit, 40...First transversal equalizer, 41...First control signal generation circuit, 42...Second transversal equalizer, 43...Second Control signal generation circuit, 44-5
1... 9th to 16th binary discriminator, 101 to 1
16...Terminal.

Claims (1)

[Claims] 1. Signal branching circuit 1 into which 8-phase phase modulated waves are input
, a voltage controlled oscillator 6 controlled by an automatic phase control signal for carrier synchronization, and the signal branch circuit 1
A first phase detector 2 performs orthogonal synchronous detection of one output signal of the voltage controlled oscillator 6 using the output of the voltage controlled oscillator 6, and the other output signal of the signal branch circuit 1 is detected with a π/2 phase shift of the voltage controlled oscillator 6. a second phase detector 3 that performs orthogonal synchronous detection on its output; an adder circuit 8 that adds the output of the first phase detector 2 and the output of the second phase detector 3; and the first phase detector Vessel 2
a subtraction circuit 9 for subtracting the output of the second phase detector 3 from the output of the second phase detector 3, the first and second phase detectors, the addition circuit and the subtraction circuit 2,
and first to fourth binary discriminators 10, 11, 12, 13 to which the outputs of 3, 8, and 9 are connected, respectively, and these binary discriminators 10, 11, 12, 1
In the 8-phase phase demodulator that converts the code of the outputs D ₁ , D ₂ , D ₄ , D ₃ of the signal branching circuit 1 and outputs them, the signal branching circuit 1
or a second transversal equalizer 42 connected to the rear of the first and second phase detectors 2 and 3; The output signals of the first and second phase detectors 2 and 3 or the second transversal equalizer 42 correspond to the two connection cases of the transversal equalizers 40 and 42, respectively. The error signals E _PU and E _PL in the x direction along the x axis in the phase plane by inputting the first and second output signals of
first circuit means for generating error signals E _QU and E _QL in the y direction along the axis; and each said error signal E _PU ,
second circuit means for generating signals Y' _P , Y' _Q from E _PL , E _QU , E _QL and said output signals D ₂ , D _{4 ,} and from said two signals Y' _P , Y' _Q and said output signals; third circuit means for generating signals Y _P , Y _Q , C ₁ , C ₃ from signals D ₁ , D ₃ and controlling said voltage controlled oscillator 6 by mutually subtracting said signals Y _P , Y _Q ; means for supplying the signal C ₁ as a control signal to an automatic phase control circuit for
C ₃ and the output signals D ₁ and D ₃ to the first or second transversal equalizer 4.
8-phase phase demodulator, characterized in that it is equipped with a first or second control signal generation circuit 41 or 43 that supplies a control signal to 0 or 42. However, the above six signals are defined by the following logical expressions. Y′ _P = E _PU・(D ₂ D ₄ )+E _PL・( _{2 4} ) Y′ _Q = E _QU・( _{2 4} )+E _QL・(D ₂ D ₄ ) Y _P = Y′ _P D ₁ D ₃ Y _Q = Y' _Q D ₁ D ₃ C ₁ = Y' _P D ₁ C ₃ = Y' _Q D _3In the above equation, is an exclusive OR. 2 the first circuit means is connected to the first and second circuit means;
The output of the first phase detector 2 or the first output of the second transversal equalizer 42 corresponds to the two connection cases of the transversal equalizers 40 and 42, respectively. a full-wave rectifier circuit 17 for full-wave rectifying either the output of the second phase detector 3 or the output of the second transversal equalizer 42 corresponding to the two connection cases; a full-wave rectifier circuit 18 that performs full-wave rectification on any of the outputs of the full-wave rectifier circuit 17; and fifth and sixth binary discriminators that generate error signals E _PU and E _PL in the x direction from the outputs of the full-wave rectifier circuit 17, respectively. 24, 25
and y from the output of the full-wave rectifier circuit 18, respectively.
The eight-phase phase demodulator according to claim 1, further comprising seventh and eighth binary discriminators 26 and 27 that generate direction error signals E _QU and E _QL . 3. The first circuit means is connected to the first and second circuit means.
The output of the first phase detector 2 or the first output of the second transversal equalizer 42 corresponds to the two connection cases of the transversal equalizers 40 and 42, respectively. The ninth to twelfth binary discriminators 44, 4 to which either is connected
5, 46, 47, and the output of the second phase detector 3 or the second transversal equalizer 42, respectively, corresponding to the two connection cases.
13th to 13th to which any of the second outputs of
16 binary discriminators 48, 49, 50, 51, the outputs of the ninth and twelfth binary discriminators 44, 47, and the outputs of the tenth and eleventh binary discriminators 45, 46, respectively. First and second exclusive OR circuits 52, 5 that generate x-direction error signals E _PU and E _PL
3, and the thirteenth and sixteenth binary discriminators 48, 5
1 and the fourteenth and fifteenth binary discriminator 4
Error signals in the y direction from the outputs of 9 and 50, respectively.
The eight-phase demodulator according to claim 1, further comprising third and fourth exclusive OR circuits 54 and 55 that generate EQU _{and EQL} .