JPH0270542U

JPH0270542U -

Info

Publication number: JPH0270542U
Application number: JP14848088U
Authority: JP
Priority date: 1988-11-16
Filing date: 1988-11-16
Publication date: 1990-05-29

Description

[Brief explanation of the drawing]

第１図は本考案の実施例を示す遅延検波回路の
構成ブロツク図、第２図は従来の遅延検波回路の
構成ブロツク図、第３図は従来の遅延検波回路の
構成ブロツク図である。１……入力端子、２，３……ミキサ、４……移
相器、５……局部発振器、６，７……低域フイル
タ、８，９……ＡＤ変換器、１０，１１……遅延
回路、１２，１３，１４，１５……乗算器、１６
，１７……加算器、１８，１９……出力端子。 FIG. 1 is a block diagram of a delay detection circuit showing an embodiment of the present invention, FIG. 2 is a block diagram of a conventional delay detection circuit, and FIG. 3 is a block diagram of a conventional delay detection circuit. 1...Input terminal, 2,3...Mixer, 4...Phase shifter, 5...Local oscillator, 6,7...Low pass filter, 8,9...AD converter, 10,11...Delay Circuit, 12, 13, 14, 15... Multiplier, 16
, 17... Adder, 18, 19... Output terminal.

補正平１．８．８実用新案登録請求の範囲を次のように補正する
。Amendment 8/8/199 The scope of claims for utility model registration is amended as follows.

【実用新案登録請求の範囲】アナログ信号と、その搬送波周波数と同じ周波
数で互いに位相が９０度異なる２つの局部搬送波
とをそれぞれ乗算する手段２〜５と、それぞれの乗算出力の高調波成分を除去し、そ
れぞれをデイジタル信号へ変換する手段６〜９と
、それぞれの当該デイジタル信号を１単位時間の
遅延操作を行なう手段１０，１１と、遅延前の２つの前記デイジタル信号と遅延後の
２つのデイジタルと２つずつ乗算し、それら２つ
の乗算結果の和を出力し且つ他の２つの乗算結果
の差を出力する手段１２〜１７とを備え、それら和と差の組み合せによつて検波出力を得
ることを特徴とした遅延検波回路。[Claims for Utility Model Registration] Means 2 to 5 for respectively multiplying an analog signal by two local carrier waves having the same frequency as the carrier wave frequency and having a phase difference of 90 degrees from each other, and removing harmonic components of the respective multiplication outputs. and means 6 to 9 for converting each digital signal into a digital signal; means 10 and 11 for delaying each digital signal by one unit time; and two digital signals before delay and two digital signals after delay. and means 12 to 17 for multiplying by two, outputting the sum of the two multiplication results and outputting the difference between the other two multiplication results, and obtaining a detection output by the combination of the sum and difference. A delay detection circuit characterized by:

Claims

[Claims for Utility Model Registration] Means 2 to 5 for respectively multiplying an analog signal by two local carrier waves having the same frequency as the carrier wave frequency and having a phase difference of 90 degrees from each other, and removing harmonic components of the respective multiplication outputs. and means 6 to 10 for converting each into a digital signal.
and means 10 and 11 for delaying each of the digital signals by one unit time; multiplying the two digital signals before the delay and the two digital signals after the delay two by two, and multiplying the two digital signals by two, and multiplying the two digital signals by two after the delay, and multiplying the two digital signals by two after the delay. A delay detection circuit comprising means 13 to 16 for outputting a sum and a difference between two other multiplication results, and obtaining a detection output by a combination of the sum and difference.