JP2950351B2 - Pulse signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse signal generating circuit for generating a digital clock pulse signal by detecting and compensating for a phase shift occurring in an analog input clock signal for generating a digital clock pulse.

[0002]

2. Description of the Related Art In general, a clock supply device in a network configuration for backbone transmission sends a stable reference clock signal to various devices in a station. Since only an interface for transmitting a reference clock signal is interposed between the clock supply device and various devices, information on a transmission clock on the transmission side and information on a failure on the clock supply side are not recognized on the clock reception side. I do not know at present.

As means for transmitting information on the transmitting side to the receiving side, it is considered to provide a dedicated line for transmitting the information in question, but all means between the clock supply device and the clocked supply device are considered. If a new signal transmission / reception circuit is provided and a dedicated cable connecting them is provided, a physically large space is required and the cost becomes enormous. Therefore, it is desirable to provide a method of establishing synchronization of a clock signal already transmitted to each device and carrying information.

In such a case, when a receiving side receives an analog input clock signal for generating a digital clock pulse and A / D converts the analog input clock signal and treats it as a digital clock pulse waveform, a pulse signal generating circuit as shown in FIG. Is used.

In this pulse signal generating circuit, the input terminal 1
The voltage level of the analog input clock signal A input from the reference power supply unit 6 is
Comparison with the reference voltage level from
The pulse generation circuit 5 generates two different logic levels according to the absolute value of the voltage level difference between the two signals, and A / D converts the analog input clock signal according to each of these logic levels to generate and output a predetermined period. The digital clock pulse signal D is output to the output terminal 2. Here, the two logical levels are usually binarized 0 and 1, and these binary 0 and 1 indicate the rising (or falling) timing of the rectangular wave when the digital clock pulse signal D is generated. Used to indicate.

[0006]

In the case of the above-described pulse signal generation circuit, the digital clock pulse signal D output from the output terminal is shown in FIG. 4 showing an example of input / output waveforms in the pulse signal generation circuit of FIG. If the analog input clock signal A is a sine wave, and if the analog input clock signal A often has a phase shift, the period T of the digital clock pulse signal D generated as a reference clock signal to be synchronized T1, t2, t
, Tn (t1 <t2 <t3..., <Tn), the phase shift (jitter) increases and the cycle T of the digital clock pulse signal D is varied.

In a conventional pulse signal generating circuit, a phase-locked oscillator or the like is required to remove such unnecessary phase shift.

By the way, a technique related to a phase-locked oscillator for suppressing and removing jitter in a received signal is as follows.
For example, Japanese Patent Application Laid-Open Nos. 62-20442 and 62-1
As disclosed in Japanese Patent No. 49232 and Japanese Patent Application Laid-Open No. 3-119882, if a phase-locked oscillator is provided, the pulse signal generating circuit itself becomes expensive and the scale of the entire circuit becomes large. Then its use is not desired.

The present invention has been made to solve such a problem, and its technical problem is that a phase shift occurs in an analog input clock signal with a simple configuration without using a phase locked oscillator. It is another object of the present invention to provide a pulse signal generation circuit capable of generating and outputting a digital clock pulse signal by sufficiently removing a phase shift.

[0010]

According to the present invention, a phase shift is detected from an analog input clock signal for generating a digital clock pulse, and the phase shift is determined based on a voltage level having a predetermined gradient corresponding to the phase shift obtained. A phase shift detection / comparison signal generation circuit for generating a comparison signal, and a delay for delaying an analog input clock signal and generating an analog delay clock signal for a time equal to the time required for the phase shift detection and the comparison signal generation processing The analog delayed clock signal is A / D-converted according to the voltage level difference obtained by comparing the voltage level of the comparison signal and the analog delayed clock signal with the circuit.
A voltage comparison / pulse generation circuit for generating and outputting a digital clock pulse signal having a predetermined period, wherein the voltage comparison / pulse generation circuit converts a voltage level difference from a voltage level of the analog delay clock signal. A pulse signal generating circuit for obtaining the absolute value obtained by subtracting the voltage level of the comparison signal and for compensating and controlling the timing of the rectangular wave when the digital clock pulse signal is generated in accordance with two different logical levels generated according to the voltage level difference is obtained. Can be

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG.
1 shows a configuration of a pulse signal generation circuit according to one embodiment of the present invention.

The pulse signal generating circuit is connected to the input terminal 1 and has a predetermined gradient corresponding to the phase shift amount obtained by detecting the phase shift from the analog input clock signal A for generating a digital clock pulse. A phase shift detection / comparison signal generation circuit 3 for generating a comparison signal B based on a voltage level, and an analog circuit connected to the input terminal 1 for a time equal to the time required for the phase shift detection and comparison signal generation processing A delay circuit 4 for delaying the input clock signal A to generate an analog delayed clock signal A 'is connected to the output terminal 2 and obtained by comparing the voltage levels of the comparison signal B and the analog delayed clock signal A'. The analog delayed clock signal A ′ is changed to A according to the voltage level difference.
/ D conversion and a digital clock pulse signal C having a predetermined period
And a voltage comparison / pulse generation circuit 5 for generating and outputting

Here, the voltage comparison / pulse generation circuit 5
The voltage level difference is obtained as an absolute value obtained by subtracting the voltage level of the comparison signal B from the voltage level of the analog delayed clock signal A ', and the digital clock pulse signal C is generated according to two different logic levels generated according to the voltage level difference. At the time of occurrence, the rising (or falling) timing of the rectangular wave is compensated and controlled.

The operation of the pulse signal generating circuit will be described below. However, here, the analog input clock signal A of the initially frequency f ₁ contains a very small component of the phase shift of the frequency f ₂ with respect to the frequency f _1.

First, the analog input clock signal A input from the input terminal 1 is input to the phase shift detection / comparison signal generation circuit 3, which outputs the phase shift detection / comparison signal generation circuit 3.
Detects the amount of phase shift. As the phase shift detection / comparison signal generation circuit 3, a circuit such as a demodulator having a function of extracting the phase shift amount of the main signal may be used. The comparison signal B extracted by the phase shift detection / comparison signal generation circuit 3 at a voltage level having a predetermined gradient according to the phase shift amount is input to the voltage comparison / pulse generation circuit 5.

On the other hand, the analog input clock signal A is also input to the delay circuit 4, and the delay circuit 4 has a time equal to the time required for the phase shift detection / comparison signal generation circuit 3 to detect the phase shift and generate the comparison signal. Only by delaying the analog input clock signal A, an analog delay clock signal A ′ is output. This analog delayed clock signal A ′ is input to the voltage comparison / pulse generation circuit 5.

In the voltage comparison / pulse generation circuit 5, the voltage level difference between the comparison signal B and the analog delay clock signal A 'is calculated by subtracting the voltage level of the comparison signal B from the voltage level of the analog delay clock signal A'. After that, two different logic levels (FIG. 4)
As described above, the binarized 0, 1) is generated, and the rising (falling) timing of the rectangular wave is compensated and controlled when the digital clock pulse signal C is generated according to these two logical levels. .

Here, in the process of increasing the phase shift of the analog input clock signal A, focusing on the rise of the digital clock pulse signal D with respect to the rectangular wave,
Since the change in the phase shift corresponds to the change in the voltage level of the comparison signal B, referring to FIG. 2 showing an example of input / output waveforms in the pulse signal generation circuit of FIG. The digital clock pulse signal C generated based on the voltage level difference obtained by subtracting the voltage level of the comparison signal B from the voltage level of the signal A ′ is
The phase shift is compensated for the rising edge of the analog delay clock signal A '(the same applies to the analog input clock signal A).

That is, the voltage comparison / pulse generation circuit 5 generates a positive pulse for a certain period of time after the rising edge of the analog delayed clock signal A 'required for generating the digital clock pulse signal C is detected. The digital clock pulse signal C can be obtained as a rectangular wave having a uniform duty and a duty ratio of 50%.

[0020]

As described above, according to the pulse signal generation circuit of the present invention, a phase shift that can occur in an analog input clock signal is detected, and a comparison signal corresponding to the phase shift amount is generated and output. A phase shift detection / comparison signal generation circuit is provided, and the analog input clock signal is delayed by a delay circuit for a time equal to the processing time required for detection of the phase shift and generation of the comparison signal to obtain an analog delay clock signal. A digital clock in which a voltage comparison / pulse generation circuit generates two different logic levels in accordance with the voltage level difference of each signal from these two circuits, and compensates for and removes a phase shift in accordance with the two different logic levels. Since a pulse signal is generated and output, the analog input clock signal of a sine wave is not phase-shifted, such as low frequency, as in the past. It is also be able to generate output digital clock pulse signal having a constant period without incurring the influence of the phase shift occurs. As a result, the accuracy and reliability of establishing the synchronization of the reference clock signal in the communication network including the transmitting device and the receiving device including such a pulse signal generating circuit are improved.

[Brief description of the drawings]

FIG. 1 shows a configuration of a pulse signal generation circuit according to one embodiment of the present invention.

FIG. 2 shows an example of input / output waveforms in the pulse signal generation circuit shown in FIG.

FIG. 3 shows a configuration of a conventional pulse signal generation circuit.

4 shows an example of input / output waveforms in the pulse signal generation circuit shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input terminal 2 Output terminal 3 Phase shift detection / comparison signal generation circuit 4 Delay circuit 5 Voltage comparison / pulse generation circuit 6 Reference power supply section A Analog input clock signal A 'Analog delay clock signal B Comparison signal C, D Digital clock pulse signal

Claims (1)

(57) [Claims] 1. A phase shift detection / comparison for generating a comparison signal based on a voltage level having a predetermined gradient corresponding to the phase shift amount obtained by detecting a phase shift from an analog input clock signal for generating a digital clock pulse. A signal generation circuit, a delay circuit for delaying the analog input clock signal for a time equal to a time required for the detection of the phase shift and the processing for generating the comparison signal, and generating an analog delayed clock signal; A voltage comparison / pulse generation circuit for A / D converting the analog delay clock signal according to a voltage level difference obtained by comparing the voltage levels of the analog delay clock signal to generate and output a digital clock pulse signal having a predetermined period; In the pulse signal generation circuit including: a voltage comparison / pulse generation circuit, the voltage comparison / pulse generation circuit An absolute value obtained by subtracting the voltage level of the comparison signal from the voltage level of the log delay clock signal is obtained.
A pulse signal generating circuit for compensating and controlling the timing of a rectangular wave when the digital clock pulse signal is generated in accordance with one of the logical levels.