JPH08256138A - Clock extraction circuit - Google Patents

Abstract

PURPOSE: To quickly and stably output a clock that is synchonous with the received data in a data transmission mode of a subordinate synchronous system. CONSTITUTION: A phase comparator 12 compares the received data Ri (Rn , Rn-1 ...R1 ) with the clocks Ti (Tn , Tn-1 ...T1 ) which are outputted from a phase control part 15 for every clock and outputs the phase differences δ1 (δn , δn-1 ...δ1 ) set between the data Ri and clocks Ti . These phase differences are held at a phase difference holding part 13. A phase difference management part 14 outputs a phase control signal based on the differences δi , and the control part 15 controls the phases of clocks Ti based on the phase control signal. The part 14 performs an operation by means of the phase differences δi equivalent to optional N pieces of clocks and uses this arithmetic condition as a phase control signal to control the phases of output clocks Ti .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock extraction circuit in data transmission of a slave synchronization system.

[0002]

2. Description of the Related Art Conventionally, in data transmission of a slave synchronization system, a receiving device (slave device) extracts a synchronization clock from received data in order to receive data transmitted from a transmitting device (master device). Receive data. Here, a digital PLL (Phase-Locked Loop) circuit is often used to extract a clock synchronized with the received data.

FIG. 4 is a diagram for explaining an example of a digital PLL circuit. As is well known, the phase comparator 1 compares the phase of received data with the phase of an output clock and outputs a phase difference. The output phase difference is judged by the phase difference management unit 2 to be “phase lead” or “phase delay”. The phase difference counter 3 counts and accumulates the number of outputs of "phase lead" and "phase delay". When the counter value of the phase difference counter 3 reaches a preset value K, the phase controller 4 “advances” or “delays” the phase of the output clock and outputs a clock synchronized with the received data. To do. The follow-up time and stability are set by the value K. It is generally known that a larger value K extracts a stable clock against noise and jitter, but too large a value causes out-of-sync. Further, in the terminal connected to the basic interface of the ISDN network, the digital PLL circuit is used similarly to the above.

[0004]

In the basic interface of the ISDN network, the transmission code has 100% duty AMI.
(Alternate Mark Invention) code is adopted.
FIG. 5 is a diagram for explaining this coding rule. As is well known, data “0” is made to correspond to alternating + and − amplitudes, and data “1” is made to correspond to no amplitude. ing. Therefore, in order to extract the clock synchronized with the received data, the received data must include the data "0". The synchronous clock cannot be extracted only with the data "1". Therefore, when the digital PLL circuit is used, the value of the value K that determines the stability is determined as the worst value when the data "0" is the least in the received data. That is, the value of K must be set small so that even a small number of "0" s can be followed quickly. However, although this value has a short follow-up time, there is a problem in that it cannot be said that the stability against noise, jitter, etc. is a sufficient value.

The present invention has been made in view of the above situation, and in the data transmission of the slave synchronization system, particularly in the basic interface of the ISDN network, the clock synchronized with the received data is promptly and stably output. The present invention has been made for the purpose of providing a clock extraction circuit that operates.

[0006]

According to the present invention, in order to solve the above-mentioned problems, (1) reception data R _i (R _n , R _n-1 ,
, R ₁ ) and the clock T _i (T ₁ ) output from the phase controller
_{n, T n-1, ...} , T 1) and compared with each clock, the phase difference [delta] _i ([delta] _n of the received data R _i and the output clock T _{i, δ n-1,}
..., a phase comparator for outputting a [delta] _1), and the phase difference holding unit that holds a plurality of the phase difference [delta] _i, the phase difference control section for outputting a phase control signal using the phase difference [delta] _i that the holding, In the data transmission circuit of the subordinate synchronization system, which has a phase control unit that controls the phase of the output clock T _i according to the phase control signal output from the phase difference management unit, the phase difference management unit includes any of the held Phase difference δ for N clocks
_i is used to perform some calculation, and the calculation condition is used as a phase control signal to control the phase of the output clock T _i of the phase control unit.
(2) The following equation (1) is used as the calculation condition:
(3) The following formula (2) is used as the phase control signal.

[0007]

(Equation 3)

[0008]

The received data R _i (R _n , R _n-1 , ..., R ₁ ) and the clock T _i (T _n , T _n-1 , ...
T ₁ ) for each clock to obtain a phase difference δ _i (δ _n , δ _n-1 , ..., δ ₁ ) between the received data R _i and the output clock T _i , and hold a plurality of this phase difference δ _i. Then, some operation is performed using the held phase difference δ _i for N clocks, and the phase of the output clock T _i is controlled by using the operation condition as a phase control signal.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram for explaining one embodiment of the present invention, which shows an example in the case of being adapted to a terminal connected to a basic interface of an ISDN network. In FIG. 1, the receiver 11 receives data R _i from the ISDN network.
The AMI code of (R _n , R _n-1 , ..., R ₁ ) is set to “0”,
Convert to a digital signal of "1". The phase comparator 12 compares the phase of the clock signal T _i output from the phase controller 15 with the reception data R _{i for} each clock, and outputs the phase difference δ _i . The phase difference holding unit 13 is a storage device such as a memory that holds the phase difference δ _i output from the phase comparator 12.
The phase difference management unit 14 performs some calculation using the phase difference δ _i held in the phase holding unit 13 and outputs a phase control signal such as “advance” or “delay” the phase, a digital signal processor. , An arithmetic processing unit such as a hard logic. The phase controller 15
Based on the phase control signal from the phase difference management unit 14, the reference clock 16 is used to control the phase of the output clock T _i . The reference clock 16 is a sampling clock for synchronizing with the received data and for outputting the phase difference δ _i as a digital signal in the phase comparator 12, and takes a fraction of the received data. , The clock of 1/40 of the received data.

Received AMI code from the ISDN network (see FIG. 2).
2A, in the receiver 11, as shown in FIG. 2B, the + vibration and the − vibration signals are converted into the reception digital signal R _i of “1”, and the AMI signal of 0 level is “. 0 "received digital signal R _i is converted. next,
In the phase comparator 12, the received digital signal R _i
As shown in FIG. 3, the phase difference δ _i between (FIG. 2B) and the clock T _i output from the phase controller 15 is −19 to +.
It is output as a digital value of 20 every output clock. That is, the rising position of the received digital signal R _i is detected by sampling the received digital signal with the reference clock during one output clock T _i (40 reference clock), and the detected position within the output clock is Digital values (-19 to -1,0,
1 to 20) and output as the phase difference δ _i .
This detection position is the count value of the reference clock in the output clock period whose starting point is the rising edge of the output clock and whose initial value is -19. Here, when the rising position of the received digital signal is not detected, the phase difference Δ _{i is set} to the preceding phase difference _i−1 .

As described above, the phase difference δ _i output for each output clock is sequentially stored in the phase difference holding unit 13. Next, in the phase difference management unit 14, some calculation (for example, Expression (1)) is performed using the stored phase difference sequence δ, and a phase control signal for determining the phase position of the newly output clock is generated. Output. In this case, for example, the newer the phase difference data, the greater the influence on the phase difference to be output next. Therefore, as shown in Equation 2, the past phase difference is lightly weighted, and the heavier weighting is applied toward the new phase difference. Then, the weighted average value is calculated. That is, the phase difference of T _{i + 1} is predicted by the equation 2, and a phase control signal such as “advance” or “delay” the phase of the output clock by what reference clock is output. Then, the phase of the output clock is controlled based on the phase control signal output from the phase difference management unit 14, and the output clock is output. By the series of processes described above, it becomes possible to quickly and stably output the clock synchronized with the received data.

[0012]

[Equation 4]

[0013]

As described above, according to the present invention, the past phase difference data is retained, the phase difference data is subjected to some arithmetic processing, and the phase of the newly output clock is predicted. Therefore, the clock synchronized with the received data can be output promptly and stably.

[Brief description of drawings]

FIG. 1 is an electric circuit diagram for explaining an embodiment of the present invention.

FIG. 2 is a diagram for explaining an example of conversion from an AMI code to a digital signal.

FIG. 3 is a diagram showing an output example of phase difference data δ.

FIG. 4 is a configuration diagram of a digital PLL circuit.

FIG. 5 is a diagram for explaining a coding rule of a 100% duty AMI code.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Phase comparator, 2 ... Phase difference management part, 3 ... Phase difference counter, 4 ... Phase control part, 11 ... Receiver, 12 ... Phase comparator, 13 ... Phase difference holding part, 14 ... Phase difference management part, 15 …
Phase controller, 16 ... Reference clock.

Claims (3)

[Claims] 1. Received data R _i (R _n , R _n-1 , ..., R ₁ )
And a clock T _i (T _n ,
_{T n-1, ..., T} 1) and compared with each clock, the phase difference [delta] _i ([delta] _n of the received data R _i and the output clock _{T i, δ n-1,} ...,
a phase comparator for outputting a [delta] _1), and the phase difference holding unit that holds a plurality of the phase difference [delta] _i, the phase difference control section for outputting a phase control signal using the phase difference [delta] _i that the holding, the position In the data transmission circuit of the subordinate synchronization system, which has a phase control unit that controls the phase of the output clock T _i according to the phase control signal output from the phase difference management unit, the phase difference management unit includes
Some operation is performed using the held phase difference δ _i for N clocks, and the phase of the output clock T _i of the phase control unit is controlled by using the operation condition as a phase control signal. Clock extraction circuit. 2. The clock extraction circuit according to claim 1, wherein the following expression 1 is used as the calculation condition. [Equation 1] Here, when the phase difference is larger than one clock period (360
Or more), and δ _i = δ _i-1 . i is the output order, δ
_i is the phase difference between the received data R _i and the output clock T _i in the clock T _i. 3. The clock extraction circuit according to claim 1, wherein the following formula 2 is used as the phase control signal. [Equation 2] Here, when the phase difference is larger than one clock period (360
Or more), and δ _i = δ _i-1 . i is the output order, δ
_i is the phase difference between the received data R _i and the output clock T _i in the clock T _i.