JPH08316948A - Bit synchronization circuit, and bit synchronization method - Google Patents

Abstract

PURPOSE: To provide a bit synchronization circuit and method which have no influences upon circuits in the succeeding stage and have a large phase margin in the synchronism holding state and can be stably operated. CONSTITUTION: Based on the output value or a reversible counter 7, a variable delay part 1 inserts variable delay to reception data 11 to generate output data 13. A change point detection part 2 generates change point phase signals 16 and 17 of reception data and output data. A phase comparison part 3 compares phases of output data 13 and a reference clock 12 with each other to generate a phase comparison signal 18, and a control part 6 generates a control signal 21, which control the operation of the reversible counter 7, based on the phase comparison signal 18 and a one period detection signal 19 outputted from a one period detection part 4. When detecting the continuity or the same code of output data 13 (detecting that the code of the same value is continuous), a same code detection part 5 stops the operation of the reversible counter 7 to fix the extent of delay to be inserted to reception data 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit synchronizing circuit for synchronizing the phase of data transmitted between devices for transmitting and receiving a signal and the phase of a reference clock on the receiving side when transmitting a digital signal. .

[0002]

2. Description of the Related Art An apparatus for synchronizing the phase of transmitted / received data and the phase of a reference clock is disclosed in, for example, Japanese Patent Application No. 5-3.
No. 06678. A configuration block diagram of the bit synchronization circuit shown here is shown in FIG. As shown in FIG. 16, the variable delay unit 1
Generates an output clock 12a by changing the delay amount inserted in the reception clock 23 based on the count signal 14 output from the reversible counter 7. On the other hand, the change point detection unit 2
The point a detects the change point of the received data and generates the received data change point phase signal 17. The phase comparator 3c compares the phase of the received data change point phase signal 17 with the phase of the output clock 12a, and inspects whether the phase is advanced or delayed. Then, the phase comparison unit 3c generates the phase comparison signal 18c which is the result of the inspection. The one-cycle detection unit 4a detects that the delay amount in the variable delay unit 1 is one cycle, based on the reception clock 23 and the output clock 12a, and the one-cycle detection signal 19 indicating this.
Generate

The synchronization determination section 5a determines the synchronous / asynchronous state from the received data 11 and the output clock 12a, and generates a synchronization determination signal 20a. Further, it is detected that the same code continuously appears in the received data, and the synchronization determination signal 20a indicating that the same code continuously appears has the same output value as that in the synchronized state. The control unit 6 generates the control signal 21 based on the phase comparison signal 18c from the phase comparison unit 3c, the 1-cycle detection signal 19 from the 1-cycle detection unit 4a, and the count signal 14 from the reversible counter 7. Further, the reversible counter 7 performs a counting operation and outputs a count signal 14 according to the control signal 21 output from the control unit 6 and the synchronization determination signal 20a output from the synchronization determination unit 5a.

The bit synchronization circuit according to the first conventional example employs a method of controlling the phase of the reception clock to synchronize the phase of the output clock with the phase of the reception data. This method is called a multi-phase clock type bit synchronization method.

FIG. 17 shows a conventional example 1 shown in FIG.
2 is a diagram showing a specific circuit diagram of the change point detection unit 2
a, phase comparison unit 3c, synchronization determination unit 5a, 1 period detection unit 4
The specific circuit for a is shown in detail.

As shown in FIG. 17, the change point detection unit 2a converts the received data 11 by the exclusive OR circuit 202 and the received data T / 2 by the delay element 201.
(Here, T represents one clock cycle) The exclusive OR of the delay data and the inserted data is used to detect the rising and falling transition points of the received data 11. Then, based on this detection, the reception data change point phase signal 17 is generated by the exclusive OR circuit 202.
The received data change point phase signal 17 rises at the position of the data change point, and its pulse width is determined by the delay time of the delay element 201.

Next, as shown in FIG. 17, the phase comparing section 3c outputs the received data change point phase signal 17 from the change point detecting section 2 to the output clock 12a and its inverted clock in the flip-flops 301 and 302, respectively. The phase comparison signals 181c and 182c are respectively generated by the (clocks whose phases are inverted). The value of the combination with the phase comparison signals 181c and 182c represents the so-called advance / delay state of the clock. For example, when (181c, 182c) = (H, L), the phase of the output clock 12a is the received data 1
Represents progressing toward 1. In addition, (181c,
182c) = (L, H), output clock 1
2a indicates that the phase of 2a is behind the received data 11.

Next, as shown in FIG. 17, the one-cycle detector 4a uses the flip-flops 401 and 402 to identify the receive clock 23 for two cycles at the rising timing of the output clock 12a. As a result, the logical sum of the positive-phase output of the flip-flop 401 and the negative-phase output of the flip-flop 402 is obtained.
The 1-cycle detection signal 19 is generated. The one-cycle detection signal 19 is a signal that becomes "L" level only for one cycle when the rising edge of the output clock 12a detects the falling edge of the reception clock 23.

Next, as shown in FIG. 17, the synchronism determining section 5a converts the received data into T by the delay element 504.
Data with a delay of / 4 is flip-flop 501
And 502 respectively fetch at the timing of the output clock and its inverted clock, and after the phases are aligned by the flip-flop 505, the exclusive OR is taken. In this way, the synchronization determination signal 20a is finally generated. This synchronization determination signal 20a is the output clock 1
If the rising timing of 2a is within the range of T / 4 to 3T / 4 from the change point of the received data 11, it is determined to be synchronous. When it is out of the range, it is determined to be asynchronous. It is to be noted that if it is determined to be synchronous, it becomes "L" level, and if it is determined to be asynchronous, this synchronization judgment signal 20a becomes "H" level.

Next, the control section 6 controls the phase comparison signals 181c and 182c from the phase comparison section 3c and the 1-cycle detection section 4a.
A control signal 21 for controlling the counting operation of the reversible counter 7 is generated based on the one-cycle detection signal 19 output by the reversible counter 7 and the count signal 14 output by the reversible counter 7. When the combination of the phase comparison signals 181c and 182c is (H, L), the control signal 21 indicates a count-up because the clock is in the advanced state, and conversely, when it is "L, H", it is delayed. Since it is in the state, it becomes a value indicating the countdown. Furthermore, when the control signal 21 is in the advanced state and one cycle is detected by the one cycle detection unit 4a, the control signal 21 indicates a reset to set the count signal 14 of the reversible counter 7 to "0", and the delayed state and the count Signal 14 is 0
If it is, the count signal 14 becomes a value indicating a load for setting it to a preset value.

The reversible counter 7 up-counts, down-counts, or resets when an asynchronous state is detected based on the control signal 21 output from the control unit 6 and the synchronization determination signal 20a output from the synchronization determination unit 5a. Also, a counting operation such as loading is performed and a count signal 14 is output. Further, the counting operation is stopped at the time of synchronization determination and at the same code consecutive detection of the received data.

A detailed configuration block diagram of the variable delay section 1 is shown in FIG. As shown in FIG. 18, the decoder 101 uses the count signal 1 from the reversible counter 7.
On the basis of 4, the decode signal is generated. Selector 10
2 selects one of the input with the delay element 103 inserted and the input signal with no delay element 103 based on this decoded signal. As shown in FIG. 18, this combination of selector 102 and delay element 103 is connected to a plurality of decoders 101, and each select 102 is based on a signal from the decoder.
The signal is sent to the set of the selector 102 and the delay element 103 at the next stage by selecting either the signal that has passed or not passed. In this way, the delay amount added to the reception clock 23 is controlled and finally output as the output clock 12a. That is, when the value of the count signal 14 increases, the delay time is increased and the phase of the output clock 12a is delayed. On the other hand, when the value of the count signal 14 decreases,
The delay time is reduced and the phase of the output clock 12a is advanced.

FIG. 19 is a time chart for explaining the operation of the bit synchronization circuit. Reception clock 23
On the other hand, when the output clock 12a is in the delay state as shown in FIG. 19, when the value of the count signal 14 is represented by i, the reception data 11 is input to the synchronization determination unit. In 5a, it is determined that the rising timing of the output clock 12a is not within the range of T / 4 to 3T / 4 from the change point of the received data 11, that is, asynchronous. As a result, the value of the synchronization determination signal 20a becomes "H" level. Next, the change point detection unit 2a generates a received data change point phase signal 17 based on the received data 11.

In the phase comparison section 3c, the received data change point phase signal 17 is identified by the output clock 12a, and the combination of the phase comparison signals 181c and 182c is (181).
c, 182c) = (H, L). As a result, the advanced state is detected.

Since the reversible counter 7 is in the advanced state, it is sequentially incremented from the initial state i. The variable delay unit 1 increases the delay amount sequentially inserted into the reception clock 23 based on the count signal 14,
The output clock 12a will be delayed. When the count signal 14 becomes i + 4, the synchronization determination unit 5a determines that synchronization has occurred, as shown in FIG. Based on the determination that this is the synchronization, the counting operation is stopped at the next rising timing of the clock, and this synchronized state is held.

As described above, in the example shown in FIG. 19, the phase of the reception clock is controlled to synchronize the phase of the output clock with the phase of the reception data.

An example of another type of bit synchronization circuit is shown in FIG. As a document relating to such a conventional bit synchronization circuit, "International Z
urich Seminar on Digital
Communications, C4, 1986 ”. As shown in FIG. 20, the variable delay unit 1b inputs the reception data 11, and the polyphase conversion unit 104 uses n delay elements (n is a positive integer) having a delay time of T / n to n. The delay data 15 is generated with the given delay.
The selector 102 selects one of the n delay data 15 based on the count signal 14 output by the reversible counter 7 and outputs the output data 13. The reversible counter 7 performs a counting operation by using the output data 13 from the variable delay unit 1b as a clock input, and the reference clock 12 is “H” at the rising timing of the output data 13.
If the reference clock 12 is "L" at the rising timing of the output data 13, the countdown operation is performed, and the count signal 14 is output in this manner. .

In the bit synchronization circuit of the second conventional example, the data after the fixed delay time is inserted is used as the clock input of the reversible counter 7 and the reference clock is used as the control input of the reversible counter 7 to receive data. Is controlled to synchronize the phase of the output data with the phase of the reference clock. This method is called a polyphase data type DPLL method.

FIG. 21 is a time chart showing the operation of the bit synchronization circuit shown in FIG. First, for the received data 11, n delay data 15 are generated. The output data 13 is shown in FIG.
Count signal 1 in the delay state as shown in
When the value of 4 is i, when the reference clock 12 is input, the reversible counter 7 counts from the initial state i because the reference clock 12 is “H” at the first rising edge of the output data 13. Do up. As a result, the count signal 14 becomes i + 1, and the count-up operation is continued while the reference clock 12 is "H" at the rising edge of the output data 13.

Next, the selector 102 sequentially selects the next delay data 15 based on the count signal 14. Then, when the count signal 14 becomes i + 2, the position of the change point of the output data 13 is changed to the reference clock 12
The reference clock 12 becomes "L" at the next rising edge of the output data 13 beyond the falling edge of the. The reversible counter 7 counts down and the count signal 14 becomes i + 1. The selector 102 selects the immediately preceding delay data according to the count signal 14. When the count signal 14 becomes i + 1, the position of the change point of the output data 13 is again "H" of the reference clock 12.
Since it comes to the section, the counter counts up at the next rising edge of the output data 13. In this way, thereafter, the reversible counter 7 alternately repeats the count-up and the count-down at the rising timing of the output data 13 to hold the synchronized state.

As described above, in the second conventional example, the phase of the received data is controlled and the phase of the output data is synchronized with the phase of the reference clock.

Further, as another conventional example, there is a circuit as shown in B-830, Proceedings of Autumn Meeting of the Institute of Electronics, Information and Communication Engineers, 1993. The circuit shown here is different from the above-mentioned two conventional examples 1 and 2 in the following points.

That is, the bit synchronization circuit shown in the above-mentioned abstract includes a shift register which receives a high-speed clock signal and operates as a multi-phase conversion section with a high-speed clock. By using this shift register, the received data is multiphased without using a delay element. Further, it is provided with a frequency divider for dividing the high speed clock to generate a reference clock, and the reversible counter uses the reference clock as a control input to perform the same operation as that shown in FIG. To do. The divided clock is also output outside the circuit. The reversible counter has an initial phase set by a reset signal from the outside of the circuit.

Other configurations and operations of the bit synchronization circuit described in the above-mentioned proceedings are the same as those of the conventional example 2 shown in FIG. That is, the same configuration as that of the conventional example 2 shown in FIG. 20 is adopted except for the two points that the received data is multi-phased using the high-speed clock and that the frequency divider is provided. .

In this way, the bit synchronization circuit shown in the above-mentioned proceedings multi-phases the received data by the shift register operating with a high-speed clock, controls the phase of the received data, and controls the phase of the output data. It is synchronized with the phase of the reference clock.

[0026]

As described above, the bit synchronization circuit according to the prior art 1 employs the method of controlling the phase of the reception clock to synchronize the phase of the output clock with the phase of the reception data. It was Therefore, there is a problem that the duty of the output clock fluctuates when the phase control is performed, and the timing margin is reduced in the circuit in the subsequent stage. Further, if the phase control is always performed, the time in which the duty of the output clock fluctuates becomes long, and the operation of the circuit in the subsequent stage becomes unstable, which is likely to occur. Therefore, there is a problem that the phase control cannot be continued until the optimum phase is obtained. Further, since the delay element is used in the variable delay unit, there is a problem in that an error and a change in the delay time occur due to variations in the delay amount and changes in the external environment.

In the bit synchronization circuit according to the above-mentioned conventional example, the data after the insertion of the predetermined delay amount is used as the clock input of the reversible counter, and the reference clock is further controlled and input to the reversible counter to receive the received data. The method of controlling the phase of was adopted. Therefore, when the phase control is performed, the output data becomes discontinuous, which causes a problem that a so-called spike is mixed in the clock input of the reversible counter and causes a malfunction. further,
There is a problem that it is necessary to set the initial phase of the reversible counter because the delay amount to be inserted into the received data is insufficient depending on the initial phase of the reversible counter.

The present invention has been made to solve the above problems, and the object thereof is to provide a multi-phase data type bit synchronization system capable of stable operation and having the following features. It is to be.

(A) Without affecting the circuit in the subsequent stage,
Controls data phase and provides synchronization.

(B) Phase control is performed until the optimum phase is obtained, and a large phase margin is obtained.

(C) It is possible to accurately provide a delay time between multi-phased data without causing an error and fluctuation in the delay time in the variable delay section.

(D) When performing phase control, no malfunction occurs even if the output data is discontinuous.

(E) The output data synchronized with the reference clock is generated with a delay amount of one cycle regardless of the value of the initial phase.

[0034]

In order to solve the above-mentioned problems, the first aspect of the present invention controls the phase of received data based on the phase relationship between output data and a reference clock so that the phase of the reference clock is set. In a bit synchronization circuit that outputs synchronized output data, a variable delay unit that generates the output data by changing a delay amount to be inserted into the received data based on a count value of a reversible counter, a phase of the output data, and the reference. The output data is discriminated from the output data by the reference clock for two cycles by comparing the phase of the clock with the phase comparison unit that detects a lead / lag state and generates a phase comparison signal. When the same-code continuous state that is the same over the cycle is detected, the same-code detection unit that generates the same-code detection signal and the phase comparison signal output by the phase comparison unit are used. A reversible counter for counting a reference clock, wherein the reversible counter stops its operation when the same sign detection section detects the same sign continuity of the output data. is there.

In order to solve the above problems, a second aspect of the present invention is the bit synchronization circuit of the first aspect of the present invention, further comprising:
A control unit that generates a control signal that controls resetting and loading of the reversible counter based on the phase comparison signal and a count value of the reversible counter, and the reversible counter operates based on the control signal. It is a bit synchronization circuit characterized by the above.

In order to solve the above-mentioned problems, a third aspect of the present invention is the bit synchronization circuit of the second aspect of the present invention, wherein the control section further generates a control signal for controlling the counting operation of the reversible counter, The reversible counter is a bit synchronizing circuit characterized by performing a reset operation and a load operation together with a counting operation based on the control signal.

In order to solve the above problems, a fourth aspect of the present invention provides a bit synchronization circuit according to the first, second and third aspects of the present invention,
Further, a change point detection for detecting respective change points of the reception data and the output data, and generating a reception data change point phase signal and an output data change point phase signal which rise at the timing when the respective data change points are detected. Section, the one cycle detection signal is generated when it is detected that the delay amount inserted in the received data is one cycle based on the received data change point phase signal and the output data change point phase signal. A 1-cycle detection unit, wherein the control unit includes the phase comparison signal, the 1-cycle detection signal,
A control signal for controlling the operation of the reversible counter is generated based on the count value of the reversible counter, and the control signal resets the reversible counter when the one-cycle detection signal is output. It is a characteristic bit synchronization circuit.

In order to solve the above-mentioned problems, a fifth aspect of the present invention is the bit synchronization circuit of the fourth aspect of the present invention, wherein the phase comparison section outputs the output data change point phase signal generated by the change point detection section. And based on the reference clock
The bit synchronization circuit is characterized in that the phase of the output data is compared with the phase of the reference clock to detect a lead / lag state, and the phase comparison signal is generated.

In order to solve the above-mentioned problems, a sixth aspect of the present invention is the bit synchronizing circuit of the fourth aspect of the present invention, wherein the phase comparison section uses the output data generated in the variable delay section and a reference clock. The bit synchronization circuit is characterized by directly comparing the phase of the output data with the phase of the reference clock to detect a lead / lag state and generating the phase comparison signal.

In order to solve the above problems, the seventh aspect of the present invention controls the phase of received data on the basis of the phase relationship between output data and a reference clock, and outputs output data synchronized with the phase of the reference clock. In the bit synchronization circuit for outputting, a variable delay unit that changes the delay amount to be inserted in the received data based on the count value of a reversible counter to generate the output data, and a change point of each of the received data and the output data are set. A change point detection unit that detects a received data change point phase signal and an output data change point phase signal that rise at the timing when each data change point is detected; and a phase of the output data and a phase of the reference clock. A phase comparison unit for comparing and detecting a lead / lag state to generate a phase comparison signal, the received data change point phase signal and the output Based on the data change point phase signal, when detecting that the delay amount inserted in the received data has reached one cycle, a one cycle detection unit for generating a one cycle detection signal, and the output data as the reference 2 by clock
A homo-code detection unit that generates a homo-code detection signal when a homo-code continuation state in which the value of the output data is the same over two cycles is detected, and the phase comparison signal; A control unit that generates a control signal that controls the operation of the reversible counter based on the one-cycle detection signal and the count value of the reversible counter, and an operation that is performed based on the control signal. And a reversible counter that stops its operation when the same sign continuity of output data is detected, and a bit synchronization circuit.

In order to solve the above-mentioned problems, an eighth aspect of the present invention includes, in the bit synchronization circuit of the first or seventh aspect of the present invention, a multiplication section for multiplying the reference clock to generate a multiplied clock. The variable delay unit uses the multiplied clock to generate a variable delay in which the delay time for one cycle of the multiplied clock is one unit, and changes the delay amount to be inserted into the received data based on the counter value of the reversible counter. The bit synchronization circuit is characterized by generating output data.

In order to solve the above-mentioned problems, a ninth aspect of the present invention provides a bit synchronizing circuit according to the first or seventh aspect of the present invention, which further comprises a frequency divider for dividing the reference high-speed clock to generate a reference clock. The variable delay unit generates a variable delay using the reference high-speed clock as a unit with a delay time corresponding to one cycle of the reference high-speed clock, and inserts a delay amount into the received data into a counter of the reversible counter. It is a bit synchronization circuit characterized in that output data is generated by changing it based on a value.

In order to solve the above problems, the tenth aspect of the present invention controls the phase of received data based on the phase relationship between output data and a reference clock and outputs data synchronized with the phase of the reference clock. In the bit synchronization method
A bit synchronization method characterized by including the following steps.

That is, (a) a variable delay insertion step of changing the delay amount to be inserted into the received data based on the count value of the reversible counter to generate output data,
(B) a phase comparison step of generating a phase comparison signal by comparing the phase of the output data with the phase of the reference clock; and (d) identifying the output data by the reference clock for two cycles and continuously outputting the same sign of the output data. And a homo-code continuity detection step of stopping the operation of the reversible counter at the time of homo-code continuity detection.

In order to solve the above problems, the 11th present invention is the bit synchronizing method according to the 10th present invention, which further includes the following steps.

That is, (a) a change point detecting step of detecting a change point of the received data and the output data and generating a received data change point phase signal and an output data change point phase signal,
(B) Based on the received data change point phase signal and the output data change point phase signal, it is detected that the delay amount inserted in the received data in the variable delay insertion step is one cycle, and 1 One cycle detection step of generating a cycle detection signal, and (c) a control step of controlling the operation of the reversible counter based on the phase comparison signal, the one cycle detection signal, and the count value of the reversible counter. It includes.

In order to solve the above problems, the twelfth aspect of the present invention is the bit synchronization method according to the eleventh aspect of the present invention, which further includes the following steps.

That is, (a) a reference clock multiplication step of multiplying a reference clock to generate a multiplied clock,
(B) Using the multiplied clock, a variable delay is generated with the delay time of one cycle of the multiplied clock as one unit,
A variable delay insertion step of changing the delay amount to be inserted into the received data based on the count value of the reversible counter to generate the output data.

In order to solve the above-mentioned problems, the 13th aspect of the present invention is the bit synchronization method according to the 11th aspect of the present invention, further including the following steps.

That is, (a) a dividing step of dividing the reference high-speed clock to generate the reference clock, and (b) using the reference high-speed clock, a delay time of one cycle of the reference high-speed clock is set to 1. A variable delay insertion step of generating a variable delay as a unit and changing the delay amount to be inserted into the received data based on the count value of the reversible counter to generate the output data.

[0051]

The bit synchronization circuit according to the first aspect of the present invention controls the delay amount to be inserted into the received data by comparing the phases of the output data and the reference clock, and further, the same code is continuously present in the output data. When it appears, that is, when the same code continues, the operation of the reversible counter is stopped, and the data synchronized with the reference clock is output without affecting the reference clock.

A bit synchronization circuit according to a second aspect of the present invention performs reset and load operations of a reversible counter. Therefore, it is not necessary to set the initial phase of the reversible counter.

The bit synchronizing circuit according to the third aspect of the present invention controls not only the counting operation of the reversible counter but also the reset and load operations. Therefore, it is not necessary to set the initial phase of the reversible counter.

A bit synchronizing circuit according to a fourth aspect of the present invention resets the reversible counter when the delay amount inserted in the received data in the variable delay section is one cycle. Therefore, the variable delay can be continuously changed even when there is variation or fluctuation in the delay time in the delay element.

The bit synchronizing circuit according to the fifth aspect of the present invention can perform the phase control until the optimum phase is reached.

In the bit synchronizing circuit according to the sixth aspect of the present invention, the phase of the output data and the phase of the reference clock are compared without using the delay element. Therefore, there is a feature that the phase comparison result is not affected by the fluctuation of the delay time.

A bit synchronizing circuit according to a seventh aspect of the present invention compares the respective phases of the output data and the reference clock, and controls the delay amount to be inserted in the received data. Further, when the same code appears consecutively in the output data, the operation of the reversible counter is stopped. Next, the delay amount inserted in the received data in the variable delay unit is exactly 1
The fact that the number of cycles has been reached is detected, and the reset and load operations of the reversible counter are controlled by this detection. for that reason,
It is possible to continuously change the variable delay even if the delay element varies or fluctuates in the delay element without affecting the clock.

Since the bit synchronization circuit according to the eighth aspect of the present invention generates a variable delay in which the delay time of one cycle of the multiplied clock is one unit and inserts it into the received data,
It is possible to give the variable delay accurately.

The bit synchronizing circuit according to claim 9 of the present invention generates a variable delay in which the delay time of one cycle of the reference high-speed clock is one unit, and inserts this into the received data.
Therefore, the variable delay can be accurately given.

In the bit synchronization method according to the tenth aspect of the present invention, the phases of the output data and the reference clock are compared with each other to control the delay amount to be inserted in the received data, and further the same in the output data. When the codes appear consecutively, the operation of the reversible counter can be stopped and the data synchronized with the reference clock can be output without affecting the reference clock.

In the bit synchronization method according to the eleventh aspect of the present invention, the reversible counter is reset when the delay amount inserted in the received data is one cycle. Therefore, it is possible to continuously change the variable delay even when there is variation or fluctuation in the delay time in the delay element.

According to the twelfth aspect of the present invention, the bit synchronization method generates a variable delay in which the delay time of one cycle of the multiplied clock is one unit and inserts it into the received data. for that reason,
A precise variable delay can be generated.

In the bit synchronization method according to the thirteenth aspect of the present invention, a variable delay having a delay time of one cycle of the reference high speed clock as one unit is generated and inserted into the received data. Therefore, it is possible to generate an accurate variable delay.

[0064]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 1 shows a block diagram of a bit synchronizing circuit which is a preferred embodiment of the present invention. As shown in FIG. 1, the variable delay unit 1 changes the delay amount to be inserted into the reception data 11 based on the count signal 14 output from the reversible counter 7 to generate the output data 13. The change point detection unit 2 detects a change point between the output data 13 and the received data 11 and rises at the timing of the point where the data changes, that is, the output data change point phase signal 16
Similarly, a reception data change point phase signal 17 which is a signal rising at the data change point of the reception data is generated. The phase comparison unit 3 outputs the output data change point phase signal 1
6 and the reference clock 12, the phases of the output data 13 and the reference clock 12 are compared. The lead / lag state is detected by this comparison, and the phase comparison signal 18 is generated. The 1-cycle detection unit 4 outputs the output data change point phase signal 16
It is detected that the delay amount in the variable delay unit 1 is one cycle based on the received data change point phase signal 17 and the one cycle detection signal 19 indicating this is output. The same code detection unit 5 detects, based on the output data 13 and the reference clock 12, the same code continuity (that consecutive codes having the same value appear consecutively) of the output data and detects the same code detection signal 2.
Generates 0.

On the other hand, the control unit 6 follows the phase comparison signal 18 from the phase comparison unit 3, the 1-cycle detection signal 19 from the 1-cycle detection unit 4, and the count signal 14 output from the reversible counter 7 in addition to the reversible counter. A control signal 21 for controlling the counting operation of 7 is generated. The reversible counter 7 performs up / down counting operation based on the control signal 21 output from the control unit 6 and outputs the count signal 14. Further, based on the homo-code detection signal 20 output by the homo-code detector 5, the counting operation is stopped when the homo-code consecutive detection of the received data is performed.

The bit synchronizing circuit according to the first embodiment employs a method of controlling the phase of received data and synchronizing the phase of output data with the phase of the reference clock without controlling the phase of the clock. This method is called a multi-phase data type bit synchronization method.

FIG. 2 is an explanatory diagram showing a specific circuit configuration of the bit synchronization circuit according to the first embodiment. In particular, FIG.
As shown in, the change point detection unit 2, the phase comparison unit 3,
Detailed circuits are shown for the one-cycle detection unit 4 and the same code detection unit 5.

As shown in FIG. 2, the change point detection unit 2 outputs the output data 13 by the exclusive OR circuit 202.
And the data obtained by inserting T / 2 delay in the output data by the delay element 201 and detecting the rising and falling transition points of the output data 13 to output the output data transition point phase signal 16 To generate. Here, T represents one clock cycle. Further, the change point detection unit 2 takes the exclusive OR of the received data 11 by the exclusive OR circuit 204 and the data obtained by inserting a delay of T / 2 into the received data by the delay element 203 to obtain the received data. The rising and falling change points of 11 are detected. By detecting this change point, the change point detection unit 2 generates the reception data change point phase signal 17. The output data change point phase signal 16 and the received data change point phase signal 17 rise at the timing of data change, and the pulse widths thereof are the delay elements 201 and 2.
This is a signal determined by the delay time of 03.

Further, as shown in FIG. 2, the phase comparator 3 outputs the output data change point phase signal 16 output from the change point detector 2 in the flip-flops 301 and 302 respectively to the reference clock 12 and its reference clock 12. The phase comparison signals 181 and 182 are generated by fetching with the inverted clock and aligning the phases with the flip-flop 304. The combination of the values of the phase comparison signals 181 and 182 represents the lead / lag states, respectively. For example, the phase comparison signals 181 and 182 are (181, 182) = (H,
L) indicates that the phase of the reference clock 12 leads the output data 13. On the other hand, when these signals are (181, 182) = (L, H), it means that the phase of the reference clock 12 is behind the output data 13.

Further, the one-cycle detecting section 4 identifies the output data change point phase signal 16 for two cycles at the rising timing of the received data change point phase signal 17 by the flip-flops 401 and 402. Further, the one-cycle detection unit 4 includes the flip-flop 401 and the flip-flop 4
The one-cycle detection signal 19 is generated by taking the logical sum of the respective positive-phase outputs of 02. The one-cycle detection signal 19 is a signal that becomes "L" level only for one cycle when the rising edge of the output data change point phase signal 16 is detected at the rising edge of the reception data change point phase signal 17. .

The same code detection unit 5 includes a flip-flop 50.
Output data 1 by reference clock using 1 and 502
Identify 3 over two cycles. That is, output data 1
Each value over 2 cycles of 3 is the flip-flop 50
1 and 502 hold the exclusive OR of the output signals of each flip-flop. by this,
The same sign continuity of the output data 13 can be detected. By taking the exclusive OR, the same-code detection signal 20 is generated, and this same-code detection signal 20 is a signal that becomes “L” when the output data 13 over two cycles has the same code.

The control unit 6 outputs the phase comparison signals 181, 182 output by the phase comparison unit 3, the 1-cycle detection signal 19 output by the 1-cycle detection unit 4, and the count signal 14 output by the reversible counter 7. Based on this, the control signal 21 for controlling the counting operation of the reversible counter 7 is generated. Control signal 2
1 is a combination of the phase comparison signals 181 and 182 (H,
In the case of L), since it is in the advanced state, it becomes a signal indicating a countdown. On the other hand, the phase comparison signals 181, 182
When the combination is (L, H), it is a signal indicating a count up because it is in a delayed state. Further, the control signal 21 represents a reset operation for setting the value of the count signal 14 of the reversible counter 7 to 0 when it is in a delayed state and the 1-cycle detection unit 4 detects 1 cycle. , In the advanced state and when the value of the count signal 14 is 0, it is a signal indicating a load for setting the count signal 14 to a preset value.

The reversible counter 7 performs a counting operation based on the control signal 21 output by the control unit 6 and the same code detection signal 20 output by the same code detection unit 5. That is,
When the same code continuity is not detected in the output data 13 (when the codes having the same value as the other values are not continuously detected in the output data 13), counting operations such as up-down, down-count, reset, and load are performed. is there. As a result of such counting operation, the reversible counter 7 outputs a count signal 14. When the same-code detection unit 5 continues the same code (when the codes having the same value are continuously detected in the output data 13), the reversible counter 7 stops the counting operation.

The structure of the variable delay unit 1 is shown in FIG. As shown in FIG. 3, the decoder 101 generates a decode signal based on the count signal 14 output by the reversible counter 7. The selector 100 receives an input signal that has passed through the delay element 103 based on this decoded signal, and an input signal that has not passed (that is, an input signal with a delay inserted and an input signal with no delay inserted). Select either signal. In this way, the delay amount inserted in the received data 11 is controlled, and the output data 1
3 is finally output. That is, when the value of the count signal 14 increases, the delay time is increased and the phase of the output data 13 is delayed. On the other hand, when the value of the count signal 14 is decreased, the delay time is decreased and the phase of the output data 13 is advanced.

FIG. 4 is a time chart showing the operation of the bit synchronization circuit shown in FIG. FIG.
As shown in FIG. 4, when the count signal 14 is i, for example, the received data 11 and the output data 13 are shown in FIG.
In the case of the delay state as shown in (1), the change point detector 2 generates the output data change point phase signal 16 based on the output data 13 based on the reference clock 12. The output data change point phase signal 16 has a value as shown in FIG. In the phase comparison unit 3,
The value of the output data change point phase signal 16 is set to the reference clock 1
2 is used as a reference, and the phase comparison signal 18
The combination of 1, 182 is (181, 182) = (L,
Since it is H), the delay state is detected.

In this case, the reversible counter 7 sequentially counts up from the initial state i because the delayed state is detected. As a result, the variable delay unit 1 increases the delay amount to be inserted into the received data 11 based on the count signal 14 and sequentially delays the output data 13. In this way, when the reversible counter 7 counts up and the count signal 14 becomes i + 3, the phase comparator 3
In, since the combination of the phase comparison signals 181 and 182 is (181, 182) = (H, L) (see FIG. 4), the advance state is detected. When the advance state is detected in this way, the reversible counter 7 then performs a countdown operation. That is, as shown in FIG. 4, the count signal is sequentially counted down from i + 3 to i + 2, i + 1. Variable delay unit 1
On the basis of the count signal 14
The amount of delay to be inserted into is gradually decreased. In this way, the count signal 14 is sequentially counted down,
When it becomes i as shown in (1), the phase comparison signals 181 and 182 represent the advanced state again. As a result, the reversible counter 7 performs the count-up operation again, and thereafter, such operations are repeated, and as a result, the synchronized state is held.

FIG. 5 shows a time chart for explaining the operation of the 1-cycle detecting section 4 shown in FIG.
As shown in FIG. 5, first, the delay amount of the output data change point phase signal 16 is increased so that the rising edge of the reception data change point phase signal 17 rises earlier than the rising edge of the output data change point phase signal 16. Then, the output of the flip-flop 401 changes from "H" to "L".
Next, the output of the flip-flop 402 is delayed from the output of the flip-flop 401 by one cycle and goes from "L" to "H".
Becomes Therefore, by taking the logical sum of the outputs of the flip-flops 401 and 402, "L" is obtained for one cycle.
One cycle detection signal 19 is generated (see FIG. 5).

In this way, in this embodiment, the phase of the output data and the reference clock are compared and the delay amount to be inserted in the received data is controlled. Further, the operation of the reversible counter is stopped when the output data has the same sign, and the variable delay unit detects that the delay amount inserted in the received data is one cycle and controls the reset and load operations of the reversible counter. did. As a result, the variable delay can be continuously changed without affecting the clock, even if there is variation or fluctuation in the delay time in the delay element, and the output data is in the optimum phase. Phase control can be performed. As a result, it is possible to increase the phase margin in the state where the synchronization is maintained without affecting the circuit in the subsequent stage, and the bit synchronous operation capable of stable operation is realized.

Second Embodiment In the first embodiment, the phase comparison unit 3 performs the phase comparison using the output data change point phase signal 16 output from the change point detection unit 2. However, it is also preferable to directly perform the phase comparison from the output data 13 without using the output data change point output signal 16 as shown in FIG.
FIG. 6 is a block diagram showing the configuration of the bit synchronizing circuit according to the second embodiment when the phase comparison is performed directly from the output data 13 as described above.

In FIG. 6, the variable delay unit 1, the change point detection unit 2, the one-cycle detection unit 4, the same code detection unit 5, and the reversible counter 7 are shown in FIG. 1 of the first embodiment. The same operation is performed according to the existing one.

The phase comparator 3a detects the lead / lag state by comparing the phases of the output data 13 output from the variable delay unit 1 and the reference clock 12, and the phase comparison signal 18a which is the detection result. To generate. Control unit 6
Is the phase comparison signal 18a output by the phase comparison unit 3a.
And a 1-cycle detection signal 19 output by the 1-cycle detector 4,
Further, based on the count signal 14 output from the reversible counter 7, a control signal 21 for controlling the counting operation of the reversible counter 7 is generated.

A detailed circuit diagram of the phase comparison section 3a is shown in FIG. As shown in FIG. 7, the phase comparison unit 3
In a, the output data 13 output from the variable delay unit 1 is fetched by the flip-flops 301 and 302 with the reference clock 12 and its inverted clock (the clock inverted by the inverter 303) as the reference. The fetched signals have their respective phases aligned by the flip-flops 304, and then the flip-flops 301 and 304.
The exclusive OR of the output signals of and is taken in the XOR gate 305 to generate the phase comparison signal 18a. This phase comparison signal 18a is the reference clock 1
When the phase of 2 is ahead of the output data 13, it becomes an "H" level signal, while when the phase of the reference clock 12 is behind the output data 13, it is "L".
It becomes a level signal.

Based on the phase comparison signal 18a output by the phase comparison unit 3a, the 1-cycle detection signal 19 output by the 1-cycle detection unit 4, and the count signal 14 output by the reversible counter 7, the control unit 6 A control signal 21 for controlling the counting operation of the reversible counter 7 is generated. This control signal 21
When the phase comparison signal 18a is "H", it indicates a countdown because it is in the advanced state. on the other hand,
When the phase comparison signal 18a is "L", the control signal 21 is a signal indicating a count up because it is in the delayed state. Further, this control signal 21 is in a delayed state,
And when one cycle is detected by the one cycle detection unit,
A signal indicating that the count signal 14 of the reversible counter 7 is reset to 0. On the other hand, when the count signal 14 is in the advanced state and the count signal 14 is 0, a signal indicating a load for setting the count signal 14 to a preset value. Becomes

In this way, in this embodiment, by directly performing phase comparison without using the output data change point phase signal output from the change point detection section, the delay variation in the change point detection section and the It is possible to eliminate the influence of delay time fluctuations on the phase comparison result due to changes in environmental conditions. Therefore, the phase margin in the synchronized holding state can be made larger and stable.

Third Embodiment In the first embodiment, the variable delay section 1 generates the output data 13 by changing the delay amount to be inserted in the received data 11 using a plurality of delay elements. However, as shown in FIG. 8, a delay unit is not used, and a multiplying unit is provided to provide a delay by using a multiplying clock having a frequency n times (n is a positive integer) the reference clock. Is also suitable. FIG. 8 shows a block diagram of a configuration of a bit synchronization circuit using the variable delay unit 1a in which the delay amount is set by using the multiplication clock output from the multiplication unit 8.

In FIG. 8, the multiplication unit 8 is, for example, a PLL.
A reference clock 12 is input, which is composed of a multiplier circuit such as (Phase Locked Loop), and a multiplied clock 22 having a frequency n times that of the reference clock 12 phase-synchronized with the reference clock is generated. Variable delay unit 1
a is composed of, for example, a shift register, and based on the multiplication clock 22 output from the multiplication unit 8, a variable delay time in which one cycle of the multiplication clock 22 is set as one unit is inserted into the reception data 11 to generate the output data 13. To do. Other configurations and operations of the bit synchronization circuit shown in FIG. 8 are the same as those shown in FIG.

As described above, in the third embodiment, the delay time is given to the received data 11 by using the multiplied clock without using the delay element. Therefore, since the variable delay time can be accurately given to the signal, it is possible to remove the influence of the fluctuation of the delay time due to the variation of the delay or the change of the environmental condition.

Fourth Embodiment In the third embodiment, the multiplication unit 8 is provided and a constant delay time is given by using the multiplication clock 22. However, as shown in FIG. 9, it is also possible to use a reference high-speed clock to give a delay without using a multiplied clock, and to further provide a frequency divider to generate the reference clock from the reference high-speed clock. It is suitable. FIG. 9 shows a block diagram of the configuration of a bit synchronization circuit in the case where a delay is given after using a reference high-speed clock, and a signal obtained by dividing the reference high-speed clock by a frequency divider 9 is used as the reference clock. Has been done.

In FIG. 9, the variable delay unit 1a inserts a variable delay with one cycle of the reference high-speed clock 22a as one unit into the received data 11 based on the reference high-speed clock 22a to generate output data 13. There is. Here, the reference high-speed clock 22a is a clock signal having a frequency n times that of the reference clock 12.

Further, the frequency dividing section 9 uses the reference high speed clock 22.
The reference clock 12 is generated by dividing a by 1 / n.
The reference clock 12 is output to each part in the circuit and also to the outside of the circuit. In the bit synchronization circuit shown in FIG. 9, the other configurations are the same as the configurations of the bit synchronization circuit shown in FIG. 1, and the operation is also the same.

Thus, in the fourth embodiment,
The delay time was given to the signal using the reference high-speed clock without using the multiplied clock. Therefore, the variable delay can be accurately given, and the influence of the delay time variation due to the delay variation or the change of the environmental condition can be removed.

Embodiment 5 FIG. 10 shows a block diagram of the configuration of a bit synchronization circuit according to another embodiment of the present invention. As shown in FIG. 10, the variable delay unit 1b inputs the reception data 11, and the polyphase conversion unit 104 generates a plurality of signals given various delay times. The multi-phase conversion unit 104 uses T / n (where,
T is one clock cycle, and n is a positive integer). The delay time is 1 unit, and n delay data 15 to which n kinds of delays of 1 to n are given are generated. Selector 10
2 selects one of the n delay data 15 based on the count signal 14 output from the reversible counter 7 and outputs the output data 13.

On the other hand, the phase comparator 3b outputs the output data 13
Of the reference clock 12 is compared with the phase of the reference clock 12 to generate a phase comparison signal 18b which is the comparison result. The same code detection unit 5 detects, based on the output data 13 and the reference clock 12, that the output data 13 continuously outputs a code having the same value. Then, the same sign detection signal 20 which is the detection result is generated. Reversible counter 7
Performs a counting operation based on the phase comparison signal 18b output from the phase comparison unit 3b and outputs the count signal 14. Further, based on the homo-code detection signal 20 output from the homo-code detection unit 5, when homo-code continuity detection of the output data 13 (codes having the same value appearing continuously in the output data 13 is detected. In this case, the counting operation is stopped.

In the bit synchronizing circuit according to the fifth embodiment, the reference clock is used as the clock input of the reversible counter 7, and the reversible counter is controlled from the data after a certain delay time is inserted. Therefore, a method of controlling the phase of the received data and synchronizing the phase of the output data with the phase of the reference clock is adopted.

FIG. 11 is a circuit diagram showing a concrete circuit configuration of the bit synchronization circuit according to the fifth embodiment.
The variable delay unit 1b receives the received data 11 and is given n kinds of delays (1 / n to n / n) by n delay elements having a delay time of T / n in the multi-phase conversion unit 104. A plurality of delay data 15 are generated.

The phase comparison unit 3b takes the exclusive OR of the output data 13 output from the variable delay unit 1b and the data obtained by inserting a delay of T / 2 into the output data 13 by a delay element. The data of the exclusive OR is sampled by the flip-flop 303 based on the reference clock 12, and the inverted output is output to the outside as the phase comparison signal 18b. In the phase comparison signal 18b, when the rising edge of the reference clock 12 is the output data 1
When it exists in the time range of T / 2 from the change point of the data value of 3, it becomes “L”, which indicates that the phase of the reference clock 12 leads the phase of the output data 13. On the other hand, the phase comparison signal 18b becomes "H" when the rising timing of the reference clock 12 is within the time range of T / 2 preceding the change point of the output data 13,
This indicates that the phase of the reference clock 12 is behind the phase of the output data 13.

The same code detection unit 5 is a flip-flop 50.
The value of the output data 13 is identified using 1 and 502 over two cycles. That is, the output data 1 that is consecutively output to the flip-flops 501 and 502 that are connected in series.
The data of 3 are retained. Then, by taking the exclusive OR of the output signals of the flip-flops 501 and 502, the same sign continuity of the output data 13 is detected. The exclusive OR signal is called the same code detection signal 20.

The reversible counter 7 performs counting operations such as counting up and counting down based on the phase comparison signal 18b output from the phase comparison unit 3b and the same code detection signal 20 output from the same code detection unit 5, and outputs the count signal. 14 is output. The reversible counter 7 operates according to the reference clock 12, but when the output data 13 does not continuously detect the same code (when the output data 13 does not continuously have the same code), the count up or The counting operation of the countdown is performed, but when the same code continuation is detected by the same code detection unit 5, the counting operation is stopped.

The operation of the bit synchronization circuit shown in FIG. 11 will be described with reference to FIG. FIG. 12 is a time chart showing the operation of the bit synchronization circuit shown in FIG.

As described above for the received data 11, n
The individual delay data 15 are generated. A case where the value of the count signal 14 is i and the output data 13 is in the delay state as shown in FIG. 12 will be described. Here, when the reference clock 12 is input, first, the rise of the reference clock 12 is within the range of T / 2 before the change point of the output data 13 (the time range of T / 2 preceding the change point), The comparison signal 18b becomes "H". Next, the reversible counter 7 counts up from the state where the count signal 14 is i, and the phase comparison signal 18
This count-up operation is continued while b is "H". As a result, the count signal 14 sequentially increases.

Next, the selector 102 outputs the count signal 1
Based on 4, the next delay data is sequentially selected. When the count signal 14 becomes i + 2, the change point position of the output data 13 exceeds the fall of the reference clock 12 (the output data 13 falls after the fall of the reference clock 12), and as a result, the phase comparison is performed. The signal 18b becomes "L". The reversible counter 7 has a phase comparison signal 18b.
Becomes "L", the countdown is performed from the first rising timing of the reference clock 12. Due to this countdown, the count signal 14 sequentially decreases.
The selector 102 sequentially selects the immediately preceding delay data based on the count signal 14.

When the count signal 14 repeatedly decreases and its value becomes i + 1 (see FIG. 12), the output data 13
, The phase comparison signal 18b becomes “H”. Then, when the value of the count signal 14 becomes i, the reversible counter 7 starts counting up again. After that, the reversible counter 7 alternately repeats the count-up operation and the count-down operation to maintain a constant synchronization state (see FIG. 12).

As described above, in the fifth embodiment, the phase comparison unit 3b compares the phases of both the output data and the reference clock, and the variable delay unit 1b controls the delay amount inserted in the received data. There is. Further, when the same-code detector 5 detects that the output data has the same-code continuity (two codes having the same value appear consecutively in two cycles), the operation of the reversible counter 7 is stopped and the reference clock It is possible to output data synchronized with the reference clock without affecting the above. As a result, with a simple configuration, it is possible to realize a bit synchronization circuit that can be stably operated without affecting the circuit in the subsequent stage.

Sixth Embodiment In the fifth embodiment described above, it is also preferable that the reversible counter 7 is provided with a control unit outside the reversible counter 7 to control resetting and loading of the reversible counter 7. As described above, the configuration in which the control unit of the reversible counter 7 is provided is shown in FIG.
3 is shown.

As shown in FIG. 13, the variable delay section 1b, the same code detection section 5, and the phase comparison section 3b have the same configurations as those in the fifth embodiment. The control unit 6a uses the phase comparison signal 18b output by the phase comparison unit 3b.
And based on the count signal 14 from the reversible counter 7,
A control signal 21a for controlling resetting and loading of the reversible counter 7 is generated. The control signal 21a is reversible when the phase of the reference clock 12 with respect to the output data 13 is delayed and the count signal 14 causes the selector 102 to select the delayed data having the maximum delay in the selector 102. This means that the count signal 14 of the counter 7 is reset to 0. On the other hand, when the phase of the reference clock is advanced with respect to the phase of the output data 13 and the value of the count signal 14 is 0, this represents a so-called load for setting the count signal 14 to a preset value. It will be. The reversible counter 7 has a phase comparison signal 18b output by the phase comparison unit 3b.
Then, the operation is performed based on the same code detection signal 20 output from the same code detection unit 5, and the count signal 14 is output. The reversible counter 7 operates according to the reference clock 12 as in the first to fifth embodiments described above, and stops the counting operation when the same code continuation is detected by the same code detection unit 5. .

Thus, in the sixth embodiment,
By providing the control unit 6a and controlling resetting and loading of the reversible counter 7, it is not necessary to set the initial phase of the reversible counter 7, and the total delay amount of the variable delay unit 1b is 1
If there is a delay corresponding to a cycle, it becomes possible to perform synchronization regardless of the initial phase of the reversible counter 7.

Seventh Embodiment In the sixth embodiment, the variable delay unit 1b includes the multi-phase conversion unit 10.
4, the delay amount to be inserted in the received data 11 is changed by using the plurality of delay elements to generate the plurality of delay data 15. However, as shown in FIG. 14, a multiplier is provided without using a plurality of delay elements, and
It is also preferable to add a delay to the signal using a multiplied clock having a frequency that is double (n is a positive integer). FIG. 14 shows a block diagram of the configuration of a bit synchronization circuit provided with such a multiplication unit 8. In FIG. 14, the multiplication unit 8 receives the reference clock 12 and inputs the reference clock 12
A multiplied clock 22 whose phase is synchronized with that is generated. The multiplied clock 22 has a frequency n times that of the reference clock 12. The multi-phase conversion unit 105 in the variable delay unit 1a is composed of, for example, a shift register or the like, and based on the multiplication clock 22 output from the multiplication unit 8, there are n types of one cycle of the multiplication clock 22 in the received data 11 N pieces of delay data 15 given a delay of (delay amount is 1 to n)
Is generated.

The other structure and the operation of the structure shown in FIG. 4 are similar to those shown in FIG.

Thus, in the seventh embodiment,
It is possible to accurately provide variable delay for multiphase data using a multiplied clock without using a plurality of delay elements. Therefore, it is possible to obtain a bit synchronization circuit capable of eliminating the influence of delay time fluctuations due to delay variations and changes in environmental conditions.

Eighth Embodiment In the seventh embodiment, a case is shown in which the multiplication unit 8 is provided and a delay is given by using the multiplication clock 22. However, as shown in FIG. 15, the reference high-speed clock is used to delay without using the multiplied clock, and a frequency division unit is further provided to generate the reference clock based on the reference high-speed clock. Is also suitable. FIG. 15 shows a bit synchronization circuit having a configuration in which the reference high-speed clock is applied to the multi-phase conversion unit 105, and the frequency dividing unit 9 is further provided to generate the reference clock 12 from the reference high-speed clock using the frequency dividing unit 9. The configuration block diagram of is shown.

In FIG. 15, the multi-phase conversion section 105 inside the variable delay section 1a delays the received data 11 by n kinds of one cycle of the reference high-speed clock 22a based on the reference high-speed clock 22a. The given delay data 15 (given the delay amount of 1 to n) is generated. Here, the reference high-speed clock 22a is n of the reference clock 12.
It is a clock signal having a doubled frequency. The frequency divider 9 is
The reference high-speed clock 22a is divided into 1 / n to generate the reference clock 12.

The reference clock 12 is a signal supplied to each part in the bit synchronizing circuit, but is similarly supplied to the outside of this circuit. The other configuration shown in FIG. 15 and the operation of this other configuration are the same as those of the bit synchronization circuit shown in FIG.

Thus, in the eighth embodiment,
By using the reference high-speed clock to multiphase the data without using a delay element, a variable delay can be accurately given, so the effects of delay time fluctuations due to delay variations and changes in environmental conditions are eliminated. It becomes possible to do.

[0115]

As described above, in the bit synchronizing circuit and the bit synchronizing method according to the present invention, since the various configurations described above are adopted, the following effects can be obtained.

First, the phase comparator compares the phases of the output data and the reference clock, the variable delay unit controls the delay amount to be inserted in the received data, and the homo-code detector detects the homo-code continuity of the output data. If so, the operation of the reversible counter is stopped. Therefore, since it is possible to generate output data that is synchronized with the reference clock without affecting the reference clock, it is possible to perform stable operation without affecting the circuits in the subsequent stages with a simple configuration. A synchronization circuit can be provided.

Since the control unit controls the reset and load operations of the reversible counter, it is not necessary to set the initial phase of the reversible counter. Therefore, the total delay amount in the variable delay unit is enough to delay one cycle, and the delay of one cycle can synchronize the phase of the output data with the phase of the reference clock regardless of the initial phase. Become.

Further, the control unit controls the counting operation of the reversible counter and the reset and load operations.
Therefore, it is not necessary to set the initial phase of the reversible counter, and if the total delay amount in the variable delay unit has a delay of one cycle, the phase of the output data should be synchronized with the phase of the reference clock regardless of the initial phase. Is possible.

When the one-cycle detecting section detects that the delay amount inserted in the received data in the variable delay section is one cycle, the reversible counter is reset. Therefore, even if there is variation or fluctuation in the delay time in the delay element, the variable delay continuously changes, so that stable phase control can be performed.

Further, in the phase comparison section, the lead / lag state is detected by comparing the phase of the output data and the phase of the reference clock based on the output data change point phase signal generated from the change point detection section and the reference clock. To do. Then, since the phase control is performed until the phase relationship between the output data and the reference clock becomes the optimum phase, it is possible to obtain a large phase margin in the state where the synchronization is maintained.

In the phase comparison unit, the phase of the output data and the phase of the reference clock are directly compared from the output data generated by the variable delay unit and the reference clock to advance / advance.
The delay condition is detected. Therefore, since the phase of the output data and the phase of the reference clock are compared without using the delay element, it is possible to remove the influence of the delay time variation in the phase comparison result. Therefore, it is possible to perform stable phase control with a large phase margin in the state where synchronization is maintained.

Further, the phases of the output data and the reference clock are compared, the delay amount to be inserted in the received data is controlled, and when the same sign of the output data continues (the codes having the same value in the output data continue. The operation of the reversible counter is stopped, the variable delay unit detects that the delay amount inserted in the received data is one cycle, and the reset and load operations of the reversible counter are controlled. There is. As a result, the variable delay can be continuously changed without affecting the clock and even if the delay time varies or fluctuates in the delay element.
Further, since the phase control is performed until the output data has the optimum phase, the circuit in the subsequent stage is not affected. As a result, the phase margin is large while maintaining the synchronization hold state,
A bit synchronization circuit capable of stable operation can be obtained.

By generating a variable delay time in which the delay time for one cycle of the multiplied clock is one unit in the variable delay unit and inserting this time delay in the received data, the variable delay can be accurately given. is there. Therefore, it is possible to eliminate the influence of delay variation and delay time variation due to environmental conditions.

In addition, the variable delay unit sets the reference high-speed clock to 1
Since a variable delay having a delay time of one cycle as one unit is generated and inserted into the received data, it is possible to give the variable delay accurately. Therefore, it is possible to eliminate the influence of delay variation and delay time variation due to environmental conditions.

Further, the phases of the output data and the reference clock are compared with each other to control the delay amount to be inserted into the received data, and when the same sign of the output data is consecutive (the codes having the same value in the output data are consecutive). Then, the operation of the reversible counter is stopped. Therefore, a method of outputting data synchronized with the reference clock without affecting the reference clock can be obtained, so that it is possible to realize a bit-synchronous operation capable of stable operation without affecting the circuit in the subsequent stage. It is possible. The reversible counter is reset when the delay amount inserted in the received data is one cycle. Therefore, a method for continuously changing the variable delay is provided even when there is variation or fluctuation in the delay time in the delay element, so that stable bit synchronization operation can be realized.

Further, there is provided a method for generating an accurate variable delay by generating a variable delay in which the delay time for one cycle of the multiplied clock is one unit and inserting this delay time in the received data. Therefore, it is possible to realize a stable variable delay that does not cause variations in delay and variations in delay time due to environmental conditions.

A variable delay is generated with the delay time of one cycle of the reference high-speed clock as one unit, and this variable delay is inserted into the received data. Therefore, a method that can generate an accurate variable delay is realized, and a method that generates a stable variable delay that does not cause a delay time variation due to delay variation or environmental conditions can be provided.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a bit synchronization circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of the bit synchronization circuit shown in FIG.

FIG. 3 is a circuit diagram of a variable delay unit shown in FIG.

FIG. 4 is a time chart explaining the operation of the bit synchronization circuit shown in FIG.

FIG. 5 is a time chart explaining the operation of the one-cycle detecting unit shown in FIG.

FIG. 6 is a configuration block diagram of a bit synchronization circuit according to a second embodiment.

7 is a circuit diagram of a phase comparison unit of the bit synchronization circuit shown in FIG.

FIG. 8 is a configuration block diagram of a bit synchronization circuit according to a third embodiment of the present invention.

FIG. 9 is a configuration block diagram of a bit synchronization circuit that is Embodiment 4 of the present invention.

FIG. 10 is a configuration block diagram of a bit synchronization circuit according to a fifth embodiment of the present invention.

11 is a circuit diagram of the bit synchronization circuit shown in FIG.

12 is a time chart explaining the operation of the bit synchronization circuit shown in FIG.

FIG. 13 is a configuration block diagram of a bit synchronization circuit according to a sixth embodiment of the present invention.

FIG. 14 is a configuration block diagram of a bit synchronization circuit according to a seventh embodiment of the present invention.

FIG. 15 is a configuration block diagram of a bit synchronization circuit according to an eighth embodiment of the present invention.

FIG. 16 is a configuration block diagram of a bit synchronization circuit of Conventional Example 1 of the present invention.

FIG. 17 is a circuit diagram of the bit synchronization circuit shown in FIG.

18 is a circuit diagram of the variable delay unit shown in FIG.

FIG. 19 is a time chart explaining the operation of the bit synchronization circuit of Conventional Example 1 shown in FIG.

FIG. 20 is a configuration block diagram of a bit synchronization circuit of Conventional Example 2.

FIG. 21 is a time chart explaining the operation of Conventional Example 2 shown in FIG. 20.

[Explanation of symbols]

1, 1a, 1b variable delay unit, 2, 2a change point detection unit, 3, 3a, 3b, 3c phase comparison unit, 4, 4a 1
Cycle detection unit, homo-code detection unit, 5a synchronization determination unit, 6
a control unit, 7 reversible counter, 8 multiplication unit, 9 frequency division unit, 11 received data, 12 reference clock, 12b
Output clock, 13 output data, 14 count signal,
15 delay data, 16 output data change point phase signal,
17 reception data change point phase signal, 18 phase comparison signal, 19 1 cycle detection signal, 20 homo-code detection signal, 20
a sync determination signal, 21,21a control signal, 22 multiplication clock, 22a reference high-speed clock, 23 reception clock, 201, 203 delay element, 202, 204 E
XOR gate, 301, 302, 304 flip-flop, 303 inverter, 401, 402 flip-flop, 403 OR gate, 501, 502 flip-flop, 503 EXOR gate, 101 decoder, 102 selector, 103 delay element, 104 polyphase converter, 15 Delayed data, 105 Polymorphizer.

Claims (13)

[Claims] 1. A bit synchronization circuit for controlling the phase of received data based on a phase relationship between output data and a reference clock and outputting output data synchronized with the phase of the reference clock, and inserting the bit into the received data. A variable delay unit that changes the delay amount based on the count value of the reversible counter to generate the output data, and a phase comparison signal by comparing the phase of the output data and the phase of the reference clock to detect a lead / lag state. And a phase comparison unit for generating the output data, the output data is identified by the reference clock over two cycles, and the same code continuous state in which the value of the output data is the same over two cycles is detected. And a reversible counter that counts the reference clock based on the phase comparison signal output by the phase comparison unit. The reversible counter stops its operation when the same-code detector detects the same-code continuity of the output data. 2. The bit synchronization circuit according to claim 1, further comprising a control unit that generates a control signal for controlling reset and load of the reversible counter based on the phase comparison signal and the count value of the reversible counter. And the reversible counter operates based on the control signal. 3. The bit synchronization circuit according to claim 2, wherein the control unit further generates a control signal for controlling a counting operation of the reversible counter, and the reversible counter performs a counting operation based on the control signal. A bit synchronizing circuit characterized by performing reset and load operations together with the above. 4. The bit synchronization circuit according to claim 1, 2 or 3, further, detecting respective change points of the reception data and the output data, and rising at the timing when the respective data change points are detected. A change point detection unit that generates a received data change point phase signal and an output data change point phase signal, and a delay amount inserted in the received data is 1 based on the received data change point phase signal and the output data change point phase signal. A cycle detection unit that generates a cycle detection signal when it is detected that the number of cycles is reached; and the control unit includes the phase comparison signal, the cycle detection signal, and the reversible counter. A control signal that controls the operation of the reversible counter is generated based on a count value, and the control signal is generated when the one-cycle detection signal is output. Bit synchronization circuit, characterized in that resetting the reversible counter. 5. The bit synchronization circuit according to claim 4, wherein the phase comparison unit is configured to output the phase of the output data based on the output data change point phase signal generated by the change point detection unit and the reference clock. And a reference clock are compared with each other to detect a lead / lag state, and the phase comparison signal is generated. 6. The bit synchronization circuit according to claim 4, wherein the phase comparison unit directly determines the phase of the output data and the reference clock based on the output data and the reference clock generated by the variable delay unit. The phase synchronization signal is generated by detecting the lead / lag state by comparing the phases of the bit synchronization circuits. 7. A bit synchronization circuit that controls the phase of received data based on the phase relationship between output data and a reference clock and outputs output data that is synchronized with the phase of the reference clock, and inserts it into the received data. A variable delay unit that changes the amount of delay based on the count value of a reversible counter to generate the output data, a change point of each of the received data and the output data, and a timing at which each data change point is detected. A change point detection unit that generates a reception data change point phase signal and an output data change point phase signal that rises at, and a lead / lag state is detected by comparing the output data phase and the reference clock phase, and phase comparison is performed. A phase comparison unit that generates a signal, and based on the received data change point phase signal and the output data change point phase signal, the reception A 1-cycle detection unit that generates a 1-cycle detection signal when it is detected that the delay amount inserted in the data has reached 1 cycle; and the output data is identified by the reference clock over 2 cycles, A homo-code detection section that generates a homo-code detection signal when a homo-code continuation state in which the value of the output data is the same over two cycles is detected; the phase comparison signal; A control unit that generates a control signal that controls the operation of the reversible counter based on the count value of the reversible counter; and an operation that is performed based on the control signal, and that the same code continuation of the output data is performed by the same code detection unit. A bit synchronization circuit, comprising: the reversible counter that stops operating when detected. 8. The bit synchronization circuit according to claim 1, further comprising: a multiplication unit that multiplies the reference clock to generate a multiplication clock, the variable delay unit using the multiplication clock. Variable synchronization in which the delay time for one cycle is generated as one unit, and the delay amount to be inserted into the received data is changed based on the counter value of the reversible counter to generate output data. circuit. 9. The bit synchronization circuit according to claim 1, further comprising: a frequency divider that divides the reference high-speed clock to generate a reference clock, wherein the variable delay unit uses the reference high-speed clock. Then, a variable delay in which the delay time of one cycle of the reference high-speed clock is set as one unit is generated, and the delay amount to be inserted into the received data is changed based on the counter value of the reversible counter to generate the output data. Characteristic bit synchronization circuit. 10. A bit synchronization method for controlling a phase of received data based on a phase relationship between output data and a reference clock and outputting data synchronized with the phase of the reference clock, including the following steps. Characteristic bit synchronization method. (A) A variable delay insertion step of changing the delay amount to be inserted into the received data based on the count value of a reversible counter to generate output data, (b) comparing the phase of the output data with the phase of the reference clock. A phase comparison step of generating a phase comparison signal, (d) the output data is identified by a reference clock for two cycles to detect the same sign continuity of the output data, and the operation of the reversible counter is stopped when the same sign continuity is detected. Same sign continuous detection step. 11. The bit synchronization method according to claim 10, further comprising the following steps. (A) a change point detecting step of detecting a change point of the received data and the output data and generating a received data change point phase signal and an output data change point phase signal; (b) the received data change point phase signal; A one-cycle detecting step of generating a one-cycle detection signal by detecting that the delay amount inserted in the received data in the variable delay inserting step is one cycle based on the output data change point phase signal; ) A control step of controlling the operation of the reversible counter based on the phase comparison signal, the one-cycle detection signal, and the count value of the reversible counter. 12. The bit synchronization method according to claim 11, further comprising the following steps. (A) a reference clock multiplication step of multiplying a reference clock to generate a multiplied clock; (b) using the multiplied clock, generating a variable delay having a delay time of one cycle of the multiplied clock as one unit;
A variable delay insertion step of generating the output data by changing a delay amount to be inserted into the received data based on a count value of the reversible counter. 13. The bit synchronization method according to claim 11, further comprising the following steps. (A) Dividing step of dividing the reference high-speed clock to generate the reference clock, (b) Using the reference high-speed clock, a variable delay in which the delay time of one cycle of the reference high-speed clock is set as one unit. A variable delay insertion step of generating the output data by changing a delay amount that is generated and inserted into the received data based on a count value of the reversible counter.