JP3102756B2 - Clock extraction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock extracting circuit using a digital phase-locked loop circuit, and more particularly to an IS circuit.
The present invention relates to a clock extraction circuit of an S interface circuit connected to a DN network.

[0002]

2. Description of the Related Art Conventionally, an ISDN-S interface circuit performs data reception by extracting a synchronization clock from received data in order to receive data transmitted from an ISDN network. Then, in order to extract a clock synchronized with the received data, a digital phase locked loop (hereinafter, referred to as a digital phase locked loop)
(DPLL) circuit is often used.

FIG. 5 is a block diagram of a conventional DPLL circuit. In the figure, a phase comparator 11 compares a phase of received data with a phase of an output clock and outputs a phase difference. The output phase difference is counted by the phase counter 12 for “phase advance” or “phase delay” and is cumulatively counted.

When the count value of the phase counter 12 reaches a preset value K, the phase control section 13 "advances" or "delays" the phase of the output clock to generate an output clock synchronized with the received data. I do.

[0005] The follow-up time and stability of the DPLL circuit are determined by a set value K. The larger the set value K is, the more stable the clock can be extracted with respect to noise and jitter, and if it is too large, loss of synchronization occurs.

[0006]

In the basic interface of the ISDN network, an AMI code having a 100% duty is used as a transmission code. FIG. 6 shows this encoding rule. As shown in the figure, the AMI code represents data “0” alternately in correspondence with + amplitude and − amplitude, and associates data “1” without amplitude. Then, "+0 digital signal" is extracted with the + side reference voltage, and "-0 digital signal" is extracted with the-side reference voltage.

Therefore, in order to extract a clock synchronized with the received data, the data "0" must be included in the received data, and the synchronous clock cannot be extracted only by the data "1".

For this reason, when a DPLL circuit is used,
The value of the set value K that determines the tracking time and the stability is set as the worst value when the data “0” is the least in the received data. That is, the value of the set value K is set to a small value so that even a small number of “0” can be followed quickly. However, if the value of the set value K is small, the following time is short, but the stability against noise, jitter and the like is not sufficient.

It is an object of the present invention to provide a clock extracting circuit capable of quickly and stably extracting a clock synchronized with received data in a basic interface of an ISDN network.

[0010]

According to a first aspect of the present invention, there is provided a clock extracting circuit for comparing a phase between received data and an output clock to output a phase difference, and
In a digital phase locked loop circuit comprising a phase counter that counts and accumulates the phase difference and a phase control unit that controls the phase of the output clock using the count value of the phase counter as phase control information, the received data is detected and the phase is compared. A pulse detection circuit that supplies a pulse valid period signal in synchronization with the received data, and a switch circuit that supplies and controls the phase difference to the phase counter using the pulse valid period signal as a switch signal. Provided.

A clock extraction circuit according to a second aspect of the present invention includes a phase comparator that compares phases between received data and an output clock and outputs the phase difference, a phase counter that counts and accumulates the phase difference. And a phase control unit for controlling the phase of the output clock using the count value of the phase counter as phase control information. A first receiver circuit for extracting data "0" of + amplitude, and a second receiver circuit for extracting data "0" of-amplitude, comprising a digital signal representing data "1" corresponding to no representation amplitude. , First and second pulse detection circuits for outputting rising edge signals synchronized with the received data from the outputs of the first and second receiver circuits, And a second pulse valid period output circuit that outputs a pulse valid period signal using the output of the second pulse detection circuit as a trigger and an edge signal that is output from the first and second pulse detection circuits, and A first OR circuit that supplies the comparator, and a second OR circuit that combines the pulse valid period signals output from the first and second pulse valid period output circuits and supplies the combined signal to the switch circuit as a switch signal. Provided.

[0012]

The clock extraction circuit according to the first and second aspects of the present invention is a pulse detection circuit for detecting the presence or absence of received data in a loop of a DPLL circuit including a phase comparator, a phase counter, and a phase control unit. A pulse valid period output circuit that outputs a pulse valid period signal in synchronization with an output of the pulse detection circuit; and a switch circuit that controls supply of an output of the phase comparator to the phase counter using the pulse valid period signal as a switch signal. When the received data is "1" (no amplitude), the input to the phase counter is suppressed by the switch circuit. Thus, the value of the set value K does not need to be determined as the worst value when the data “0” is the least in the received data, and the value of the set value K with high stability can be set.

[0013]

FIG. 1 is a block diagram showing an embodiment of a clock extraction circuit according to the present invention. In the figure, receiver circuits 1a and 1b compare an AMI code received from an ISDN network with a reference voltage, and receiver circuit 1a outputs a +0 digital signal Aa and receiver circuit 1b outputs a −0 digital signal Ab.

The pulse detectors 2a and 2b receive the received AMI
The presence or absence of a pulse (that is, data “0”) is detected from the code, and edge signals Ba and Bb synchronized with the rising edge of the received digital signal are output.

The pulse valid period output circuits 3a and 3b use the output signals Ba and Bb of the pulse detectors 2a and 2b as a trigger, for example, by counting reference clocks, or by using a one-shot multivibrator or the like. It outputs pulse valid period signals Ca and Cb indicating a period in which a pulse exists.

The OR circuit 4a combines the edge signals Ba and Bb from the pulse detectors 2a and 2b and supplies them to the phase comparator 5 as an edge signal D. The OR circuit 4b outputs a pulse valid period signal C from the pulse valid period output circuits 3a and 3b.
a and Cb are combined and supplied to the switch circuit 6 as a pulse effective period signal E.

The phase comparator 5 counts the phases of the output clock T and the rising edge signal D of the received data with the reference clock, and outputs the counted value as a phase difference signal F. The switch circuit 6 receives the pulse valid period signal E from the OR circuit 4b.
Is used as a switch signal to control the output of the phase difference signal F.

The phase counter 7 cumulatively counts the phase difference signal F supplied from the phase comparator 5 through the switch circuit 6 for each output clock. The phase controller 8 controls the phase of the output clock T based on the count value G of the phase counter 7.

The reference clock circuit 9 outputs a clock signal CK as a basis for controlling the phase of the output clock T. The phase difference is also output based on the clock signal CK and takes a value of 1 / N of the received data. Here, the value is 1/40 of the received data.

Next, the operation of this embodiment will be described with reference to the waveform diagrams shown in FIGS. ISDN
The AMI code received from the network includes two receiver circuits 1a,
1b and received by the comparator circuit at +0 reception digital signal Aa and −0 reception digital signal Ab, respectively.
Is converted to

Next, the pulse detectors 2a and 2b detect the rising edge signal Ba from the +0 received digital signal Aa using the reference clock, and detect the rising edge signal Bb from the -0 received digital signal Ab.

Next, the pulse valid period output circuits 3a, 3
b, the rising edge signals Ba and Bb are used as a trigger for 1
Signals Ca and Cb for 40 reference clock periods of received data width
Is output. Then, the OR circuit 4b combines the signals Ca and Cb indicating the pulse valid period to generate one pulse valid period signal E. The OR circuit 4a combines the rising edge signals Ba and Bb to generate one rising edge signal D.

That is, the rising edge positions of the positive and negative amplitudes of the data "0" are individually detected from the received AMI code, and the pulse valid periods are individually output, and the OR circuits 4a and 4b are respectively provided. To generate one rising edge signal D of one received data and one pulse effective period signal E.

The rising edge signal D of the received data generated by the OR circuit 4a is compared with the rising edge position of the output clock T by the phase comparator 5 using the reference clock, and as a phase difference signal F for each output clock T. Is output. Here, the phase difference at the time of the output clock Ti is δi.

The phase difference signal F is supplied to the phase counter 7 only during a period when the pulse valid period signal E indicates validity in the switch circuit 6, and is accumulated by the phase counter 7 as needed. That is, the phase counter 7 sequentially accumulates the phase difference signal F (δi) for each output clock Ti during a period in which the pulse valid period signal E indicates validity (a period of “1”), and the pulse valid period signal E indicates invalid. The period (the period of “0”) is not cumulatively added. FIG. 4 is a waveform diagram showing this relationship.

Next, when the phase count value G of the phase counter 7 reaches the set value K or more, the phase control section 8 performs phase control of "advancing" or "delaying" the phase of the output clock T by several reference clocks. .

When received data is present by the above series of operations, the phase difference is accumulated in the phase counter 7 at every output clock T, and when the phase count value G reaches the set value K or more, the phase difference is suppressed. So that the phase of the output clock T is controlled. If there is no received data, the phase difference in that period is not added to the phase counter 7 by the pulse valid period signal E, and the previous accumulated phase count value is stored. Therefore, even when the received data "0" is received, the phase count value is held, the phase difference is counted quickly, and the time for the output clock T to follow the received data is shortened.

[0028]

According to the clock extracting circuit of the present invention, when the received data is "1" (no amplitude), the input of the phase counter is suppressed, so that the set value K for determining the tracking time and the stability is determined. It is not necessary to determine the value as the worst value when the data “0” is the least in the received data, and the set value K with high stability can be determined. Therefore, the output clock synchronized with the received data can be output quickly and stably using the DPLL circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a clock extraction circuit according to the present invention.

FIG. 2 is a waveform chart for explaining the operation of the present invention.

FIG. 3 is a waveform chart for explaining the operation of the present invention.

FIG. 4 is a waveform chart for explaining the operation of the present invention.

FIG. 5 is a block diagram of a conventional DPLL circuit.

FIG. 6 is a waveform diagram showing an example of conversion from an AMI code to a digital signal.

[Explanation of symbols]

 1a, 1b Receiver circuit 2a, 2b Pulse detection circuit 3a, 3b Pulse valid period output circuit 4a, 4b OR circuit 5 Phase comparator 6 Switch circuit 7 Phase counter 8 Phase control unit 9 Reference clock circuit

Claims (2)

(57) [Claims] 1. A phase comparator for comparing phases between received data and an output clock to output a phase difference, a phase counter for counting and accumulating the phase difference, and using a count value of the phase counter as phase control information. In a digital phase locked loop circuit comprising a phase control unit for controlling the phase of the output clock, a pulse detection circuit for detecting the received data and supplying it to the phase comparator, and a pulse valid period signal synchronized with the received data A pulse valid period output circuit that outputs a pulse valid period signal as a switch signal, and a switch circuit that controls supply of the phase difference to the phase counter.
A clock extraction circuit comprising: 2. A phase comparator for comparing phases between received data and an output clock to output a phase difference, a phase counter for counting and accumulating the phase difference, and a count value of the phase counter as phase control information. In the digital phase locked loop circuit comprising a phase control unit for controlling the phase of the output clock, the received data represents data "0" by associating + amplitude and -amplitude alternately, and data "1" by associating with no amplitude. A first receiver circuit for extracting the + amplitude data "0", a second receiver circuit for extracting the -amplitude data "0", and the first and second signals. A first output of a rising edge signal synchronized with the reception data from an output of a receiver circuit;
And a second pulse detection circuit; a first and a second pulse valid period output circuit for outputting a pulse valid period signal using an output of the first and the second pulse detection circuits as a trigger; A first OR circuit that synthesizes an edge signal output from the pulse detection circuit and supplies the signal to the phase comparator; and a pulse effective period signal output from the first and second pulse effective period output circuits. And a second OR circuit for supplying the switch circuit with a switch signal as a switch signal.