JP2001268061A - Bit synchronization circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bit synchronization circuit that can have no dead band phase, instantaneously establish synchronization, and can be in operation even at a high-speed bit rate of 10 Gb/s or over. SOLUTION: The bit synchronization circuit of this invention is characterized in that a phase and an amplitude of a data signal are compared with those of a reference clock signal to instantaneously establish bit synchronization, the circuit is configured with a simple logic, the bit synchronization is instantaneously established because of absence of a feedback loop, the phase of the data signal is analogically compared with the phase of the clock signal, and sampling and holding the result of the phase comparison receives no limitation of a preamble pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit synchronization circuit which is a component of an electronic circuit used for a digital communication transmission device, an exchange, a router, an optical interconnection and the like.

[0002]

2. Description of the Related Art A method for synchronizing data communication with a system clock signal includes a clock parallel transmission system in which one data channel is allocated to a clock signal, a clock extraction system generally used in optical fiber transmission, and the like.
There are three clock selection schemes, which generate several types of clock signals having different phases from the system clock signal and select a clock signal suitable for synchronization.

The clock parallel transmission system is redundant because one channel is used for clock transmission, and skew is a serious problem in high-speed signals. The clock extraction method is described in P. Gray et al., "Analysis and Design of Analog
Integrated Circuits ", a method using a phase-locked loop PLL as described in John Wilay & Sons (1977), which extracts clock signals from data signals using analog circuit technology, but uses a feedback loop. Since the clock phase is locked and it takes time to extract the clock signal, this method is not suitable for a high-speed signal.

On the other hand, the clock selection method may be applicable to high-speed signals. A first conventional example of the clock selection method is a method of synchronizing data with a clock using a multi-phase clock or multi-phase data as described in Koizumi, JP-A-4-16032. This method uses a clock that has been precisely phased. However, for example, when a four-phase clock is used, for example, a phase margin of π or more is necessary. However, as the bit rate increases, the phase margin necessarily decreases. Therefore, in this method,
Bit synchronization at a bit rate of several Gb / s or more is difficult due to the performance limitations of electric circuits.

A second prior art example using a multiphase clock is also disclosed in A. Tajima et al., "A 10 Gb / s optical asy
nchronous cell / packet receiver with a fast bit-syn
chronization circuit ", Tech. Dig., ECOC'98, TuI6-1
(1998) a bit synchronization circuit as described in
In this bit synchronization circuit, operation at 10 Gb / s has been confirmed. However, in this method, the data and 4
Since the phase comparison with each of the phase clocks is performed digitally, the problem of the phase margin has been solved, but a multi-phase clock whose phase has been accurately adjusted is still required.

Further, a third conventional example is disclosed in H. Rokugawa et al.
l., "A Skew Free Receiver Circuit for Gigabit Opti
cal Parallel Interconnection ", Tech. Dig., ECOC'9
3, Wep10.5, p.93 (1998) is a method of detecting the phase by converting the phase relationship between clock and data into a pulse width. However, in this method, if the rise and fall times of the data and clock waveforms are about 50% or more of the data bit period, it becomes difficult to convert the phase relationship into a pulse width. Therefore, the first
As in the conventional example, there is a problem that it is not suitable for high-speed operation.

Further, a conventional example of a bit synchronization circuit developed to address the above problems and to realize a high-speed operation by simplifying the logical configuration will be described with reference to FIGS. 15, 16 and 17. FIG. FIG. 15 is a block diagram showing the entire configuration of a conventional example of this bit synchronization circuit, and FIG.
FIG. 17 is a timing chart for explaining the operation of this circuit. The conventional bit synchronization circuit shown in FIG. 15 includes a delay circuit DLY, a selector circuit SEL, and a phase detector PDET. The phase detector PDET shown in FIG. 16 includes a delay circuit DLY, two delay flip-flop circuits DFF, and an EXOR (exclusive OR) circuit EXO.
R and a toggle flip-flop circuit TFF.

As shown in FIG. 16, a phase detector PDET
Is divided into two, and one system is appropriately delayed by a delay circuit DLY, and then identified by each delay flip-flop circuit DFF by a common clock CLK of both systems. The output of both delay flip-flop circuits DFF is E
The signal is input to the XOR circuit EXOR. Here, when the results of the two delay flip-flop circuits DFF of the two systems match, the output of the EXOR circuit EXOR is 0, and when they do not match, the output is 1.

In FIG. 17, data D is applied by a clock CLK.
When identifying ATA1 and data DATA1 (DELAY), the data DA
D4 is obtained from TA1 and D3 is obtained from data DATA1 (DELAY). Since the data of D3 and the data of D4 are different, EX is obtained.
The output of the OR circuit EXOR becomes 1. When the output of the EXOR circuit EXOR is 1, the delay circuit DLY is output by the selector circuit SEL.
Side data DATA2 is selected. Here, the delay amount of the delay circuit DLY is set to about a half clock time of the reference clock signal.

When the same processing as that of data DATA1 is performed for data DATA2, data DATA2 (D
ELAY), D3 is obtained, and the output of the EXOR circuit EXOR becomes 0. Therefore, the output of this bit synchronization circuit is
Becomes DATA2. This circuit uses a mismatch between delayed data and non-delayed data, so that a preamble pattern having a large data change is used.

In this prior art, the logic configuration is simplified, and polyphase data and polyphase clocks are not used, so that bit synchronization can be performed for a high bit rate of 10 Gb / s or more. It is. However, when the time position at which the data signal is identified by the clock signal falls on the rising or falling time of the data signal, since the data signal has not been determined, a match or mismatch EXOR cannot be determined, and a dead phase occurs. There is a problem of doing.
When configuring a synchronous circuit using only digital circuit technology,
The logical position of the relative position between the data signal and the clock signal must be determined by logic 0 or 1. In this case, in order to eliminate the dead phase, the multi-phase clock and the multi-phase data, which are eventually multi-valued logic, are used. Had to be used.

[0012] Further, in the above-mentioned Patent Applications Nos. 10-323265 and 11-165641 based on the invention by the inventor of the present invention, the case where the data signal includes a preamble pattern composed of a specific clock signal is described. A proposed bit synchronization circuit is proposed.

[0013]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a bit synchronization circuit which can perform instantaneous synchronization without a dead phase and can operate even at a high bit rate of 10 Gb / s or more. It is another object of the present invention to provide a bit synchronization circuit which is not restricted by a preamble pattern.

[0014]

In order to achieve the above object, a bit synchronization circuit according to the present invention synchronizes an input first clock signal with the first clock signal and outputs one of the first clock signals. / 2, and the phases are mutually π / 2
Means for generating different second and third clock signals; first phase comparing means for comparing the phase of an input data signal with the phase of the second clock signal;
First sampling and holding means for sampling and holding the output amplitude of the phase comparing means, second phase comparing means for comparing the phase of the data signal with the phase of the third clock signal, and the second phase comparing means. Second sampling and holding means for sampling and holding the amplitude of the output;
A potential comparing means for comparing the output of the sampling and holding means with the output of the second sampling and holding means, and using the output of the potential comparing means to generate the first clock signal or the phase inverted signal of the first clock signal. It is characterized by comprising selecting means for selecting and outputting one of them, and means for outputting the data signal in synchronization with the output of the selecting means.

The second bit synchronizing circuit of the present invention synchronizes with the first clock signal from the input first clock signal, has a half frequency of the first clock signal, and has a phase mutually. Means for generating a second clock signal and a third clock signal which are different from each other by π / 2, first phase comparison means for comparing the phase of the input data signal with the phase of the second clock signal, and the first phase comparison First sampling and holding means for sampling and holding the amplitude of the output of the means, second phase comparing means for comparing the phase of the data signal with the phase of the third clock signal, and the output of the second phase comparing means. Second sampling and holding means for sampling and holding the amplitude; potential comparison for comparing the output of the first sampling and holding means with the output of the second sampling and holding means Stage, first output means for outputting the data signal based on the first clock signal, second output means for outputting the data signal based on a phase inversion signal of the first clock signal, and the potential comparison means And selecting means for selecting and outputting one of the output from the first output means and the output from the second output means using the output of (1).

The third bit synchronization circuit according to the present invention comprises: delay means for generating a second data signal obtained by delaying the first data signal from the input first data signal by a predetermined time; First phase comparing means for comparing the phase with the phase of the input clock signal, first sampling and holding means for sampling and holding the amplitude of the output of the first phase comparing means, and the phase of the second data signal Second phase comparing means for comparing the phase of the clock signal with the phase of the clock signal;
Second sampling and holding means for sampling and holding the amplitude of the output of the phase comparing means; potential comparing means for comparing the output of the first sampling and holding means with the output of the second sampling and holding means; Selecting means for selecting and outputting one of the first data signal and the second data signal by using an output of the means; and means for outputting the output of the selecting means in synchronization with the clock signal It is characterized by having.

The fourth bit synchronization circuit of the present invention synchronizes with the first clock signal from the input first clock signal, has a frequency half that of the first clock signal, and has a phase mutually. Means for generating a second clock signal and a third clock signal which are different from each other by π / 2, first phase comparing means for comparing the phase of an input data signal with the phase of the second clock signal, and the first phase comparing means First sampling and holding means for sampling and holding the amplitude of the output of the second clock signal, second phase comparing means for comparing the phase of the data signal with the phase of the third clock signal, and the amplitude of the output of the second phase comparing means Sampling and holding means for sampling and holding, and potential comparing means for comparing the output of the first sampling and holding means with the output of the second sampling and holding means A set / reset signal generating means for generating a set / reset signal from an output of the potential comparing means; and a first clock signal or a phase inversion signal of the first clock signal using an output of the set / reset signal generating means. Selecting means for selecting and outputting any one of the following, and means for outputting the data signal in synchronization with the output of the selecting means.

The fifth bit synchronization circuit of the present invention synchronizes with the first clock signal from the input first clock signal, has a half frequency of the first clock signal, and has a phase mutually. Means for generating a second clock signal and a third clock signal which are different from each other by π / 2, first phase comparing means for comparing the phase of an input data signal with the phase of the second clock signal, and the first phase comparing means First sampling and holding means for sampling and holding the amplitude of the output of the second clock signal, second phase comparing means for comparing the phase of the data signal with the phase of the third clock signal, and the amplitude of the output of the second phase comparing means Sampling and holding means for sampling and holding, and potential comparing means for comparing the output of the first sampling and holding means with the output of the second sampling and holding means Holding means for holding an output of the potential comparing means using a preamble extraction signal, and selecting one of the first clock signal and a phase inversion signal of the first clock signal using an output of the holding means; And a selector for outputting the data signal in synchronization with an output of the selector.

According to such a bit synchronization circuit of the present invention, the phase and amplitude of the data signal and the reference clock signal are compared, and bit synchronization can be performed instantaneously. In the bit synchronization circuit of the present invention, it is configured with simple logic, there is no dead phase in principle, and there is no feedback loop, so that the bit synchronization operation is performed instantaneously,
It is characterized in that the phase comparison between the data signal and the clock signal is performed in an analog manner, and the result of the phase comparison is sampled and held so as not to be restricted by the preamble pattern.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

[Embodiment 1] FIG. 1 is a block diagram showing a configuration of a bit synchronization circuit according to a first embodiment of the present invention, in which a toggle flip-flop circuit TFF, two phase comparison circuits PCMP,
It includes a voltage amplitude sampling and holding circuit AS / H, a potential comparison circuit VCMP, a delay flip-flop circuit DFF, and a selector circuit SEL. FIG. 6B is a block diagram showing a configuration of the embodiment of the phase comparison circuit PCMP, which includes an EXOR circuit EXOR and a low-pass filter LPF. FIG. 6D is a block diagram showing a configuration of an embodiment of the voltage amplitude sampling and hold circuit AS / H, and includes a delay circuit DLY, an EXOR circuit EXOR,
Includes sampling and hold switch circuit S / HSW and full-wave rectifier circuit FWR_P. FIG. 6A is a block diagram showing the configuration of the embodiment of the delay circuit DLY, and includes three amplifier circuits AMP. 7 is a circuit diagram of a potential comparison circuit VCMP, FIG. 9 is a circuit diagram of a full-wave rectifier circuit FWR_P, and FIG. 11 is a circuit diagram of a toggle flip-flop circuit TFF. FIG. 12 is a timing chart showing a configuration of a data signal.

The data signal input to the circuit of FIG.
Is a signal as shown in DATA1. Da0 with information
Before the subsequent data (payload), a preamble pattern is arranged as effective data when the bit synchronization circuit is broken. The preamble pattern is shown in FIG.
Clock data having a frequency of 1/2 of the external reference clock CLK as shown in DATA2 (for example, 0 and 1 when the data signal is an NRZ code which is frequently used in optical fiber communication)
) Is optimal, but any pattern having a relatively large number of change points of 0 and 1 may be used.

The operation of the bit synchronization circuit according to the first embodiment of the present invention will be described with reference to FIGS. 1, 12, 13 and 14. FIG. 13 is a timing chart for explaining the operation of the bit synchronization circuit of the present invention when the preamble portion is a clock, and FIG. 14 is a timing chart of the bit synchronization circuit of the present invention when the preamble portion has an arbitrary pattern instead of a clock. 6 is a timing chart for explaining an operation.

In FIG. 1, an external clock signal CLK is processed by a toggle flip-flop circuit TFF, and a clock signal CLK / 2 having a frequency half that of the input clock signal CLK.
Occurs. Here, as shown in FIG. 11, when the toggle flip-flop circuit TFF is of a master slave type, the frequency is あ り and four different phases (0,
(π / 2, π, 3π / 2) can be easily generated. Among them, the clock signal CLK / 2 having the phase of 0 and π / 2 and the input data signal are respectively supplied to the phase comparator P
Phase is compared by CMP.

First, a simple case in which the preamble pattern such as DATA2 in FIG. 12 has a frequency which is half the frequency of the clock signal CLK will be described. Phase comparison circuit PCMP
Then, the data signal DATA and the clock signal CLK / 2 are EXO
R is performed. For example, the angular frequency of the clock signal CLK / 2 is ω
c, assuming that the phase shift of the data signal DATA (preamble pattern) with respect to the clock signal CLK / 2 is φ, the voltage VA of the clock signal CLK / 2 and the voltage VB of the data signal (preamble pattern) are expressed by the following equations. (1A) and (1
B).

(Equation 1)

Here, a rectangular wave is assumed, and there are no even-order harmonics. The product of these two rectangular waves is given by the following equation (2).

(Equation 2)

The voltage product of the two clock signals is an even harmonic of the clock including the DC voltage. EXOR circuit EX
The OR acts as an analog mixer, and the inverted voltage product is output. By passing through a low-frequency pass filter LPF that cuts the second harmonic having the highest intensity, DC information including only the phase shift φ of the data signal (preamble pattern) based on the clock signal CLK / 2 is extracted. be able to. This DC component has a phase difference φ of nπ ±
It becomes 1 and becomes 0 at nπ / 2 (n is an odd number). Normal digital circuits operate with bi-phase input / output. The amplitude (voltage difference) of the two-phase output of the phase comparison circuit PCMP becomes 2 when the phase difference φ is nπ, and becomes 0 when nπ / 2 (n is an odd number).

In FIG. 13, DATA is an input data signal, DA
TA_PRE is the preamble pattern of the input data signal, CLK
Is an external clock signal, CLK / 2_π / 2 is a clock signal whose frequency is halved by the toggle flip-flop circuit TFF triggered by the falling edge of the external clock signal, and CLK / 2_0 is a toggle flip-flop triggered by the rising edge of the external clock signal. This is a clock signal obtained by dividing the frequency by で in the circuit TFF. The data preamble pattern DATA_PRE naturally has the same phase as the data signal DATA.

In the example of FIG. 13, DATA_PRE and CLK / 2_0
Or, when the phase is compared with CLK / 2_π / 2, DATA_PRE and CLK / 2_π
0 is a phase difference of about π, and DATA_PRE and CLK / 2_π / 2 are a phase difference of about π / 2. Further, the amplitude of the two-phase output of the phase comparison circuit PCMP is close to 2 in the case of CLK / 2_0, and CLK / 2_π /
In the case of 2, it is close to 0. That is, the amplitude of the two-phase output of the phase comparison circuit PCMP is smaller in the case of CLK / 2_π / 2.

Further, in this case, when the signal is identified by the delay flip-flop circuit DFF using the falling edge of the external clock signal CLK, it can be identified near the center of the data signal DATA. That is, the phase of DATA_PRE is compared with CLK / 2_0 or CLK / 2_π / 2, and when the amplitude of both phase outputs of the phase comparator circuit PCMP of CLK / 2_π / 2 is small, data is output using the falling edge of the external clock signal CLK. When the amplitude of both phase outputs of the phase comparison circuit PCMP of CLK / 2_0 is small, the data signal DATA is identified using the rising edge of the external clock signal CLK.
Is identified, data can always be identified near the center of the input data, and identification errors are extremely small. As described above, the amplitudes of the two outputs of the phase comparison circuit PCMP are compared, CLK / 2 having a small amplitude is selected, and a clock (positive or inverted) corresponding thereto is selected.

Next, a case where the leading preamble portion of the data signal DATA has an arbitrary pattern instead of a clock like DATA2 in FIG. 12 will be described with reference to FIG. Figure
At 14, DATA is an input data signal, CK is an external clock signal, and EXOR is an EXOR output of DATA and CK. Here, the time axis is divided by the data bit period T.

In the EXOR pattern of FIG. 14, the solid line is the DC voltage in the time section T, and the broken line is the DC voltage of the EXOR inverted pattern. In the time section in which the data signal DATA changes, the DC voltage of the EXOR takes the value shown by the equation (2).
The DC voltage of XOR becomes 0. Due to the phase relationship between the data signal DATA and the external clock signal CK, the DC voltage value of the EXOR is inverted between the sections of FIG. 14, but the voltage amplitude of the positive and inverted EXORs is constant. Sampling in the section where DATA changes, positive and inverted E
If the voltage amplitude of XOR is held, the preamble part
It can be handled in the same way as the case of a clock such as 12 DATA2.

The above operation is performed in the bit synchronization circuit shown in FIG. The data signal DATA and the external clock signal CLK are processed by a phase comparison circuit PCMP (EXOR circuit EXOR and low-pass filter LPF), and the phase comparison circuit PCMP outputs positive and inverted EXOR DC voltages. The voltage amplitude sampling and holding circuit AS / H samples and holds the positive and negative EXOR DC voltages in a section where the data signal DATA changes. The potential comparison circuit VCMP at the subsequent stage can be realized by a normal amplifier as shown in FIG. 7, and always selects the one with smaller amplitude. If a clock (positive or inverted) corresponding to the amplitude comparison result is selected to identify the data signal, the data can always be identified near the center of the input data as shown in FIG. Is extremely small.

In this clock selection method, the voltage amplitude of the positive and negative EXORs is sampled and held in the preamble pattern portion or the payload portion of the data signal and held constant, so that the preamble position in FIG. It is not necessary to input data such as data PRE. Further, since this clock selection method is based on phase comparison, there is no dead phase in principle even for data having a very small phase margin.

Voltage amplitude sampling and holding circuit AS
As an example of the configuration of / H, as shown in FIG. 6 (d), the delay circuit DLY and the EXOR circuit EXOR use a sampling section near the data change point (about T for one cycle of the clock signal CLK) from the data signal DATA. The voltage amplitude is extracted from the DC voltage of the positive and negative EXOR by the full-wave rectifier circuit FWR_P as shown in FIG. 9, and the sampling and hold switch circuit S / HSW as shown in FIG. The voltage amplitude is held only for the sampling section.

[Embodiment 2] FIG. 2 is a block diagram showing a configuration of a bit synchronization circuit according to a second embodiment of the present invention, which includes a toggle flip-flop circuit TFF, two phase comparison circuits PCMP,
It includes a voltage amplitude sampling and hold circuit AS / H, a potential comparison circuit VCMP, two delay flip-flop circuits DFF, and a selector circuit SEL. The bit synchronization circuit according to the second embodiment has a configuration in which clock selection by the selector circuit SEL in the first embodiment is replaced with data selection.

In this case, the input data is transferred to the clock signal CL.
First, the delay flip-flop circuit DFF is used to identify each of them using the inversion of K and the clock signal CLK, and identification data having the optimum phase relationship with the input data is selected by the selector circuit SEL. This delay flip-flop circuit DFF normally has the configuration shown in FIG.
A master slave configuration similar to the toggle flip-flop circuit TFF shown in FIG. In addition, a delay flip-flop circuit DFF for inputting an inverted clock signal CLK.
Is composed of three stages instead of a two-stage master slave configuration, it is possible to output identification data synchronized with the clock signal CLK, and the selector circuit SEL synchronizes either data with the clock signal CLK. Can be.

[Embodiment 3] FIG. 3 is a block diagram showing a configuration of a bit synchronization circuit according to a third embodiment of the present invention.
DLY, a toggle flip-flop circuit TFF, two phase comparison circuits PCMP, two voltage amplitude sampling and hold circuits AS / H, a potential comparison circuit VCMP, a selector circuit SEL, and a delay flip-flop circuit DFF. The bit synchronization circuit according to the third embodiment has a configuration in which clock selection by the selector circuit SEL in the first embodiment is replaced with data selection.

In this case, a phase difference is given to the data signal DATA instead of the clock signal. The delay circuit DLY immediately after the data input terminal delays about 1/2 bit. The toggle flip-flop circuit TFF only outputs a single-phase 1/2 clock signal.

[Embodiment 4] FIG. 4 is a block diagram showing a configuration of a bit synchronization circuit according to a fourth embodiment of the present invention, which includes a toggle flip-flop circuit TFF, two phase comparison circuits PCMP,
Voltage amplitude sampling and hold circuit AS / H, potential comparison circuit VCMP, set and reset signal generation circuit GRS,
It includes a selector circuit SEL and a delay flip-flop circuit DFF. The bit synchronization circuit according to the fourth embodiment has a configuration in which a set and reset signal generation circuit GRS is added to the subsequent stage of the potential comparison circuit VCMP in the first embodiment. The set and reset signal generation circuit GRS includes two potential comparison circuits VCMP and a set and reset flip-flop circuit, for example, as shown in FIG.

In this case, by adding the set and reset signal generation circuit GRS, there is an advantage that unnecessary fluctuations of the output of the potential comparison circuit VCMP are absorbed and the signal to the selector circuit SEL is stabilized. Furthermore, since a flip-flop circuit is employed internally, when new data is input to the circuit, a corresponding output can be instantaneously performed.
Therefore, there is an advantage that the speed of clock selection can be increased.

Fifth Embodiment FIG. 5 is a block diagram showing a configuration of a bit synchronization circuit according to a fifth embodiment of the present invention, which includes a toggle flip-flop circuit TFF, two phase comparison circuits PCMP,
It includes a voltage amplitude sampling and hold circuit AS / H, a potential comparison circuit VCMP, two delay flip-flop circuits DFF, and a selector circuit SEL. The bit synchronization circuit according to the fifth embodiment is provided after the potential comparison circuit VCMP according to the first embodiment.
For example, it has a configuration in which an identification circuit such as a delay flip-flop circuit DFF is added.

In this case, the delay flip-flop circuit DF
By adding F, it operates in synchronization with a preamble extraction signal indicating the head of data. Therefore, as a configuration of the input data, a preamble extraction signal PRE is required for the data signal DATA1. However, the selector circuit SEL of the clock signal CLK receives the preamble extraction signal PR
There is an advantage that it can be securely locked by E.
This is practical in a system in which the preamble extraction signal PRE can be easily obtained from the outside.

[0044]

As described above, according to the bit synchronization circuit of the present invention, (1) a phase comparison between sine waves is performed by using a clock signal that is phase-synchronized with data and a reference clock signal. Since the phase is detected, there is no dead phase in principle. (2) It is possible to perform bit synchronization at a high bit rate by using a simple logical decision that does not use a polyphase clock and polyphase data. 3) Since a delay line, an RC phase shifter, and the like are not used, operation at a frequency as long as the device operates is possible, and one circuit can support various frequencies, and is economical. 4) Open loop configuration, enabling instantaneous bit synchronization operation. (5) Use of a method of sampling and holding the result of phase comparison between a data signal and a clock signal. Rukoto there is no, the effects of the equal.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a bit synchronization circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a bit synchronization circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration of a bit synchronization circuit according to a third embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration of a bit synchronization circuit according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram illustrating a configuration of a bit synchronization circuit according to a fifth embodiment of the present invention.

FIG. 6A is a block diagram illustrating a configuration of an embodiment of a delay circuit DLY. (b) is a block diagram showing a configuration of an embodiment of a phase comparison circuit PCMP. (c) is a block diagram showing a configuration of an embodiment of a set and reset signal generation circuit GRS. (d) is a voltage amplitude sampling and hold circuit AS / H
FIG. 3 is a block diagram showing a configuration of the example.

FIG. 7 is a circuit diagram of a potential comparison circuit VCMP.

FIG. 8: Sampling and hold switch circuit S / HS
It is a circuit diagram of W.

FIG. 9 is a circuit diagram of a full-wave rectifier circuit FWR_P.

FIG. 10 is a circuit diagram of a potential comparison circuit FWR including a full-wave rectifier circuit.

FIG. 11 is a circuit diagram of a toggle flip-flop circuit TFF.

FIG. 12 is a timing chart showing a configuration of a data signal.

FIG. 13 is a timing chart for explaining the operation of the bit synchronization circuit of the present invention when the preamble part is a clock.

FIG. 14 is a timing chart for explaining the operation of the bit synchronization circuit of the present invention when the preamble portion has an arbitrary pattern instead of a clock.

FIG. 15 is a block diagram showing the overall configuration of a conventional bit synchronization circuit.

16 is a block diagram illustrating a configuration of a phase detection unit PDET in FIG.

FIG. 17 is a timing chart illustrating the operation of a conventional circuit.

[Explanation of symbols]

 AMP amplifying circuit AS / H voltage amplitude sampling and holding circuit DFF delay flip-flop circuit DLY delay circuit EXOR EXOR circuit FWR potential comparison circuit including full-wave rectification circuit FWR_P full-wave rectification circuit GRS set and reset signal generation circuit LPF low-frequency pass filter PCMP phase comparison circuit PDET phase detection unit R / SFF set and reset flip-flop circuit SEL selector circuit S / HSW sampling and hold switch circuit TFF toggle flip-flop circuit VCMP potential comparison circuit

Claims (5)

[Claims] 1. A bit synchronization circuit for outputting a data signal in synchronization with the first clock signal when a data signal and a first clock signal are input, wherein the first clock signal is changed from the first clock signal to the first clock signal. Means for synchronizing and generating a second clock signal and a third clock signal having a frequency half of that of the first clock signal and having phases different from each other by π / 2, and a phase of the data signal and the second clock. First phase comparing means for comparing a phase of a signal; first sampling and holding means for sampling and holding an amplitude of an output of the first phase comparing means; a phase of the data signal and a phase of the third clock signal; Second sampling means for sampling and holding the amplitude of the output of the second phase comparison means, and the first sampling and holding means. Potential comparing means for comparing the output of the loading means with the output of the second sampling and holding means, and using the output of the potential comparing means, either the first clock signal or the phase inverted signal of the first clock signal A bit synchronization circuit comprising: selection means for selecting and outputting one of them; and means for outputting the data signal in synchronization with an output of the selection means. 2. A bit synchronization circuit for outputting a data signal in synchronization with the first clock signal when a data signal and a first clock signal are input, wherein the first clock signal is changed from the first clock signal to the first clock signal. Means for synchronizing and generating a second clock signal and a third clock signal having a frequency half of that of the first clock signal and having phases different from each other by π / 2, and a phase of the data signal and the second clock. First phase comparing means for comparing a phase of a signal; first sampling and holding means for sampling and holding an amplitude of an output of the first phase comparing means; a phase of the data signal and a phase of the third clock signal; Second sampling means for sampling and holding the amplitude of the output of the second phase comparison means, and the first sampling and holding means. Potential comparing means for comparing the output of the second clocking means with the output of the second sampling and holding means; first output means for outputting the data signal based on the first clock signal; and a phase inversion signal of the first clock signal. A second output means for outputting the data signal based on the following: and selecting one of an output from the first output means and an output from the second output means using an output of the potential comparing means. A bit synchronization circuit comprising a selection means for outputting. 3. A bit synchronization circuit for outputting a first data signal in synchronization with a clock signal when a first data signal and a clock signal are input, wherein the first data signal is fixed from the first data signal. Delay means for generating a second data signal delayed in time; first phase comparison means for comparing the phase of the first data signal with the phase of the clock signal; sampling the amplitude of the output of the first phase comparison means First sampling and holding means for holding, second phase comparing means for comparing the phase of the second data signal with the phase of the clock signal, and the second for sampling and holding the amplitude of the output of the second phase comparing means. (2) a sampling and holding means, a potential comparing means for comparing an output of the first sampling and holding means with an output of the second sampling and holding means. A selecting means for selecting and outputting one of the first data signal and the second data signal by using an output of the potential comparing means; and synchronizing an output of the selecting means with the clock signal. A bit synchronizing circuit, comprising: means for outputting an output. 4. A bit synchronization circuit for outputting a data signal in synchronization with the first clock signal when the data signal and the first clock signal are input, wherein the first clock signal is changed from the first clock signal to the first clock signal. Means for synchronizing and generating a second clock signal and a third clock signal having a frequency half of that of the first clock signal and having phases different from each other by π / 2, and a phase of the data signal and the second clock. First phase comparing means for comparing a phase of a signal; first sampling and holding means for sampling and holding an amplitude of an output of the first phase comparing means; a phase of the data signal and a phase of the third clock signal; Second sampling means for sampling and holding the amplitude of the output of the second phase comparison means, and the first sampling and holding means. Potential comparing means for comparing the output of the potential comparing means with the output of the second sampling and holding means; set and reset signal generating means for generating a set and reset signal from the output of the potential comparing means; Using the output of the means,
Selecting means for selecting and outputting one of the first clock signal and a phase inversion signal of the first clock signal;
And a means for outputting the data signal in synchronization with the output of the selection means. 5. A bit synchronization circuit for outputting a data signal in synchronism with the first clock signal when a data signal, a first clock signal and a preamble extraction signal are input, wherein: Means for generating a second clock signal and a third clock signal which are synchronized with one clock signal, have a half frequency of the first clock signal, and have phases different from each other by π / 2; First phase comparing means for comparing the phase of the second clock signal; first sampling and holding means for sampling and holding the amplitude of the output of the first phase comparing means; phase of the data signal and the third clock Second phase comparing means for comparing the phase of the signal with the signal; second sampling and holding means for sampling and holding the amplitude of the output of the second phase comparing means; Potential comparing means for comparing the output of the sampling and holding means with the output of the second sampling and holding means; holding means for holding the output of the potential comparing means using the preamble extraction signal; and using the output of the holding means. Selecting means for selecting and outputting one of the first clock signal and the phase inversion signal of the first clock signal; and means for outputting the data signal in synchronization with the output of the selecting means. A bit synchronization circuit.