JP3338659B2 - Bit synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bit synchronization circuit which is a component of an electronic circuit in digital communication.

[0002]

2. Description of the Related Art In packet communication, the timing of packets arriving at an exchange differs in each line. When receiving packets with random phases, a bit synchronization circuit that matches the data phase with the system clock is effective to identify and reproduce data without error. Also, in the optical interconnection technology, which has been attracting attention as a technology for greatly reducing the wiring between switchboards, a bit for adjusting the phase of data input in parallel after O / E conversion has been performed on the optical interconnection receiving side. A synchronization circuit is required.

The prior art is disclosed in Japanese Patent Laid-Open No. 4-16032.
As described in the publication, there is a method of synchronizing data with a clock using a multiphase clock or multiphase data.
This method requires a clock whose phase has been accurately adjusted, and requires a phase margin of 180 ° or more when a four-phase clock is used. However, as the bit rate increases, the phase margin necessarily decreases. In this method, bit synchronization at a bit rate of 1 Gb / s or more is difficult due to the performance limit of an electric circuit.

Also, H. Rokugawa et.al., "A Skew Free
Receiver Circuit for Gigabit Optical Parallel Inte
rconnection "(Tech.Dig.ECOC'93, Wep10.5, p.63), there is a method of detecting the phase by converting the phase relationship between clock and data into a pulse width. ,
In this method, when the rising or falling time of the data and clock waveforms becomes about 50% or more of the data bit period, it becomes difficult to convert the phase relationship into a pulse width. Therefore, similar to the above method,
There is a disadvantage that it is not suitable for high-speed operation.

FIG. 1 shows an example of the configuration of a bit synchronization circuit developed to compensate for such a drawback, simplify the logic configuration, and enable high-speed operation. FIG. 2 is a block diagram of a phase detection unit PDET serving as a core of the bit synchronization circuit. The operation of these circuits will be described with reference to a signal timing chart in FIG. The data input to the phase detector PDET is 2
Branching is performed, and one system is given an appropriate delay by a delay circuit DLY, and each is identified by a delay flip-flop circuit DFF with the same clock. The output of the delay flip-flop circuit DFF is input to the exclusive OR EXOR. Here, if the results of the two systems of the delay flip-flop circuits DFF match, the output of the exclusive OR EXOR is 0 and must not match. In this case, the output becomes 1.

[0006] As shown in FIG.
When distinguishing DATA1 from delayed data DATA2 (DELAY), DA
D1 is obtained from TA1 and D3 is obtained from DATA2 (DELAY).
When the data of 3 and D4 are different, the output of the exclusive OR EXOR becomes 1. When the output of the exclusive OR EXOR is 1, the selector circuit SEL in FIG.
Select the data DATA2 on the Y side. Here, the delay circuit DLY
Is set to about half a clock time of the reference clock signal. When the same processing as DATA1 is performed for DATA2, D2 is obtained from both DATA2 and DATA2 (DELAY).
3 is obtained, and the exclusive OR EXOR output becomes 0. Therefore, the output of this bit synchronization circuit is DATA2. This circuit uses a mismatch between delayed data and non-delayed data, so that a preamble pattern having a large data change is used.

In this technique, the logical configuration is simplified, and since polyphase data and polyphase clock are not used,
Bit synchronization can be performed for a high-speed bit rate of 10 Gb / s or more. However, if the time position at which data is identified by the clock falls on the rising edge or falling edge of the data, the data is not determined, so that a match or mismatch EXOR determination cannot be made. Therefore, a dead phase occurs. When a synchronous circuit is constituted only by digital circuit technology, theoretical determination must be made with the relative position between data and clock being 0/1. The only way to eliminate this dead phase is to use a multi-phase clock or multi-phase data, which is also multi-valued logic.

As a method of extracting a clock component from data information by analog circuit technology, P. Gray et al.,
"Analysis and Design of Analog Integrated Circuit
s "(John Wilay & Sons, 1997), using a phase-locked loop PLL.
In this method, the phase comparison circuit PCMP-low-pass filter LP
Since a feedback loop called F-voltage controlled oscillator VCO is used, there is a disadvantage that it takes time until the clock phase is locked.

[0009]

As described above,
In the conventional technology, a method of synchronizing data with a clock using a multiphase clock or multiphase data, and synchronizing data with a clock by performing phase detection by converting a phase relationship between the clock and data into a pulse width and performing phase detection. Methods have been devised, but these have been difficult to operate at bit rates of 1 Gb / s and higher. In addition, a method has been devised in which the logic configuration is simplified and data is synchronized with a clock using only two-phase data using a delay, which can operate at a high bit rate of about 10 Gb / s. However, there is a disadvantage that a dead phase exists.

An object of the present invention is to provide a bit synchronization circuit which can operate even at a high bit rate of 10 Gb / s or more, has no dead phase, and can perform instantaneous synchronization.

[0011]

In order to achieve the above object, a bit synchronization circuit according to the present invention has a configuration including a delay circuit, a phase comparison circuit, an amplitude comparison circuit or a potential comparison circuit, and synchronizes with a data phase. It is characterized in that bit synchronization is performed by comparing the phase of the synchronized clock signal with the reference external clock signal.

According to the bit synchronization circuit of the present invention, since the phase comparison is performed between the clock signals and the synchronization determination is performed using a circuit which operates partially in analog with the digital circuit, the configuration becomes simple. Since there is no dead phase and no feedback loop, bit synchronization can be performed instantaneously.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 4 is a block diagram showing a first embodiment of the bit synchronization circuit according to the present invention, and FIG.
To (f) denote the delay circuit DL,
FIG. 4 is a block diagram showing a configuration example of Y, a phase comparison circuit PCMP, an amplitude comparison circuit ACMP 1, an amplitude comparison circuit ACMP 2, a Manchester decoding and clock extraction circuit CKREC, and a potential comparison circuit (differential amplifier) VCMP.

The data signal input to the bit synchronization circuit in FIG. 4 has a configuration like DATA1 in FIG. In this configuration, data after Da0 that contains information (payload)
, Clock data having a half frequency of the external reference clock signal CLK is included as a preamble pattern. For example, when the data signal is an NRZ code most frequently used in optical fiber communication, the preamble pattern is a repetition of 0 and 1. PRE is data indicating a preamble position, and is data that becomes 1 in a preamble pattern portion.

Next, the operation of the bit synchronization circuit of the present invention will be described with reference to FIGS. In FIG. 4, the input signal
DATA first branches into two, and one system enters the delay circuit DLY,
Receive delay. The delay amount is about a half clock of the reference clock signal CLK. The data signal and the delayed data signal are supplied to an external reference clock signal CLK by a phase comparison circuit PCMP.
The phase is compared with a clock signal CLK / 2 having a frequency of 1/2 of the clock generated from. When the data signal is the leading preamble portion, the data signal and the clock signal CLK / 2 are first input to the exclusive OR EXOR in the phase comparison circuit PCMP.

For example, if the angular frequency of the clock signal CLK / 2 is ω _c and the phase shift of the data signal (preamble pattern) with respect to the clock signal CLK / 2 is φ, the voltage V _A of the clock signal CLK / 2 is obtained. , The voltage V _B of the data signal (preamble pattern) is expressed as follows.

(Equation 1)

(Equation 2)

This assumes a square wave and no even harmonics. The product of these two rectangular waves is as follows.

(Equation 3)

Therefore, the voltage product of the two clock signals is D
It becomes an even harmonic of the clock including the C voltage. The exclusive OR EXOR is an inverted output of this voltage product. A low-pass filter that cuts the strongest second harmonic
When the signal passes through the LPF, a D signal including a phase shift φ of the data signal (preamble pattern) based on the clock signal CLK / 2
Only C information can be extracted. This DC component is ± 1 when the phase difference φ is nπ and is 0 when nπ / 2 (n is an odd number).
Becomes

In FIG. 7, DATA is an input data signal, CLK-DATA
Is the preamble pattern, DATA (DELAY) is the input data signal passed through the delay circuit, and CLK-DATA (DELAY) is the preamble pattern. CLK is an external reference clock signal, and CLK / 2 is a clock signal whose frequency is 分 divided by a toggle flip-flop (frequency dividing circuit) TFF triggered by the fall of the external reference clock signal CLK. Each data preamble pattern naturally has the same phase as the data signal.

In the figure, CLK-DATA and CLK-DATA (DELAY) and CLK / DATA
Comparing the phase with 2, the CLK-DATA and CLK / 2 are approximately π / 2
, CLK-DATA (DELAY) and CLK / 2 have a phase difference of about π. For DATA near the phase difference of about [pi / 2, when identified in the delay flip-flop circuit DFF with CL ^1, DATA
Can be identified near the center of. On the other hand, in the case of DATA (DELAY) having a phase difference of about π, it is identified near the data change point. When the amplitude of the exclusive OR EXOR output (difference between positive logic and negative logic) is taken out, the amplitude is large when the phase difference φ is close to nπ, and is large when the phase difference φ is close to nπ / 2 (n is an odd number). Becomes smaller. Therefore, when the amplitude of the exclusive OR EXOR output is small, it is possible to identify near the center of the data with an external clock, and the identification error is extremely small.

From the above, in order to reduce the identification error, two outputs of the phase comparison circuit PCMP are connected to the amplitude comparison circuit.
It can be seen that a path having a small amplitude may be selected by inputting to the ACMP and determining whether or not there is a delay circuit.
The amplitude comparison circuit ACMP always selects only the one with the smaller amplitude, and there is no dead phase even for data with an extremely small phase margin.

The configuration of the amplitude comparison circuit ACMP can be as shown in FIGS. 5 (c) and 5 (d). The full-wave rectifier circuit FWR in the figure can be configured as shown in FIG. Further, a diode may be used as a half-wave rectifier circuit to form a ring-shaped circuit. FIG.
The circuit (d) is a circuit in which an external DC voltage is input to one of the two terminals of the full-wave rectifier circuit FWR at the subsequent stage and is used as a threshold value. In this case, if the phase difference of the preceding full-wave rectifier circuit FWR does not exceed this threshold value, 0 is output.
Actually, the external clock may enter the data transition region only when the output of the full-wave rectifier circuit FWR that performs amplitude comparison is sufficiently large, and the path may be changed only in that case. Providing a threshold value is effective to prevent useless route change.

Further, this route selection is performed by a preamble pattern of data, and when data having information following the data comes in, it is necessary to fix the route selection.
Therefore, data indicating the position of the preamble pattern is input from outside as shown in PRE of FIG. 6, and the selector circuit SEL after the amplitude comparison circuit ACMP is controlled by the data PRE indicating the preamble position. Is fixed. The data is bypassed from before the phase comparison circuit PCMP and is selected and output by the second-stage selector circuit SEL.

[Second Embodiment] FIG. 9 is a block diagram showing a second embodiment of the bit synchronization circuit according to the present invention. Of the two-stage path selecting portion of the selector circuit SEL in FIG. 4 of the first embodiment, FIG. This is a configuration in which the selector circuit SEL in the preceding stage is replaced by a delay flip-flop circuit DFF. In this case, the pattern PRE of FIG. 6 indicating the end of the preamble pattern position
Can be used as a clock for the delay flip-flop circuit DFF.

[Third Embodiment] FIG. 10 is a block diagram showing a third embodiment of the bit synchronization circuit according to the present invention, except for the toggle flip-flop TFF of the external reference clock signal CLK in FIG. 4 of the first embodiment. It has a configuration. The data signal input to the bit synchronization circuit of FIG.
It has the following configuration. This configuration contains information
Before the data (payload) after Da0, clock data having the same frequency as the external reference clock signal CLK is included as a preamble pattern. For example, when the data signal is a Manchester code, this preamble pattern can be carried on the data signal as a repetition of 0 or a repetition of 1.

If the data signal is a Manchester code, (10) is sent for 0 and (01) for 1 b
This is an iphase code, and the center of the data is a change point. Therefore, in order to identify this Manchester code with the most error by synchronizing the bit with the external reference clock signal CLK, the phase difference between the preamble pattern synchronized with the data and the external clock signal is nπ / 2 (n is an odd number). It is necessary to be. Therefore, as described in the first embodiment,
By performing phase comparison and amplitude comparison between the external clock signal and a preamble pattern having the same frequency as the clock signal, bit synchronization can be obtained.

Fourth Embodiment FIG. 11 is a block diagram showing a fourth embodiment of the bit synchronization circuit according to the present invention. When the clock signal can be easily extracted from the data signal as in the case of the Manchester code, the clock signal is first extracted by the Manchester decoding and clock extraction circuit CKREC on the data input side. FIG. 5E shows a configuration example of the Manchester decoding and clock extraction circuit CKREC. In this circuit CKREC, the extracted clock signal OUT2 is input to the phase comparison circuit PCMP and further to the potential comparison circuit VCMP. on the other hand,
The data signal OUT1 decoded to NRZ is supplied to a phase comparison circuit
In response to the comparison result of the PCMP and the potential comparison circuit VCMP, a path is selected in the selector circuit SEL. In this case, since the PRE indicating the preamble pattern position can be omitted, the number of selector circuits SEL can be reduced by one.

Further, in this embodiment, the phase of the clock signal extracted from the clock and the phase of the decoded data signal are synchronized. When the phase difference between the extracted clock signal and the external reference clock signal is 0, it can be identified at the edge of the NRZ code data signal, and when the phase difference is π, it can be identified at the center. The phase comparison circuit PCMP has the maximum (cos
(0) = 1), and outputs a minimum (cos (π) = − 1) voltage with a phase difference π. Therefore, as shown in FIG. 11, it is preferable to input the result of this phase comparison to the potential comparison circuit VCMP and select the smaller one.

[0030]

As described above, the bit synchronization circuit of the present invention performs phase detection by comparing the phases of sine waves with each other using a clock signal that is phase-synchronized with data and a reference clock signal. In principle, there is no dead phase, simple logic judgment that does not use multi-phase clock or multi-phase data enables high-speed bit rate bit synchronization, and instantaneous bit It has features such as being capable of synchronous operation, and has a very large practical effect.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration example of a conventional bit synchronization circuit.

FIG. 2 is a block diagram of a phase detector PDET of a conventional bit synchronization circuit.

FIG. 3 is a timing chart of signals in the circuit of FIG. 1;

FIG. 4 is a block diagram showing a first embodiment of the bit synchronization circuit of the present invention.

FIG. 5 is a block diagram showing a configuration example of each component of the bit synchronization circuit of the present invention.

FIG. 6 is a diagram showing a configuration of a signal input to a bit synchronization circuit of the present invention.

FIG. 7 is a timing chart of signals in the circuit of FIG. 4;

FIG. 8 is a circuit diagram illustrating a configuration example of a full-wave rectifier circuit.

FIG. 9 is a block diagram showing a second embodiment of the bit synchronization circuit of the present invention.

FIG. 10 is a block diagram showing a third embodiment of the bit synchronization circuit of the present invention.

FIG. 11 is a block diagram showing a fourth embodiment of the bit synchronization circuit of the present invention.

[Explanation of symbols]

 ACMP Amplitude comparison circuit AMP amplifier CKREC Manchester decoding and clock extraction circuit CLK Reference clock signal DFF Delay flip-flop circuit DLY Delay circuit EXOR Exclusive OR FWR Full-wave rectifier LPF Low-pass filter PCMP Phase comparator PDET Phase detector PRE Data indicating the preamble position SEL selector circuit TFF Toggle flip-flop circuit (frequency divider) VCMP potential comparator (differential amplifier)

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-3-255743 (JP, A) JP-A 9-149026 (JP, A) JP-A 4-16032 (JP, A) Kiyomitsu Onodera Keishi Habara, 10Gbps Instantaneous Bit Synchronization Circuit Using Phase Comparison / Amplitude Comparison Circuit, IEICE National Convention, 00-Autumn-Electronics Society 2, C-12-31 (58) Fields surveyed (Int. Cl. ^7, DB name) H04L 7/04 H04L 7/02

Claims (3)

(57) [Claims] 1. A bit synchronization circuit including a delay circuit, a phase comparison circuit, and an amplitude comparison circuit, to which a first clock signal and a first data signal serving as a reference are input, wherein a first data signal transmits information data to be transmitted. A second portion including a second clock signal having a frequency half that of the first clock signal and being synchronized with the first data signal in a preceding portion, including a first data path and a first delay circuit; And two branches to the data path, synchronized with the first clock signal and 1/1 of the first clock signal.
A third clock signal generated from the first clock signal at a frequency of 2 and a fourth clock signal included in the second data signal passing through the first data path by a first phase comparison circuit; And a fifth clock signal included in the third data signal that has passed through the second data path. The second phase comparison circuit compares the phases of the signals and the first phase comparison circuit and the second phase comparison circuit compare the result of the phase comparison with the first amplitude. The first comparison is performed by comparing the amplitude in the comparison circuit.
A bit synchronization circuit which instantaneously selects one of a data path and a second data path and outputs a first data signal in synchronization with a first clock signal. 2. A bit synchronization circuit including a delay circuit, a phase comparison circuit, and an amplitude comparison circuit, which receives a first clock signal and a first data signal as a reference, wherein a first data signal transmits information data to be transmitted. A second data path including a second clock signal having the same frequency as the first clock signal and being synchronized with the first data signal in a previous portion, and including the first data path and the first delay circuit; The first clock signal and the fourth clock signal included in the second data signal passing through the first data path are compared in phase by a first phase comparator, and the first clock signal and the second data path are compared. The second clock signal included in the passed third data signal is compared in phase by the second phase comparison circuit, and the result of the phase comparison in the first phase comparison circuit and the second phase comparison circuit is compared by the first amplitude comparison circuit. The by amplitude comparison in 1
A bit synchronization circuit which instantaneously selects one of a data path and a second data path and outputs a first data signal in synchronization with a first clock signal. 3. A bit synchronization circuit that includes a delay circuit, a phase comparison circuit, and a potential comparison circuit and receives a first clock signal and a first data signal as a reference, wherein the first data signal is supplied to a first clock extraction circuit. Enter first
Generating a second clock signal synchronized with the data signal; branching the first data signal into a first data path and a second data path including a first delay circuit; dividing the second clock signal into a first clock path and a second data path; A second clock path including two delay circuits; a first clock signal and a third clock signal passing through the first clock path; The phase of the fourth clock signal having passed through the path is compared in the second phase comparator, and the result of the phase comparison in the first phase comparator and the second phase comparator is compared in the first potential comparator.
A bit synchronization circuit which instantaneously selects one of a data path and a second data path and outputs a first data signal in synchronization with a first clock signal.