JP3495952B2 - Bit synchronization circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to digital communication,
The present invention relates to a bit synchronization circuit which is a constituent element of an electronic circuit used for optical interconnection and the like.

[0002]

2. Description of the Related Art In packet communication, the timing of packets arriving at an exchange differs on each line. A bit synchronization circuit that matches the phase of input packet data with the system clock is effective for identifying and reproducing data without error when receiving packets with irregular phases. In addition, even in optical interconnection technology, which is drawing attention as a technology for significantly reducing the size of wiring between switchboards, a bit synchronization circuit that aligns the phases of data input in parallel after photoelectric conversion on the receiving side of the optical interconnection. is necessary.

As a first conventional technique, there is a method of synchronizing data with a clock using a multi-phase clock or multi-phase data, as described in Kokai Izumi in Japanese Patent Laid-Open No. 4-16032. This method requires a clock whose phase is adjusted accurately and requires a phase margin of π or more when using a four-phase clock. However, the higher the bit rate, the smaller the phase margin. Due to the performance limitation of electric circuits, bit synchronization at a bit rate of 1 Gb / s or more is difficult by this method.

As a second conventional technique, a paper "A 10 Gb / s optical asynchronous cell / packet rece" by A. Tajima et al.
iver with a fast bit-synchronization circuit '' (Tec
h.Dig., ECOC'98, TuI6-1), there is a bit synchronization circuit using a multiphase clock. In this paper, it was confirmed that the operation at 10 Gb / s was confirmed, but since the phase comparison between each of the four-phase clocks and the data is performed digitally, the problem of phase margin has been solved, but the phase adjustment is accurate. There is still a need for an optimized multiphase clock.

As a third conventional technique, the paper "A Skew Free Receiver Circuit for Gigabit Opt" by H. Rokugawa et al.
ical Parallel Interconnection "(Tech.Dig., ECOC'9
3, Wep10.5.p.63), there is a method of detecting the phase by converting the phase relationship between the clock and data into a pulse width. However, with this method, it becomes difficult to convert the phase relationship into a pulse width when the rising or falling time of the data and clock waveforms is about 50% or more of the data bit period. Therefore, as in the case of the above-mentioned JP-A-4-16032, there is a drawback that it is not suitable for high speed operation.

As a fourth conventional technique, FIG. 11 shows an example of the construction of a bit synchronization circuit developed for compensating the above drawbacks and simplifying the logic construction to realize a high speed operation. FIG. 11 (a) is a block diagram showing the entire configuration, and FIG. 11 (b) is a block diagram showing details of the phase detection unit (PDET) which is one of the constituent elements of FIG. 11 (a). FIG. 12 is a diagram for explaining the operation of this circuit. The data input to PDET is split into two,
One line is delayed by a delay circuit (DLY) and identified by a delay flip-flop circuit (DFF) with the same clock. The DFF output is input to the exclusive OR (EXOR), where the EXOR output becomes 0 if the results of the DFFs of the two systems match, and the EXOR output becomes 1 if they do not match. As shown in Figure 12, data DATA1 and data DATA1 at clock CLK
When identifying (DELAY), D4 from DATA1
Since EX3 is obtained from (ELAY), EXOR output becomes 1. E
When the XOR output is 1, the selector circuit (SEL) in Figure 11 (a)
Use to select the data DATA2 on the DLY side. Here, the delay amount of DLY is set to about a half clock time of the reference clock signal. When the same processing as the data DATA1 is performed on the data DATA2, D3 is obtained from both DATA2 and DATA2 (DELAY), and the EXOR output becomes 0. Therefore, the output of this bit synchronization circuit becomes DATA2. Since this circuit uses the disagreement between the delayed data and the undelayed data, the preamble pattern is a pattern in which the data changes a lot.

In the fourth prior art, since the logical structure is simplified, the multi-phase data and the multi-phase clock are not used, so that the bit synchronization is performed for the high bit rate of 10 Gb / s or more. It is possible. However,
If the time position for identifying the data with the clock hits the rising edge or the falling edge of the data, the data is not determined, and therefore EXOR judgment of coincidence or disagreement cannot be made. Therefore,
A dead phase occurs. When the synchronous circuit is constructed only by digital circuit technology, the relative position between the data and the clock must be logically judged to be 0 or 1. The only way to eliminate this dead phase is to use multiphase clocks and multiphase data that are multivalued logic.

As a fifth prior art, in order to extract a clock component from data information by analog circuit technology,
P. Gray and other books `` Analysis and Design of Analog Inte
There is a method using a phase locked loop (PLL) as described in "Grated Circuits" (John Wilay & Sons, 1977). However, this method uses a feedback loop including a phase comparison circuit, a low pass filter, and a voltage controlled oscillator, and has a drawback that it takes time to lock the clock phase.

[0009]

In view of the above situation, the present invention operates at a high bit rate of 10 Gb / s or more without using a polyphase clock and polyphase data, and has no dead phase and can be instantaneously operated. An object of the present invention is to provide a bit synchronization circuit that can perform synchronization.

[0010]

In order to achieve the above object, the bit synchronization circuit of the present invention has a first clock signal and a half of the first clock signal as a preamble pattern.
Is a bit synchronization circuit that receives as input a data signal including a second clock signal having a frequency of, and has a frequency of ½ of the first clock signal and a phase of π / 2 means for outputting different 3rd clock signals and 4th clock signals, 1st phase comparing means for comparing the phases of the 2nd clock signal and 3rd clock signal, 2nd clock signal and 4th clock signal Second to compare
Output of the amplitude comparing means and the amplitude comparing means for comparing the amplitude of the output voltage of the phase comparing means and the first phase comparing means with the amplitude of the output voltage of the second phase comparing means to select a clock signal suitable for selecting the data signal. Holding means for holding the signal except for the time when the second clock signal exists, selecting means for selecting and outputting either the first clock signal or the phase inversion signal of the first clock signal with the output of the holding means as a control signal, and And a means for outputting a data signal in synchronization with the output of the selecting means.

Another bit synchronization circuit of the present invention is a bit synchronization circuit which receives as input a data signal including a first clock signal and a second clock signal having a frequency of ½ of the first clock signal as a preamble pattern. First
A means for outputting a third clock signal and a fourth clock signal which are in synchronism with the clock signal and have a frequency of ½ of that of the first clock signal and different in phase from each other by π / 2, second clock signal and third clock signal Of the output voltage of the first phase comparison means and the second phase comparison means for comparing the phases of the second clock signal and the fourth clock signal. Amplitude comparison means for comparing with the amplitude of the output voltage to select a clock signal suitable for selection of the data signal, holding means for holding the output of the amplitude comparison means except the time when the second clock signal exists, and the first data signal A first synchronizing circuit that outputs in synchronization with a clock signal, a second synchronizing circuit that outputs a data signal in synchronization with a signal obtained by inverting the phase of the first clock signal, and an output of the holding means. Characterized by comprising a selection means for selecting and outputting one of the outputs of the output or the second synchronizing circuit of the first synchronizing circuit as control signals.

Yet another bit synchronization circuit of the present invention is a first bit synchronization circuit.
A bit synchronization circuit which receives as input a data signal including a second clock signal having the same frequency as the first clock signal as a preamble pattern of the clock signal and the information data, the phase of the first clock signal and the second clock signal And a second phase signal comparing means for comparing the phases of the phase inversion signal of the first clock signal and the second clock signal.
The output of the phase comparison means, the voltage comparison means for comparing the output voltage of the first phase comparison means with the output voltage of the second phase comparison means to select the clock signal suitable for the selection of the data signal, Holding means for holding except the time when two clock signals exist, selecting means for selecting and outputting either the first clock signal or the phase inversion signal of the first clock signal using the output of the holding means as a control signal, and selecting It is characterized by comprising means for outputting a data signal in synchronization with the output of the means.

Still another bit synchronization circuit of the present invention is a first bit synchronization circuit.
A bit synchronization circuit which inputs a clock signal, a data signal, and a second clock signal which is synchronized with the data signal and has the same frequency as that of the first clock signal, wherein the phase of the first clock signal and the second clock signal Of the first phase comparison means, the second phase comparison means for comparing the phase of the phase inversion signal of the first clock signal and the phase of the second clock signal, and the output voltage of the first phase comparison means and the second phase comparison means. A voltage comparison unit that compares a voltage of the output with a clock signal suitable for selecting a data signal, and selects either the first clock signal or a phase inversion signal of the first clock signal with the output of the voltage comparison unit as a control signal. And selecting means for outputting the data signal, and means for outputting the data signal in synchronization with the output of the selecting means.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a first embodiment of a bit synchronization circuit of the present invention. As a component, a toggle flip-flop circuit (TFF), two phase comparison circuits are provided.
(PCMP), amplitude comparison circuit (ACMP), two delay flip-flop circuits (DFF) and selector circuit (SEL). Figure 2
It is a block diagram showing a detailed configuration example of PCMP and ACMP,
The PCMP shown in FIG. 2 (a) includes an exclusive OR (EXOR) and a low pass filter (LPF), and the first example of the ACMP shown in FIG. 2 (b) is
ACMP including full-wave rectification circuit (FWR) and LPF shown in Fig. 2 (c)
The second example further includes an FWR and an AND circuit (AND).

FIG. 3 is a diagram showing signal waveforms applied to the bit synchronization circuit of FIG. DATA1 is the waveform of the data signal input to the bit synchronization circuit and contains information
Before the data (payload) after Da0, clock data having a frequency of 1/2 of the external reference clock CLK is included as a preamble pattern. For example, when the data signal is an NRZ code which is frequently used in optical fiber communication,
The preamble pattern is a repetition of 0's and 1's. PR
E is data that indicates the preamble position, and is data that becomes 1 in the preamble pattern portion. Also,
DATA2 is the waveform of the data signal input to the bit synchronization circuit. Before the data after Da0 that contains information,
Clock data of the frequency of the external reference clock CLK is included as a preamble pattern.

FIG. 4 is a diagram showing operation waveforms of the bit synchronization circuit of FIG. The external reference clock signal CLK is processed by TFF to generate a clock signal CLK / 2 having a frequency half that of the input clock signal CLK. Here, when the TFF is a master-slave type as shown in the circuit diagram of FIG. 5, the frequency is 1/2 and four different phases (0, π / 2, π,
It is possible to easily generate a clock of 3π / 2).
Among them, the clock signal CLK / 2 having a phase of 0 and π / 2 and the input data signal are respectively compared in phase by PCMP. When the input data signal is the head preamble portion, the data signal and the clock signal are first input to EXOR in PCMP.

For example, if the angular frequency of the clock signal CLK / 2 is ω _c and the phase shift of the data signal (preamble pattern) with reference to the clock signal CLK / 2 is φ, then the voltage V _A of the clock signal CLK / 2 The voltage V _{B of the} preamble pattern is expressed as follows.

[Equation 1]

This assumes a square wave, and there are no even harmonics. The product of these two square waves is

[Equation 2]

Therefore, the voltage product of the two clock signals is D
It is an even harmonic of the clock including the C voltage. EXOR is
It acts as an analog mixer and outputs the inverse of this voltage product. If you pass a low-pass filter that cuts the second harmonic with the highest intensity, the clock signal CLK /
It is possible to extract the DC information including only the phase shift φ of the preamble pattern with reference to 2. This DC component is ± 1 when the phase difference φ is nπ, and is n when n is an odd number.
It becomes 0 at π / 2. A normal digital circuit operates with both-phase input / output. Therefore, considering the amplitude (voltage difference) of the two-phase outputs of the above PCMP, the amplitude is 2 when the phase difference is nπ, and the amplitude is 0 when n is odd and nπ / 2.

A specific operation will be described with reference to FIG. In FIG. 4, DATA is an input data signal, DATA-PRE is a preamble pattern of the input data signal, CLK is an external clock signal, and CLK / 2-0 is a clock divided by 1/2 by TFF triggered by the rising edge of the external clock signal. Signal, CLK / 2-π / 2
Is 1 at TFF triggered by the falling edge of the external clock signal
A clock signal divided by two, CLK / 2-0 and CLK / 2-π
The phase differs from / 2 by π / 2. The data preamble pattern DATA-PRE naturally has the same phase as the data signal DATA. In the example of Figure 4, DATA-PRE and CLK / 2-0 or CL
Comparing the phases of K / 2-π / 2, the phase difference between DATA-PRE and CLK / 2-0 is about π, and the difference between DATA-PRE and CLK / 2-π / 2 is about π /.
The phase difference is 2. Therefore, the amplitude of both phase output of PCMP is
It is close to 2 for CLK / 2-0 and close to 0 for CLK / 2-π / 2. That is, the amplitude of the two-phase output of PCMP is smaller in the case of CLK / 2-π / 2. Further, in this case, when the DFF is used for identification using the falling edge of the external clock signal CLK, it can be identified near the center of DATA.

That is, DATA-PRE and CLK / 2-0 and CLK / 2-π / 2
When the phase of CLK / 2-π / 2 is small and the amplitude of both outputs of PCMP is small, DA is calculated by using the falling edge of external clock signal CLK.
If TA is identified and conversely, if the amplitude of both-phase outputs of PCMP of CLK / 2-0 is small, DATA is identified using the rising edge of the external clock signal CLK (falling edge of the inversion of the external clock signal CLK). Data can always be identified near the center of the input data, and identification errors are extremely small.

From the above, the two outputs of the phase comparison circuit are input to the amplitude comparison circuit, and CLK / 2 having a small amplitude is selected.
It can be seen that the corresponding clock (positive or inverted) should be selected. Since the amplitude comparison circuit always selects only the smaller amplitude, there is no dead phase in principle even for data with a very small phase margin.

This amplitude comparison circuit can be constructed as shown in FIGS. 2 (b) and 2 (c). The FWR in these figures can be configured as shown in FIG. In addition, this may be configured by combining diodes in a ring shape as a half-wave rectifier circuit. The ACMP of FIG. 2 (c) has a configuration in which an external DC voltage is input to one of the two terminals of the FWR in the subsequent stage and this is used as a threshold. In this case, 1 is output when the LPF output exceeds this threshold. In practice, the external clock may come to the data transition area only when the output of the FWR that performs the amplitude comparison is sufficiently large, and it is sufficient to change the clock only in that case. This is effective in avoiding unnecessary clock changes.

Further, it is necessary to carry out this clock selection with a preamble pattern of data, and to fix the clock selection when data having information of the rear part comes in. Therefore, as shown in FIG. 1, data indicating the position of the preamble pattern such as PRE in FIG. 3 is input from the outside, DFF after ACMP is controlled by PRE, and SEL thereafter is fixed. Data is bypassed from the front of PCMP and the second DF
It is selected by F and output.

FIG. 7 is a block diagram showing the configuration of the second embodiment of the bit synchronization circuit of the present invention. As the constituent elements, a toggle flip-flop circuit (TFF) and two phase comparison circuits are provided.
(PCMP), amplitude comparison circuit (ACMP), three delay flip-flop circuits (DFF) and selector circuit (SEL). This configuration is a configuration in which the clock selection of SEL in the first embodiment is replaced with data selection.

In this embodiment, CLK and inverted CLK
The input data are identified by DFF using, and the identification data with the optimum phase relationship with the input data is selected by SEL.
This DFF is usually a master-slave type similar to the TFF in Fig. 5, but the DFF that inputs the inversion of the clock CLK.
If is configured with master-slave (3 stages) instead of master-slave (2 stages), it is possible to output the identification data synchronized with the clock CLK. Furthermore, no matter which data is selected by SEL, the data phase is It never changes.

FIG. 8 is a block diagram showing the configuration of the third embodiment of the bit synchronization circuit of the present invention.
Phase comparator circuit (PCMP), voltage comparator circuit (VCMP), delay flip-flop circuit (DFF) and two selector circuits (SE
L) is included. In this configuration, the TFF of the reference clock signal CLK in the first embodiment is removed, and the clock input to the two PCMPs is either positive or inversion of the reference clock CLK.

In this embodiment, the signal input to the circuit has a structure like DATA2 in FIG. Clock data having the same frequency as the external reference clock signal CLK is included as a preamble pattern before the data (payload) after Da0 carrying the information.

Consider the case where a DFF identifies a data signal using the falling edge of the clock. In order to identify the data near the center of the data, the preamble pattern and the positive or inversion of CLK are compared in phase and the clock closer to the same phase is selected. PCMP is 0 (L when the two input phases are in phase).
ow) is output, and 1 (High) is output when the phase is reversed. Therefore, the smaller output of PCMP is selected by VCMP. In a digital circuit, since both phases input and output are operated in many circuit formats, for example, the positive phase input of the amplifier as shown in FIG.
Input the positive phase data of PCMP1 and input PCMP to the negative phase input of the amplifier.
It can be operated as a VCMP by inputting the positive phase data of 2.

FIG. 10 is a block diagram showing the configuration of the fourth embodiment of the bit synchronization circuit of the present invention. As components, like the third embodiment, two phase comparison circuits (PCMP) and voltage comparison circuits are provided. Circuit (VCMP), delay flip-flop circuit (DFF) and 2
Includes individual selector circuits (SEL). This configuration is different from the third embodiment in that a clock CLK DATA synchronized with DATA is input in addition to the input data signal DATA. The operation is similar to that of the third embodiment. Also, with this configuration, the clock signal CL that is always synchronized with the data signal DATA
Since K DATA is input, the hold circuit that uses the preamble pattern PRE (SEL that uses PRE as the control signal in FIG. 10) may be omitted.

[0031]

As described above, according to the bit synchronizing circuit of the present invention, phase detection is performed by comparing the phases of sine waves with each other using a clock signal that is phase-locked with data and a reference clock signal. In principle, there is no dead phase, and since multi-phase clocks and multi-phase data are not used, high-speed bit rate bit synchronization is possible, and delay lines or R
Since a C phase shifter or the like is not used, it is possible to operate without depending on the frequency up to the limit of device operation. Also, since it is an open loop configuration, instantaneous bit synchronization operation is possible, etc.
Has a remarkable effect.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a circuit of the present invention.

FIG. 2 is a block diagram showing a detailed configuration example of a phase comparison circuit and an amplitude comparison circuit.

3 is a diagram showing a signal waveform applied to the bit synchronization circuit of FIG.

4 is a diagram showing operation waveforms of the bit synchronization circuit of FIG.

FIG. 5 is a circuit diagram showing a configuration example of a toggle flip-flop circuit.

FIG. 6 is a circuit diagram showing a configuration example of a full-wave rectifier circuit.

FIG. 7 is a block diagram showing the configuration of a second embodiment of the circuit of the present invention.

FIG. 8 is a block diagram showing a configuration of a third exemplary embodiment of the circuit of the present invention.

FIG. 9 is a circuit diagram showing a configuration example of a voltage comparison circuit.

FIG. 10 is a block diagram showing a configuration of a fourth exemplary embodiment of the circuit of the present invention.

FIG. 11 is a block diagram showing a configuration example of a conventional bit synchronization circuit and a phase detection unit.

FIG. 12 is a diagram showing operation waveforms of a conventional bit synchronization circuit.

[Explanation of symbols]

ACMP amplitude comparison circuit AMP amplifier circuit AND AND DFF delay flip-flop circuit DLY delay circuit EXOR Exclusive OR FWR full wave rectifier circuit LPF low pass filter PCKP phase comparison circuit PDET phase detector SEL selection circuit TFF toggle flip-flop circuit VCMP voltage comparison circuit

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04L 7/02 H03L 7/087

Claims (4)

(57) [Claims] 1. A bit synchronization circuit which receives as input a data signal including a first clock signal and a second clock signal having a frequency of ½ of the first clock signal as a preamble pattern, the bit synchronization circuit being synchronized with the first clock signal. 1/2 of the first clock signal
Means for outputting a third clock signal and a fourth clock signal having a frequency of π / 2 and having phases different from each other by π / 2, first phase comparing means for comparing the phases of the second clock signal and the third clock signal, and Second phase comparing means for comparing the phases of the clock signal and the fourth clock signal, the amplitude of the output voltage of the first phase comparing means and the amplitude of the output voltage of the second phase comparing means are compared to select the data signal. Amplitude comparison means for selecting a suitable clock signal, hold means for holding the output of the amplitude comparison means except for the time when the second clock signal exists, and the first clock signal or the phase of the first clock signal using the output of the hold means as a control signal. Bit synchronization characterized by comprising selection means for selecting and outputting any one of the inverted signals and means for outputting a data signal in synchronization with the output of the selection means. circuit. 2. A bit synchronization circuit which receives as input a data signal including a first clock signal and a second clock signal having a frequency of ½ of the first clock signal as a preamble pattern, wherein the bit synchronization circuit is synchronized with the first clock signal. 1/2 of the first clock signal
Means for outputting a third clock signal and a fourth clock signal having a frequency of π / 2 and having phases different from each other by π / 2, first phase comparing means for comparing the phases of the second clock signal and the third clock signal, and Second phase comparing means for comparing the phases of the clock signal and the fourth clock signal, the amplitude of the output voltage of the first phase comparing means and the amplitude of the output voltage of the second phase comparing means are compared to select the data signal. Amplitude comparison means for selecting a suitable clock signal, hold means for holding the output of the amplitude comparison means except for the time when the second clock signal exists, first synchronizing circuit for outputting the data signal in synchronization with the first clock signal, data A second synchronizing circuit for outputting a signal in synchronization with a signal obtained by inverting the phase of the first clock signal, and an output of the first synchronizing circuit or a second synchronizing circuit using the output of the holding means as a control signal. Bit synchronizing circuit characterized by comprising a selection means for selecting and outputting one of the outputs of the road. 3. A bit synchronization circuit which receives as input a data signal including a second clock signal having the same frequency as the first clock signal as a preamble pattern of the first clock signal and the information data, the first clock signal First phase comparison means for comparing the phase with the second clock signal, second phase comparison means for comparing the phase of the phase inversion signal of the first clock signal with the second clock signal, voltage of the output of the first phase comparison means And a voltage of the output of the second phase comparison means to select a clock signal suitable for selecting the data signal, and a holding means for holding the output of the voltage comparison means except the time when the second clock signal exists. Selecting means for selecting and outputting either the first clock signal or a phase inversion signal of the first clock signal with the output of the holding means as a control signal And bit synchronization circuit, characterized by comprising means for outputting the data signal in synchronization with the output of the selection means. 4. A first clock signal, a data signal, and
A bit synchronization circuit which receives as input a second clock signal which is synchronized with a data signal and has the same frequency as the first clock signal, and which is a first phase comparison means for comparing the phases of the first clock signal and the second clock signal. , A second phase comparison means for comparing the phase of the phase inversion signal of the first clock signal and the phase of the second clock signal, comparing the voltage of the output of the first phase comparison means with the voltage of the output of the second phase comparison means Voltage comparing means for selecting a clock signal suitable for selecting a data signal; selecting means for selecting and outputting either the first clock signal or a phase inversion signal of the first clock signal with the output of the voltage comparing means as a control signal; A bit synchronization circuit comprising means for outputting a data signal in synchronization with the output of the selecting means.