JP3364775B2 - Clock phase error detection circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock phase error detection circuit, and more particularly to a PLL (Phase Locked).
Loop) relates to a clock phase error detection circuit used for phase error detection.

[0002]

2. Description of the Related Art Conventionally, as a clock phase error detecting circuit of this type, there is one disclosed in Japanese Patent Publication No. 4-79501. This conventional clock phase error detection circuit will be described with reference to FIG. In this figure, A
In the / D converters 11a and 11b, the demodulated signals A and B of the I and Q channels are respectively k bits (k is a positive integer) by the clock signal (2fs) C which is twice the modulation speed (fs).
Is quantized into a digital signal. The MSB of the k-bit quantized signal D of the I channel and the signal E which is the MSB of the quantized signal of the k-bit k-bit of the Q channel are speeds at the frequency fs in the D-type flip-flops (hereinafter, D / FF) 12a and 12b, respectively. Sampling is delayed by. In this case, the clock signal (fs) F obtained by dividing the clock signal C of 2fs (synchronized with the reference clock of frequency fs) by 2 by the frequency divider 13 is input to the clock inputs (CK) of the D / FFs 12a and 12b. Is being applied. D / FF 12a,
The output signals G and H of 12b are D / FF 12c and 1 respectively.
The outputs K and J of the D · FFs 12c and 12d, which are sampling-delayed at a frequency fs in 2d, are input to the exclusive OR circuits (hereinafter, EX · OR) 14a and 14b, and the outputs G of the D · FFs 12a and 12b are By taking the exclusive OR of H and each, the zero crossing of the I channel and the Q channel is detected.

The Ex.OR's 14a and 14b output "1" as signals L and M, respectively, when a zero crossing is detected and "0" when a zero crossing is not detected. AND circuit 15 outputs signal L
AND the signal M to detect that the polarities of the I-channel and Q-channel demodulated signals are inverted at the same time,
It is a circuit which outputs "1" as an output signal N when polarity inversion (zero crossing) of both channels is detected and when not detected. The k bits of the k-bit quantized signal D of the I channel are sample-delayed at the speed at which fs is inverted in the D · FF 12e.

Here, a clock (inversion of fs) R obtained by inverting the clock signal F of speed fs by the inverter 16 is applied to the clock input (CK) of the D / FF 12e. The output signal S of the D / FF 12e is sampling-delayed by the D / FF 12f at a clock fs. D
The output signal U of the FF 12f is a sample value at the zero crossing point of the k-bit quantized signal D of the I channel, but the polarity of the signal U does not correctly correspond to the delay or advance of the clock timing.

Therefore, in order to make the advance of the clock timing positive and the negative delay of the phase error detection value,
The polarity inverting circuit 17 inverts the polarity of the output signal U of the D / FF 12f when the output signal J of the D / FF 12c is "1" and does not invert the polarity when the signal J is "0". The output circuit W of the polarity inverting circuit 17 becomes the clock phase error signal W whose polarity corresponds correctly to the delay or advance of the clock timing.

The polarity of the zero-crossing detection value U and the delay or advance of the clock timing depending on the polarity inversion direction of the k-bit quantized signal D will be described with reference to FIG. Figure 4
(A) shows that the zero crossing detection timing T1 is delayed from the timing T0 when there is no clock phase error. The detection value A1 is detected when the polarity is inverted from negative to positive, and the detection value B1 is detected when the polarity is inverted from positive to negative. Depending on the polarity reversal direction, the polarity of the detected value is 2
You can see that there is a street. If the detection value when the clock timing is delayed is negative (-), it is necessary to invert the polarity of the detection value A1.

Similarly, FIG. 4 (b) shows that the zero crossing detection timing T2 is ahead of T0. The detected value C1 is the detected value D1 when the polarity is reversed from negative to positive.
Is what is detected when reversing from positive to negative. When the polarity of the detected value when the clock timing is advanced is positive (+), the polarity of the detected value D1 needs to be inverted.

Returning to FIG. 3, the selection circuit 18 includes the logic circuit 15
Signal is "1" (at the time of zero crossing of I and Q channels), the signal W is selected, and the output of the AND circuit 15 is "0" (I, Q
This circuit selects and outputs the signal X ("0") when zero crossing is not detected. The output signal Y of the selection circuit 18 becomes the clock phase error signal. When the clock timing is correct, the average value of the output signal Y converges on "0". According to this clock phase error detection circuit, a zero-crossing detection circuit is provided for each of the two series of demodulated signals, and the logical product of the zero-crossing detection circuits is used to obtain only the zero crossings of the two series of demodulated signals at the same time. The clock phase error can be detected with.

[0009]

The above-mentioned conventional clock phase error detection circuit detects the error signal when the demodulated signals of the I channel and the Q channel cross zero at the same time. However, the I channel is detected as the error signal. Since only n is used, there is a drawback that correct phase error detection cannot be performed when n of n-phase modulation is 8 or more.
The reason for this will be described with reference to FIG.

FIG. 5 shows a signal phase space diagram and a demodulated signal waveform of the I channel. A conventional phase error detection circuit uses the deviation from the zero crossing point of this demodulated signal waveform as a phase error signal. There is. 8A is a signal phase space diagram of 4-phase phase modulation, FIG. 9B is an I channel demodulated signal waveform of 4-phase modulation, and FIG.
A signal space diagram of phase-phase modulation, and FIG. 6D is a diagram showing an I-channel demodulation signal waveform of 8-phase phase modulation.

First, in FIG. 1A, a solid line shows a signal transition when the polarities of the I channel and the Q channel simultaneously change. At this time, in the demodulated signal waveform of FIG. 7B, the error signal becomes completely 0 at 1/2 of the demodulated signal point (1 / fs), so that the error signal becomes 0 when the clock timing is correct, and the clock timing Go ahead,
Since the error signal is obtained according to the delay, the correct phase error can be detected by the 4-phase phase modulation.

Next, in FIG. 1C, the transition when the polarities of the I channel and the Q channel change at the same time is shown by a solid line. At this time, the demodulated signal waveform of FIG. 7D is 1/2 between the demodulated signal points, and the error signal is not completely zero. Therefore, in this case, although the clock timing is correct, an error voltage of ± v is generated, so that the correct phase error cannot be detected.

The present invention has been made in order to solve the above-mentioned drawbacks of the prior art, and its object is to detect a clock phase error which can correctly detect a clock phase error even in nPSK when n = 8 or more. It is to provide a circuit.

[0014]

According to the clock phase error detection circuit of the present invention, the polarity change of each of two series of demodulated digital signal sequences obtained by quadrature demodulating an n-phase (n is an integer of 2 or more) phase modulated signal. Corresponding to the first and second polarity control means for outputting either the inverted signal or the non-inverted signal of the demodulated digital signal, the addition means for adding the outputs of these polarity control means, and the two series. First and second zero-crossing detecting means for respectively detecting zero-crossings of the demodulated signal sequence,
The first and second zero-crossing detecting means include an output means for outputting the addition output of the adding means as a phase error detection value when the zero-crossing detection means detect the zero-crossings at the same time.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION The operation of the present invention is as follows.

Depending on the polarity change of each of the two series of demodulated digital signal sequences obtained by quadrature demodulation of the n-phase modulated signal, either one of the inverted signal and the non-inverted signal of the demodulated digital signal is output, respectively. Add outputs together. Two
Zero crossings are detected for each of the series demodulated signal sequences, and when the zero crossings are detected at the same time, the addition result is output as a phase error detection value. At the same time, when the zero crossing is not detected, a value indicating that the phase error is zero is output.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an embodiment of a clock phase error detection circuit according to the present invention, and the same portions as those in FIG. 3 are designated by the same reference numerals.

In the figure, a clock phase error detection circuit according to an embodiment of the present invention receives as input two series of demodulated signal sequences obtained by quadrature demodulation of an n-phase modulated signal, and has a modulation speed fs of the modulated signal. A / D converters 11a and 11b for sampling the demodulation sequence with the reciprocal Ts (= 1 / 2fs) of the multiple and converting the analog signal into a digital signal.
And the D / FFs 12a to 12 that detect the zero crossings of digital data from the odd-numbered sample data using the output signals of these A / D converters as input signals and output a logic "1".
d and two zero-crossing detection circuits consisting of Ex · OR 14a and 14b, and the logical product of the outputs of these two zero-crossing detection circuits, and a logical product for detecting the simultaneous occurrence of zero-crossings between two series of data Circuit 15 and A / D converter 11
Add the outputs of the polarity inverting circuits 17a and 17b to the polarity inverting circuits 17a and 17b that invert / non-invert the polarity of the even sample data of the output signals of a and 11b according to the polarity of the sample value immediately before the even sample. The adder 19 and the output signal of the adder 19 are input, and when the output of the AND circuit 15 is "1", the output signal of the adder 19 is selected and "0" is selected.
In this case, the selection circuit 18 selects an output signal indicating that the error is zero.

In such a configuration, the A / D converter 11a
And 11b, the demodulated signals A and B of the I and Q channels respectively have a doubled clock signal (2f
s) C is quantized into a k-bit (k is a positive integer) digital signal. MSB of k channel quantized signal D and Q channel k bit quantized signal E
The MSBs of the above are subjected to sampling delay at a speed of fs in the D.FFs 12a and 12b, respectively.

In this case, the clock signal C (f
The clock signal (fs) F, which is obtained by dividing the frequency of the reference clock s) by 2 by the frequency divider 13, is the D / FF 12a,
It is applied to the clock input (CK) of 12b. D
The output signals G and H of the FFs 12a and 12b are D and F, respectively.
Sampling is delayed at a speed of fs in F12c and 12d. The outputs K and J of the D / FFs 12c and 12d are input to the Ex / ORs 14a and 14b, respectively.
By taking the exclusive OR of the outputs G and H of 12a and 12b, the zero crossings of the I channel and the Q channel are detected.

The Ex · ORs 14a and 14b output "1" as signals L and M, respectively, when a zero crossing is detected and "0" when a zero crossing is not detected. The logical product circuit 15 calculates the logical product of the signals L and M to obtain the I channel,
It is detected that the polarities of the Q channel demodulation signals are inverted at the same time. The AND circuit 15 outputs "1" as the output signal N when the polarity inversion (zero crossing) of both channels is detected at the same time, and "0" when not detected.

The I-channel k-bit quantized signal D and the Q-channel k-bit quantized signal E are DFF1
Sampling is delayed at a rate at which fs is inverted at 2e and 12g.

A clock R (inversion of fs) R obtained by inverting the clock signal F of speed fs by the inverter 16 is applied to the clock inputs (CK) of the D.FFs 12e and 12g. Output signals S and T of the D / FF 12e and 12g
Is delayed by the clock of fs in the D / FFs 12f and 12h. Output signal U of D / FF 12f
Is the sample value at the zero crossing point of the I-channel quantized signal D, and the output signal V of the DFF 12h is the sample value at the zero crossing point of the Q-channel quantized signal E. The polarity of the signal V does not correctly correspond to the delay or advance of the clock timing.

Therefore, in order to correlate the advance of the clock timing with the positive phase error detection value and the negative delay,
The output signals U and V of the D / FFs 12f and 12h are supplied to the D / FFs 12c and 12d in the polarity inversion circuits 17a and 17b.
When the output signals J and K of "1" are "1", the polarity is inverted and the signal J
Do not reverse the polarity when is "0". As a result, the polarities of the output signals W and Z of the polarity inversion circuits 17a and 17b correspond correctly to the delay and advance of the clock timing.
This is as described in the above-mentioned prior art.

Thereafter, the output signals W and Z are added by the adder 19 to obtain a correct clock phase error signal.
This will be described in detail with reference to FIG. The same figure (a)
Shows the signal transition when the I channel changes from positive to negative and the Q channel changes from positive to negative (first quadrant to third quadrant) at the same time. The demodulated waveforms for the I channel and the Q channel are as shown in FIGS. Here, the four signal transitions α, β, γ, and δ on FIG. 5A are shown in FIGS.
The above αn, βn, γn, and δn (n is a natural number) are associated with each other.

Next, when the I channel and the Q channel are respectively added, the waveform 20 (α1 + α2, β1 + β2, γ1 + γ) converged into one as shown in FIG.
2, .delta.1 + .delta.2) and becomes a phase error signal of a clock which becomes 0 at the correct clock timing T0. Although the case where the first quadrant changes to the third quadrant on the signal space diagram has been described above, similar results are obtained for other quadrants.

Returning to FIG. 1, the output i of the adder 19 is input to the selection circuit 18. The selection circuit 18 outputs the signal W when the output of the logic circuit 15 is "1" (when the I and Q channels are zero crossing).
And a signal X (0) is selected and output when the output of the AND circuit 15 is "0" (when I, Q zero crossing is not detected). The output signal Y of the selection circuit 18 is a clock phase error signal. When the clock timing is correct, the average value of the output signal Y converges to zero.

As described above, according to the clock phase error detection circuit of the present invention, by adding the error signals of two series of I and Q, n = 8, that is, the correct clock phase even in the case of 8-phase phase modulation. The error can be detected.

The present invention can further have the following aspects in connection with the description of the claims.

(1) Two series of demodulated signal sequences obtained by quadrature demodulating an n-phase phase modulated signal (n is a positive integer of 2 or more) are input, and the reciprocal Ts of a multiple of the modulation speed fs of the modulated signal is input.
First and second A / D converters for sampling the demodulated sequences at (= 1 / 2fs) and converting analog signals into digital signals, and the first and second A / D converters.
First and second zero-crossing detection circuits that detect a zero-crossing of digital data from odd-numbered sample data using the output signal of the converter as an input signal and output a logic "1", and these first and second zero-crossing detection circuits. A logical product circuit that takes the logical product of the outputs of the zero-crossing detection circuit and detects that a zero-crossing occurs simultaneously between two series of data, and an even sample of the output signals of the first and second A / D converters. First and second polarity inversion circuits that invert the polarity of data according to the polarity of the sample value immediately preceding the even sample, an adder that adds the outputs of the first and second polarity inversion circuits, and the adder And a selection circuit for selecting the output signal of the adder when the output of the AND circuit is "1" and the output signal indicating that the error is zero when the output of the AND circuit is "1". Clock phase error detection characterized by including Circuit.

[0032]

As described above, according to the present invention, the added value of the error signals of two series is output as the value of the clock phase error, so that the clock phase error can be accurately calculated even when the value of n is 8 or more. The effect is that it can be detected.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a clock phase error detection circuit according to an embodiment of the present invention.

FIG. 2A is a spatial diagram of a demodulated signal, and FIG.
FIG. 4 is a diagram showing a demodulated signal waveform of I channel, FIG. 7C is a waveform of demodulated signal of Q channel, and FIG.

FIG. 3 is a block diagram showing a configuration of a conventional clock phase error detection circuit.

FIG. 4 is a diagram for explaining leading / lagging of clock timing and polarity of a clock phase error detection value at zero crossing.

5A is a signal phase space diagram in the case of 4-phase phase modulation, FIG. 5B is a demodulated signal waveform of the I channel in the case of FIG. 5A, and FIG. 5C is a signal phase in the case of 8-phase phase modulation. A space diagram and (d) are diagrams showing demodulated signal waveforms of the I channel in the case of (c), respectively.

[Explanation of symbols]

11a, 11b A / D converter 12a-12h D / FF 13 frequency divider 14a, 14b EX-OR 15 AND circuit 17a, 17b polarity reversing circuit 18 selection circuit 19 adder

Claims (2)

(57) [Claims] 1. An inverted signal and a non-inverted signal of the demodulated digital signal according to a polarity change of each of two series of demodulated digital signal sequences obtained by orthogonal demodulating an n-phase (n is an integer of 2 or more) phase modulated signal. First and second polarity control means for respectively outputting one of the above, an adding means for adding the outputs of these polarity control means, and first and second polarity detecting zero crossings of the demodulated signal sequence of two series, respectively. 2 zero-crossing detecting means and output means for outputting the addition output of the adding means as a phase error detection value when the first and second zero-crossing detecting means simultaneously detect the zero-crossing. Clock phase error detection circuit. 2. The output means outputs a value indicating that the phase error is zero when the first and second zero-crossing detection means do not detect zero-crossings at the same time. 1. A clock phase error detection circuit described in 1.