JPH05276206A - Frequency detecting and demodulating device - Google Patents

Abstract

PURPOSE:To perform excellent clock regeneration without directly being affected by a noise by calculating the difference between two phase data corresponding to a one-symbol time and utilizing the timing where the difference value crosses 0 deg.. CONSTITUTION:An input PSK modulated wave signal is supplied to a frequency discriminator 20 and a phase data converter 60 respectively. The discriminator 20 converts the frequency variation component of the signal into a voltage and an integrating discharger 30 integrates the voltage value of one symbol and discharges it at the timing determined by the signal from a clock regenerator 80. The integrated voltage value right before the discharging is inputted to a deciding circuit 50 to demodulate '1' and '0' data. The converter 60 extracts and sends phase components of the signal to a zero-crossing detector 70, which operates the difference between the two phase data corresponding to the one-symbol time determined by the timing from the regenerator 80 and supplies it as a phase difference signal to the regenerator 80. The regenerator 80 performs the clock regeneration in synchronism with the timing where the phase difference signal indicates 0 deg..

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency detection demodulator for frequency detecting a PSK modulated wave signal.

[0002]

2. Description of the Related Art FIG. 10 shows an example of the configuration of a conventional frequency detection demodulation device for performing frequency detection demodulation of a PSK modulated wave.

In this conventional example, a limiter 10 for limiting the amplitude of a modulated wave taken in from an input terminal 110, a frequency discriminator 20 for converting a frequency change component of the modulated wave into a voltage, and a voltage output of the frequency discriminator 20 are represented by one symbol. Integral discharger 3 that integrates over time and discharges at the timing from clock regenerator 40
0, a clock regenerator 40 that supplies the discharge timing of the integral discharger 30 from the output of the frequency discriminator 20, and a determination circuit 50 that determines 1, 0 or data from the integration result of the integral discharger 30. There is.

Next, in order to clarify the conventional problems,
The operation of the clock regenerator 40 will be described with reference to FIG.

FIG. 11 shows an example of an output waveform when the π / 4QPSK modulated wave is input to the frequency discriminator 20. The vertical axis represents voltage and the horizontal axis represents time. Further, x indicates the discharge timing of the integrating discharger 30. That is, the clock regenerator 40 is a circuit that creates the timing indicated by x from the waveform as shown in FIG. As a method therefor, there are a method of detecting the timing at which the output voltage of the frequency discriminator 20 crosses the median value of the voltage, a method of detecting the peak of the voltage, and outputting the intermediate time between two consecutive peaks.

A method for detecting the timing at which the output voltage of the frequency discriminator 20 crosses the median voltage is to use a comparator, one input of which is supplied with the median voltage as a reference and the other input. Is supplied with the output of the frequency discriminator 20.

The method of detecting the peak of the voltage is to differentiate the output of the frequency discriminator 20 with respect to time and use the peak at the time when the polarity changes.

[0008]

However, in the conventional frequency detection demodulator, since the clock signal is reproduced by the frequency discriminator output signal as described above, when there is noise, the output voltage has a median value. There is a problem that a correct operation is not performed due to a shift in the crossing timing or a shift in the peak position.

Therefore, in view of the above-mentioned drawbacks, the present invention is to provide a frequency detection demodulation device capable of excellent clock reproduction regardless of the presence or absence of noise.

[0010]

According to the present invention, a frequency discriminator for converting a PSK modulated wave signal having a predetermined frequency into a frequency voltage signal, and the frequency voltage signal are integrated for a predetermined period to integrate the integrated signal. Based on the discharge timing signal,
An integrating discharger for discharging, and a judging circuit for judging a symbol from the integrated signal to generate demodulated data.
In a frequency detection demodulator for frequency detection demodulating an SK modulated wave signal, a phase data converter for converting the PSK modulated wave signal into phase data by a predetermined reference signal,
A phase difference between the phase data and the adjacent symbol is calculated to detect a phase difference zero cross and a phase difference zero cross detector based on the output signal of the phase difference zero cross detector to perform clock regeneration and to perform the integration. A frequency detection demodulator having a clock regenerator for supplying the integrated discharge timing signal to the discharger is obtained.

That is, according to the present invention, in order to eliminate these drawbacks, the limiter output is converted into phase data by a phase data converter, the difference between two phase data corresponding to one symbol time is taken, and the value is 0 degree. It is characterized in that the timing of crossing is detected and the clock is reproduced based on the timing.

[0012]

The frequency detection demodulator of the present invention uses the timing at which the limiter output is converted into phase data, the difference between two phase data corresponding to one symbol time is taken, and the value crosses 0 degree. , It is rarely directly affected by noise, and good clock reproduction is possible.

[0013]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 shows the configuration of a frequency detection demodulator according to an embodiment of the present invention.

With respect to this embodiment, first, the overall configuration and operation outline will be described. P input from the input terminal 110
The SK modulated wave signal is amplitude-limited by the limiter 10 and then branched into two, one is supplied to the frequency discriminator 20, and the other is supplied to the phase data converter 60.

The frequency discriminator 20 converts the frequency change component of the PSK modulated wave signal into a voltage and supplies it to the integrating discharger. The integral discharger 30 integrates the voltage value for one symbol and discharges at a timing determined by the signal from the clock regenerator 80. At this time, the integrated voltage value immediately before discharging is taken into the determination circuit 50, and according to the voltage value, 1,
The 0 data is demodulated and output from the demodulated data output terminal 120.

Also, from the limiter 10 to the phase data converter 6
The PSK modulated wave signal supplied to 0 has its phase component extracted here, and is supplied to the zero-cross detector 70 as phase data. The zero-cross detector 70 calculates the difference between two phase data corresponding to one symbol time determined by the timing from the clock regenerator 80, and supplies it to the clock regenerator 80 as a phase difference signal d.

The data indicating the phase 0 degree of the phase difference signal d indicates the intermediate time from the discharge of the integral discharger 30 to the next discharge. The clock regenerator 80 performs clock regeneration in accordance with the timing at which the phase difference signal d indicates 0 degree, supplies necessary timing to the integral discharger 30, the zero-cross detector 70, and the like, and regenerates the clock output terminal 130. Output from.

Next, the operation of the phase data converter 60 will be described in more detail. FIG. 2 shows one configuration example of the phase data converter 60. The phase data converter 60 shown in this example includes a local master oscillator 62, a frequency divider 63, a shift register 64, a flip-flop (FF) group 65, and an encoder 66.

The local master oscillator 62 has an input terminal 6
It oscillates at m times the carrier frequency f ₀ of the PSK modulated wave input from 1 (m is a natural number) and supplies it to the clock of the frequency divider 63 and the shift register 64. In this example, m = 8. The frequency divider 63 _divides the signal of the frequency m × f ₀ into 1 / m in this example, and outputs the frequency f ₀ as the shift register 6
Supply to 4. The shift register 64 shifts the f ₀ signal by the m + f ₀ signal, thereby changing the phase difference to 8
One of the reference signals θ _1, θ _2, ..., as theta _8, respectively F
Supply to the data input of F65-1, 65-2, ..., 65-8.

A modulated wave signal is input to the clock inputs of the FFs 65-1, 65-2, ..., 65-8 through the input terminal 61.

FFs 65-1, 65-2, ..., 65-8
Will supply the phase difference between the phase of the modulated wave signal and the reference phases θ _{1 to} θ ₈ to the encoder 66 with eight HL values. The encoder 66 generates phase data quantized into 3 bits from the 8 signals and outputs the phase data.

Next, this operation will be described. FIG. 3 shows the operation of the configuration example 1 of the phase data converter as a timing chart. As shown in this figure, the reference signals θ _{1 to} θ ₈ have different phases by 45 °. For example, the reference signal θ ₁ is 22.5 °, the reference signal θ ₂
67.5 ° ... The reference signal θ ₈ has a phase of 337.5 °. Here, consider a case where the modulated wave signal θ _n-1 is input at time (n-1). At this time, FF65
-1, 65-2, ..., 65-8 are reference signals θ, respectively.
_By inputting ₁ , θ ₂ , ..., θ ₈ at the rising edge of the modulated wave signal, an H value or an L value is output.

When the modulated wave signal θ _n-1 has a phase of 170 °, for example, the phases of the reference signals θ _{1 to} θ ₄ are 17
Since it is smaller than 0 °, the outputs of the FFs 65-1 to 65-4 have the H value. However, since the phase of the reference signal θ ₅ supplied to the FF 65-5 is 202.5 °, the FF 65
The output of -5 becomes the L value. Similarly, FF65-6 to 65-
The output of 8 also becomes the L value. Therefore, in the ascending order of the FF 65, the signals supplied to the encoder 66 are HHHHLLLL.
It becomes L.

In the encoder 66, the FF 65-
Based on the signals supplied from 1, 65-2, ..., 65-8, the range of the phase to which the modulated wave signal θ _n-1 belongs is determined. In this case, the signals supplied from the FFs 65-1 to 65-4 are H values, and the signals supplied from the FFs 65-5 to 65-8 are L values.
Since it is a value, the phase of the modulated wave signal θ _n-1 is 157.
A value representative of the range of 5 ° to 202.5 °, for example 18
0 ° is output as phase data.

Similarly, at time n, the modulated wave signal θ _n
Is supplied, if the modulated wave signal θ _n has a phase of 265 °, HHLLLLLHH is output in the ascending order of the FFs 65-1 to 65-8. The encoder 66
The determination is made in the same manner as for the modulated wave θ _n−1 , 247.5 ° to 2
275 °, which is a value representative of 92.5 °, is output as phase data.

A configuration example 2 of the phase data converter 60 is shown in FIG. In this example, the local master oscillator 1
04, a frequency divider 105, a set / reset flip-flop (hereinafter, SRFF) 102, a counter 103, and a latch 107.

The operation of this configuration example will be described with reference to the operation explanatory diagram of the configuration example 2 of the phase data converter shown in FIG. The local master oscillator 104 oscillates at m times (m is a natural number) the carrier frequency f ₀ of the modulated wave input from the input terminal 100, and supplies it to the clock of the frequency divider 105 and the counter 103. The frequency divider 105 divides the signal of frequency m × f ₀ into 1 / m to generate a signal A1 of frequency f ₀ , and SRFF1
02, and a negative pulse A2 having the same frequency as A1 is generated and supplied to the reset input of the counter 103. The pulse A2 is the inverter 1
It is supplied to the clock of the latch 107 via 06.

The modulated wave is transmitted from the input terminal 100 to the SRFF 10
It is supplied to the set input of 2 and SRFF
The output B of 102 is set to the H value. As mentioned above, SRFF1
A signal A1 is supplied to the reset input of 02, and S
The RFF 102 sets the output B to the L value at the rising edge of the signal A1. That is, the positive pulse width of the output B of the SRFF 102 is from the rising edge of the modulated wave to the rising edge of the signal A1. The output B of this SRFF 102 is the counter 1
03 counter enable.

The counter 103 performs the counter operation in the section m × f ₀ signal in which the output B of the SRFF 102 is the H value,
The counter value C is supplied to the latch 107. This counter value C is latched at the falling clock of the pulse A2 by the latch 10
It is latched at 7 and reset to 0 at the same time.

Therefore, the counter 103 counts the rising edge of the counter enable input, that is, the rising edge of the modulated wave to the rising edge of the reset input, that is, the rising edge of A1 with the clock of frequency m × f ₀ , and the count value is latched by the latch 107. It will be latched and reset to 0. As a result, the output of the latch 107 is output as a phase difference between the modulated wave and the signal A1, that is, phase data.

FIG. 6 shows an output example of the phase data converter 60. In this example, the case of a π / 4QPSK modulated wave is shown on the phase plane, and in order to make it easy to see, the amplitude component is also expressed without using a limiter, and the phase resolution is sufficiently large.

Next, the operation of the zero-cross detector 70 will be described in more detail. FIG. 7 shows a configuration example of the zero-cross detector 70. In this example, the zero-cross detector is composed of a latch 73 group and a subtractor 74. Next, this operation will be described. The phase data input from the input terminal 71 is branched into two, one is supplied to the latch 73-1 and the other is supplied to the negative input of the subtractor 74. Further, the signal input from the input terminal 72 is, in this example, the discharge timing of the integrating discharger 30 and the timing indicating an intermediate time from discharge to discharge,
This is supplied to the clocks of the latches 73-1 and 73-2. The latches 73-1 and 73-2 function as shift registers and latch phase data according to a clock. The output of latch 73-2 feeds the positive input of subtractor 74. Therefore, the phase data supplied to the two inputs of the subtractor 74 have a discharge interval, that is, a time difference corresponding to one symbol. The subtractor 74 calculates the difference between the two phase data at mod 360 ° and outputs it. When the difference of the phase data crosses 0 degree on the phase plane, it is called zero cross. It is easy to expand to a configuration in which more accurate zero-cross information is output by increasing the number of stages of the latch 73 and increasing the clock accordingly without changing the time difference between the two phase data input to the subtractor 74. Is.

FIG. 8 shows an example of the output signal of the zero-cross detector 70. In this example, the case of a π / 4QPSK modulated wave is shown on the phase plane, and in order to make it easy to see, the amplitude component is also expressed without using a limiter, and the phase resolution is sufficiently large.

It can be seen that there are a large number of routes that are zero-crossing.

Next, the operation of the clock regenerator 80 will be described in more detail. FIG. 9 shows a configuration example of the clock regenerator 80. In this example, the clock regenerator is a lag / lead detector 82, a loop filter 83, a variable frequency dividing circuit 84,
It consists of a clock recovery master oscillator 85 and is a very general first-order Digital Phaselock Loo.
p.

The output of the zero-cross detector 70 described above is
The signal is supplied from the input terminal 81 to one input of the delay lead detector 82. The delay / advance detector 82 inputs the reproduction clock of the variable frequency dividing circuit 84 from the other input, and supplies the loop filter 83 with a signal indicating whether the output of the variable frequency dividing circuit 84 is delayed or advanced with respect to the zero cross. To do. The loop filter 83 integrates this delay / advance information and supplies it to the variable frequency dividing circuit 84. The variable frequency dividing circuit 84 controls the delay advance of the clock phase to be reproduced by changing the division ratio of the master clock from the clock reproduction master oscillator 85 based on the delay advance information from the loop filter 83, and the delay advance The recovered clock is supplied to the detector 82. The variable frequency divider circuit 84 also supplies the timing required by the integral discharger 30, the zero-cross detector 70, etc., and outputs a clock corresponding to the determined bit rate.

As a result of the above operation, the reproduction clock output phase of the variable frequency dividing circuit 84 coincides with the zero cross timing of the zero cross detector 70. In other words, since the discharge time of the integral discharger 30 coincides with the intermediate time of the next discharge, the clock having the intermediate timing becomes the discharge timing of the integral discharger 30.

The configuration example of the clock regenerator 80 is a first-order Digital Phaselock Loop, but it goes without saying that the same applies to a second-order Phaselock Loop. Further, the delay / advance detector 82 may be replaced with a phase comparator, the loop filter 83 with a low-pass filter or an integrating element, and the variable frequency dividing circuit 84 and the clock recovery master oscillator 85 may be replaced with a voltage control oscillator.

Finally, although the explanation here has been made with π / 4 QPSK modulation, this clock recovery circuit can be applied as long as it is a modulation system capable of frequency detection demodulation.

[0041]

As described above, according to the present invention, the limiter output is converted into phase data by the phase data converter, and 1
The difference between two data corresponding to the symbol time is calculated, the timing at which the value crosses 0 degree is detected, and the clock is reproduced based on that timing, so that good clock reproduction can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment.

FIG. 2 is a configuration example 1 of a phase data converter in this embodiment.

FIG. 3 is an operation explanatory diagram of a configuration example 1 of a phase data converter.

FIG. 4 is a configuration example 2 of the phase data converter in this embodiment.

FIG. 5 is an operation explanatory diagram of a configuration example 2 of the phase data converter.

FIG. 6 is an example of an output signal of a phase data converter.

FIG. 7 shows a configuration example of a zero-cross detector in this embodiment.

FIG. 8 is an example of an output signal of a zero-cross detector.

FIG. 9 is a configuration example of a clock regenerator in this embodiment.

FIG. 10 shows a conventional configuration example.

FIG. 11 is a frequency discriminator output waveform.

[Explanation of symbols]

 10 Limiter 20 Frequency Discriminator 30 Integral Discharger 50 Judgment Circuit 60 Phase Data Converter 70 Zero Cross Detector 80 Clock Regenerator 110 PSK Modulated Wave Signal Input Terminal 120 Demodulated Data Output Terminal 130 Regenerated Clock Output Terminal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Rie Torii 5-1-1, Shimorenjaku, Mitaka City, Tokyo

Claims (1)

[Claims] 1. A frequency discriminator for converting a PSK modulated wave signal of a predetermined frequency into a frequency voltage signal, and an integration for integrating the frequency voltage signal for a predetermined period and discharging the integrated signal based on an integrated discharge timing signal. A frequency detection demodulator having a discharger and a determination circuit that determines a symbol from the integrated signal to generate demodulation data, and performs frequency detection demodulation of the PSK modulated wave signal. A phase data converter for converting into phase data according to a reference signal, a phase difference zero cross detector for calculating a phase difference between adjacent symbols of the phase data and detecting a phase difference zero cross, and the phase difference zero cross detection And a clock regenerator for performing clock regeneration based on an output signal of the regenerator and supplying the integral discharge timing signal to the integral discharger. A frequency detection demodulation device characterized in that