JPH01212038A - Peak value calculation type phase holding system - Google Patents

Abstract

PURPOSE:To facilitate large scale integration with simple constitution without using a tank circuit by applying the control in the same direction as the phase control of a preceding reproducing clock when the amplitude approaches a desired pulse peak and applying the control in the opposite direction to the phase control of the preceding reproducing clock when the amplitude is parted from the desired pulse peak. CONSTITUTION:A specific pattern of an output signal of a line equalizer is detected by an arithmetic control section 3, an output waveform amplitude of the line equalizer 1 is calculated at the detection of a pattern for a prescribed period, the result of calculation is compared with the output waveform amplitude calculated for a preceding prescribed period, the control of the same direction of phase control of the preceding reproducing clock is applied when the compared amplitude approaches the desired pulse peak value, and the control of the opposite direction of phase control of the preceding recovery clock is applied when the compared amplitude is parted from the desired pulse peak value, then no tank circuit is used and the timing reproducing is realized by simple circuit constitution, then large scale circuit integration is facilitated.

Description

[Detailed Description of the Invention] [Summary] Regarding a timing regeneration method in a digital transmission device, the purpose of this invention is to easily integrate it into an LSI with a simple configuration without using a tank circuit. Mouth 1g 1tal Phas
An arithmetic control unit is provided between the e-Locked Loop), detects a specific pattern of the received signal waveform, calculates the output waveform amplitude value of the line equalizer when the pattern is detected for a fixed period, and uses the result of the calculation as the previous When the compared amplitude value is close to the desired pulse peak value, control is performed in the same direction as the phase control of the previous regenerated clock, and the amplitude value is adjusted to the desired pulse value. If it deviates from the peak value, the configuration is such that control is performed in the opposite direction to the previous phase control of the reproduced clock.

[Industrial application field]

The present invention utilizes ISDN (Integrated 5erv
The present invention relates to a timing recovery method in a digital subscriber transmission device (ice Digital Network), and more specifically, to an improvement of a method for extracting timing that provides a criterion for identifying a received signal from the received signal itself.

In the conventional method, the received signal deteriorated due to the characteristics of the transmission line is waveform-shaped by a line equalizer, sliced at a certain threshold value, and input into a tank circuit to obtain the frequency components of the received signal and then processed into a PLL (Phase). -Locked Loop)
A common configuration is to obtain a recovered clock using a circuit.

However, in order to configure current transmission equipment including timing regeneration circuits, LSI integration is an essential condition, but the tank circuit is an L-C tank (L: inductance, C: capacitance).
Or, because it is composed of a mechanical filter, etc., L
It was difficult to implement SI.

Therefore, there is a demand for the development of a timing regeneration system with a circuit configuration suitable for LSI instead of the tank circuit.

[Conventional technology]

FIG. 6 is a block diagram of a conventional timing regeneration system, where ■ is a line equalizer, 6 is a slicer, 7 is a tank circuit,
8 is a PLL.

In the figure, since the received signal is degraded due to the characteristics of the transmission line, it is waveform-shaped by a line equalizer 1, sliced at a certain threshold by a slicer 6, and input to a tank circuit 7. The tank circuit 7 is L-C as mentioned above.
It consists of a tank, a mechanical filter, etc., and is configured to obtain the frequency component of the received signal here, and further to obtain a reproduced clock in the PLL circuit 8.

[Problem to be solved by the invention]

However, the conventional timing regeneration method uses an LC circuit or a tank circuit using a mechanical filter, as described above, and therefore has a problem in that it is difficult to implement it into an LSI.

SUMMARY OF THE INVENTION In view of these problems, it is an object of the present invention to provide a timing recovery method with a circuit configuration suitable for LSI implementation.

[Means to solve the problem]

FIG. 1 is a principle diagram of the peak value calculation type phase holding system of the present invention. In the figure, an A/D converter 2 converts the output of a line equalizer 1 into a digital signal, and a DPLL 4 outputs a recovered clock. It has a configuration in which an arithmetic control section 3 is provided between the two.

[Effect]

In the peak value calculation type phase holding method of the present invention, the calculation control unit 3 detects a specific pattern of the line equalizer output signal,
The output waveform amplitude value of the line equalizer 1 is calculated when the pattern is detected for a certain period, and the calculation result is compared with the output waveform amplitude value calculated in the previous certain period, and the compared amplitude value is determined to be the desired pulse peak. If the amplitude value is close to the desired pulse peak value, control is performed in the same direction as the phase control of the previous regenerated clock, and if the amplitude value is far from the desired pulse peak value, control is performed in the opposite direction to the phase control of the previous regenerated clock. Let's do it.

That is, the present invention obtains control information for timing regeneration directly from the output waveform of the line equalizer 1 without using a conventional tank circuit, controls the LL4 based on that information, and generates the regenerated clock. That's what I'm looking for.

〔Example〕

FIG. 2 is a block diagram of a peak value calculation type phase holding system according to an embodiment of the present invention, and the same components as those shown in FIG. 1 are indicated by the same symbols.

In the figure, the arithmetic control unit 3 selects a specific pattern in the received sequence, for example, . . . 0. A pattern detector 31 that detects ±a, 0... (a is a symbol value), an arithmetic circuit 32 that calculates the output waveform amplitude value of the line equalizer 1 at the time of detecting the pattern for -a constant period, and a constant period It is comprised of a comparison circuit 33 that compares the results of each calculation in time series, and a cycle counter 34 that determines a constant cycle. Furthermore, 5 is DPLL 4
This is the primary oscillator that controls the

Further, FIGS. 4 and 5 show waveform diagrams for explaining control of the DPLL 4.

The waveforms in FIG. 4 explain the principle of control of the DPLL 4, and the peak value of the received signal at the output of the line equalizer 1 is correctly set to the desired peak level Hk. A fixed calculation cycle and phase control timing are set, and during that period, the average value Ci of the peak values Hk within the cycle is calculated.

If the phase control direction for the calculation result Ci is Pi (whether to advance or delay the phase of the reproduced clock), a phase shift will occur from the correct sample phase in (a) as shown in the waveform of Figure 5, and this result The peak value decreases like the incorrect sample phase in (b). Therefore, by setting the phase control direction of the regenerated clock of DPLL 4 to Pn+l = -Pn (reverse control direction) when Cn < Cn and Pn+l = Pn (same control direction) when Cn > Cn, the phase of the regenerated clock can be adjusted correctly on the line. The output waveform of the equalizer 1 can be maintained at the peak value phase. By detecting the pulses used for calculation with the pattern detector 31, it becomes possible to perform phase control correctly. The waveform in Figure 4 is pattern 0. ±1.0
I'm using the one from

In the block diagram of FIG. 2, a received signal degraded by the characteristics of the transmission line is waveform-shaped by a line equalizer 1.

The output waveform of this line equalizer 1 is A/
A/D conversion is performed by the D converter 2, and its output signal is input to a pattern detector 31, where a received data pattern for calculating a peak value is detected. In the arithmetic circuit 32,
An average value Ci of peak values for a certain period is calculated. This calculation result is compared with the calculation result stored in the comparison circuit 33 one cycle before by the comparison circuit 33, and the direction of phase control of the recovered clock by the DPLL 4 is determined. Furthermore, the comparison circuit 33 generates a phase control timing signal for the DPLL 4 and outputs it to the DPLL 4 together with the phase control direction signal. The above calculation cycle is determined by counting the number of reproduced clocks with the cycle counter 34 based on the reproduced clock output from the leaf LL4.

Furthermore, FIG. 3 is a block diagram of a peak value calculation type phase holding system according to another embodiment of the present invention, in which an A/D converter 2 is arranged before the line equalizer 1, and line equalization is performed by digital processing. A configuration using the device 1 is also possible.

Furthermore, in the embodiment of the present invention shown in FIG. 2, a configuration is shown in which the average value of the peak values of the output of the line equalizer 1 is calculated, but the peak level (constant value) and the output peak of the line equalizer 1 A similar timing recovery function can be obtained by calculating the average error value of the values.

〔Effect of the invention〕

As explained above, according to the present invention, timing regeneration can be realized with a simple circuit configuration without using a tank circuit unlike the conventional timing regeneration method, and therefore it is possible to obtain effects such as ease of implementation into LSI. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a peak value calculation type phase holding method according to an embodiment of the present invention. FIG. 3 is a block diagram of a peak value calculation type phase holding method according to an embodiment of the present invention. FIG. 4 and FIG. 5 are waveform diagrams for explaining the control of the DPLL, and FIG. 6 is a block diagram of the conventional timing regeneration method. In the figure, 1 is a line equalizer, 2 is an A/D converter, 3 is an arithmetic control section, and 4 is a leaf LL.

Claims (1)

[Claims] The received signal is waveform-shaped through a line equalizer (1), and the A/
The D converter (2) converts it into a digital signal, and the DPLL (
In the timing recovery method of a digital transmission device that obtains a recovered clock in 4), an arithmetic control section (3) is provided between the A/D converter (2) and the DPLL (4), and a specific pattern of the received signal waveform is provided. , calculates the output waveform amplitude value of the line equalizer (1) when detecting the pattern for a certain period, compares the calculation result with the output waveform amplitude value calculated for the previous certain period, and calculates the compared amplitude. If the value is close to the desired pulse peak value, control is performed in the same direction as the phase control of the previous regenerated clock, and if the amplitude value is far from the desired pulse peak value, the control is performed in the opposite direction to the phase control of the previous regenerated clock. A peak value calculation type phase holding method characterized by being configured to control.