JPS59186453A - Selector for qpsk reference phase - Google Patents

Abstract

PURPOSE:To select a reference phase automatically and regenerate correct data by discriminating on whether synchronism detection is carried out in normal reference phase by a detecting circuit for a frame synchronizing signal or error detecting circuit for data by parity, and controlling the phase switching of the output of a 1/4 frequency dividing circuit or switching of data on the basis of the discriminated result. CONSTITUTION:A QPSK modulating signal S is applied from an input terminal 1 to multipliers 2 and 3 and a 4-multiplying circuit 10. The 4-multiplying circuit 10 obtains a four-fold carrier frequency signal P, which is supplied to a 1/4 frequency dividing circuit 11, whose outputs (a), (b), (c), and (d) are applied to a switching circuit 12; and (a,b), (b,c), (c,d), and (d,a) are selected as signals outputted to outputs (e) and (f) according to four states (0,0), (0,1), (1,0), and (1,1) of switching control signals A and B. Digital signals I and Q regenerated by a signal selected by the switching circuit 12 are normal data, and when a normal frame synchronizing signal pattern is regenerated, and output of a frame synchronizing signal detecting circuit 14 is applied to a control circuit 15. Consequently, a control circuit 15 detects frame synchronizing signals more than a half as many as a normal value within a specific time, and the control signals A and B are fixed.

Description

Detailed Description of the Invention (Field of Application) The present invention relates to a QPSK demodulation circuit used for digital signal transmission, and a 61p demodulation circuit for accurately selecting a reference phase.
3. Related to SK Reference Phase Selection Device (Prior Art) As television broadcasting services using broadcasting satellites are realized both domestically and internationally, PCM audio transmission systems using digital subcarriers are being considered. This system is based on the frequency spectrum of televisions from 0 to 4.
In addition to the 5 MHz band, a subcarrier of 4.5 MHz or more is provided, and a digital signal is placed on this subcarrier and modulated.

FIG. 1 shows a demodulation circuit for four-phase PSK (hereinafter referred to as QPSK), which is an example of the above modulation method.

Further, FIG. 2 shows the QpSK modulation waveform input to the demodulation path and its vector diagram.

In FIG. 1, 1 is a QPSK modulated wave input terminal 2, 3 is a multiplier, 5 and 6 are low-pass filters, 7 and 8 are comparators, 9 is a digital signal processing device that processes the pCM signal, and 4 is a reference phase generator that generates the reference phase necessary for QPSK demodulation.

The phase of the carrier wave input to the input terminal 1 in FIG. 1 has four orthogonal phase states, as shown in FIG. 2 (α), G6). Each phase contains 2 bins of information (oro) + (0.1) of the digital signal.
+ (1.0) + (i,1) is given meaning and tail. To demodulate a CIPSK modulated signal, as shown in FIG. 2(A), a 2-pit digital signal which is a demodulated signal is obtained by synchronously detecting the QPSK modulated signal.

Next, the operation of the circuit shown in FIG. 1 will be explained. The input signal input to the input terminal 1 is multiplied by a reference phase signal of ;y in multipliers 2 and 6, and the above-described synchronous detection is performed. The outputs of the multipliers 2 and 6 are applied to low-pass communication filters 5 and 6, respectively, where high frequency components such as carrier components are removed and sent to a comparator 7.

Added to 8. In the converters 7 and 8, it is determined whether the synchronously detected analog signal exceeds a threshold, and the waveform is shaped into digital pulse waveforms of i and o. The digital signal received and demodulated in this way is applied to the digital signal processing device 9.

In order for the conventional QPSK demodulation circuit explained above to operate normally, the reference phase generator 4 must provide accurate reference phase signals x, y.
It is essential that there is a supply of

Conventionally, this reference phase generator 4 has QPSK applied to its input.
After multiplying the modulated signal by 4, a stable 4 times carrier frequency signal is obtained using a PLL or the like, and the reference phase signal is generated by dividing the frequency by 4.

However, in the configuration of the reference phase generator 4, since the carrier wave frequency which is four times the frequency is divided by four, in addition to the original reference phase signals x and y, 90', 180°, 27
0. Signals with different phases can also be obtained. Therefore, when the circuit of FIG. 1 operates and the QpSK modulated wave is applied, the multiplier 2. The reference phase signal applied to B is not necessarily x or y. For this reason, there arises the disadvantage that synchronous detection is performed at a phase different from the reference phase, and as a result, correct data cannot be sent to the digital signal processing device 9.

(Objective) An object of the present invention is to provide a reference phase selection device for QpS that can automatically select the reference phase of a QpSK demodulation circuit.

(Summary) A feature of the present invention is that a digital signal including a frame synchronization signal, data, and the parity of the data is used to perform
Means for generating a frequency four times the carrier wave by inputting a modulated carrier wave, and dividing the four times the frequency of the carrier wave by 4 to obtain four carrier wave frequency signals having a phase difference of 90° from each other. means for synchronously detecting the four-phase pSK modulated carrier wave using two carrier frequency signals among the four carrier frequency signals; means for reproducing 2-bit parallel digital signal data; and switching means. a demodulation circuit including a demodulation circuit, a means for determining whether the digital signal data demodulated by the demodulation circuit detects a frame synchronization signal pattern and is correctly reproduced; Control of the switching means to cause the switching means to perform a switching operation when it is determined that the frame synchronization signal is not being reproduced, and to stop the switching operation of the switching means when it is determined that the frame synchronization signal is being reproduced correctly. Another feature of the present invention is that, in addition to the demodulation circuit, the present invention includes means for detecting an error p in the reproduced data based on parity included in the reproduced digital signal data; When it is determined that the error in the data is greater than the scheduled rate, the switching means is caused to perform a switching operation, and when it is determined that the data error is larger than the scheduled rate, the switching means is caused to perform a switching operation. The present invention includes a control means for the switching means that stops the switching operation.

(Example) Hereinafter, a first example of the present invention will be explained with reference to FIG. 1
0 is a quadrupling circuit which inputs a QpSK modulation signal and obtains a carrier wave frequency signal four times as large. Reference numeral 11 designates a 4-frequency divider circuit, and 12 a switching circuit for selecting and switching two phase signals from the four phase signals output from the 4-frequency divider circuit.

Further, ]3 is a decoder for detecting a frame synchronization signal pattern included in data, and 14 is a frame synchronization signal detection circuit for determining whether frame synchronization signal patterns are detected at regular intervals. 15 counts whether or not the frame synchronization signal detected by the frame synchronization signal detection circuit is detected within a certain period of time, and if the count value is less than half of the normal value, switching control is performed on the switching circuit 12. A control circuit that operates to change a signal. Note that other symbols in FIG. 3 indicate the same ones as in FIG. 1.

Here, in order to simplify the explanation of the circuit operation, the frame synchronization signal pattern is expressed as (L'
5O) r At the output Q of comparator 8, 6 of (1, o, 1)
It is assumed that the bits are inserted at intervals of 100 clocks.

Next, the operation of this embodiment will be explained. A QPSK modulated signal is applied from a modulated signal output terminal 1 to multipliers 2 and 6 and a quadrupling circuit 10. The quadrupling circuit 10 obtains a quadrupled carrier frequency signal P, which is applied to the quadrupling circuit 11. 4
The output of the frequency dividing circuit 11 becomes a carrier frequency signal having a phase difference of 90 degrees C.K, as shown by α, b, c, and cL in FIG.

The outputs of α, h, C, and d are added to the switching circuit 12,
Four states of switching control signals A and B (o, o), (o,
+ ) (1,0), (1,1), outputs t, f
The IC output signal is (a, b) (b, c) (c, c
t ) (g, a).

Now, the phases of a, Jc, and d are as shown in the vector diagram in FIG. 5, and the digital output 1.8 obtained by the comparator 7.8 is obtained when synchronous detection is performed using the normally overwhelming reference phase. Q
Suppose that B and Q are. At this time, the digital output after synchronous detection for each phase selected by the switching circuit 12 is as follows, as is clear from the vector diagram in FIG.

(11 If t = a, f = b, then I = q
, Q = if2] e = b, f =
For c, 1=i Q=q(31e=c, f
If = d, 1 = q, Q-i (41e = cl
, f = a case 1 =, i, Q = q From this reason, when the switching circuit 12 selects as in (1), (2+, (3) above), the frame synchronization signal pattern is I-('+'rO) at 100 clock intervals
'+Q=(1,0,1) pattern does not exist.

Therefore, the output of the frame synchronization signal detection circuit 14 is not output, and the control circuit 15 detects O frame synchronization signals within a certain period of time. Therefore, the control circuit 15 performs an operation of sequentially changing the control signal output AB.

As a result of such a switching operation, when A and B become (1, 1, +), the signals selected by the switching circuit 12 become e-d, f,
,, becomes α. At this time, the reproduced digital signal 1. Q
is regular data, and the frame synchronization signal pattern is 1.
I-(1,1,0), Q-(1,0
, 1) is reproduced.

When the regular frame synchronization signal pattern is reproduced, the output of the frame synchronization signal detection circuit 14 is applied to the control circuit 15. As a result, the control circuit 15 detects more than half the number of frame synchronization signals within a certain period of time compared to the normal value, and the control signals A and B are fixed.

In this embodiment, by the above-described operation, it is possible to automatically reproduce correct data regardless of the phase of the output of the frequency divider circuit 11.

FIG. 6 shows a second embodiment of the invention. In this example, 4
It is designed to switch data rather than the phase signal output from the frequency dividing circuit.

In the figure, 16 and 17 are inverters that completely invert data 1 and 0, and 18 is a four-state control signal A and B (0 and 0).
) r (o, i) , (110) + (1,
1) increases the output, L has (1, Q ), ((-1
, 1) , (Q, I ) (1, tl ). Further, the output of the frequency divider circuit 11 is two carrier wave frequency signals having a phase difference of 190 degrees. Other symbols are the same as those in Figure 1.

In the case of this embodiment, -f output from the frequency divider circuit 11 is not necessarily the regular reference phase. Therefore, the first
There is a possibility that the outputs in cases (1) to (4) described in the explanation of the operation of the embodiment appear in I and Q. Here, the output large and L of the switching circuit 18 are set to (1,
Q), (Q,I), (1,J,1)(1,
The output of l appears. For this reason, I
= q, even if Q = i, the switching control signal A
, if B becomes ("r'), then K = Q = i = i
.

L=I=q9, normal data can be reproduced. In the other cases (21, (3), (41), it is possible to similarly reproduce normal data by the switching circuit 18.

According to this embodiment, the frame synchronization signal detection circuit 14 and the control circuit 15 can perform the same control as in the first embodiment shown in FIG. It is possible to reproduce the correct data.

FIG. 7 and FIG. 8 show the sixth and fourth embodiments of the present invention, respectively. In these embodiments, data error p is detected using parity, and the switching of the switching circuits 12 and 18 in the first and second embodiments is controlled based on the result.

7th. In FIG. 8, 19 is a digital signal processing device 9.
An error detection circuit 20 that receives data input from the input terminal and generates a pulse when a data error occurs, counts the pulses output from the error detection circuit 19 for a certain period of time, and if more than half of the data is in error, 1. This is a counter circuit that becomes 0 if less than half of the circuits are errors. Further, 21 is a control circuit that operates to sequentially change the states of control signal outputs A and B when the output of the counter circuit 20 is 1, and to hold the states of control signal outputs A and H when the output is 0. Note that the other symbols indicate the same things as in FIGS. 3 and 6.

In the circuits shown in FIGS. 7 and 8, the error detection circuit 19 determines whether the reproduced data is correct based on the parity contained in the data. If so, all reproduced data I and Q will be in error. Therefore, as in the case of FIGS. 3 and 6, the error detection circuit 19. Counter circuit 20. The control circuit 21 sequentially changes the p control signals A and B, and when the normal data is reproduced, the control signals A and B are held. This makes it possible to automatically reproduce correct data regardless of the phase of the output of the frequency dividing circuit 11.

(Effects) According to the present invention, a frame synchronization signal detection circuit or a data error detection circuit due to parity determines whether synchronous detection is performed with a regular reference phase, and based on this determination result, the 4-frequency divider outputs Since the phase switching or data switching is controlled, the reference phase is automatically selected and the correct data can be reproduced.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional QpSK demodulation circuit;
Figures (α), (AH), waveform diagrams showing QPSI!-modulation waveforms, and four-phase state diagrams, Figures 3, 6, and 7.
8 are block diagrams showing the 12.5.4 embodiment of the present invention, FIG. 4 is a timing chart of the input/output signals of the 4-frequency divider circuit, and FIG. 5 is the output of the 4-frequency divider circuit. 10 shows a vector diagram of...4 multiplier circuit 11...4 frequency divider circuit 12
.........Switching circuit 13...
・・・・・・・・・・・・Decoder 14・・・・・・・・・
...Frame synchronization signal detection circuit 15...
...Control circuit 18...Switching circuit 19...
......Error detection circuit 20...
・・・・・・・・・Counter circuit 21・・・・・・・
・・・・・・・・・Control circuit 1 Figure 2 (=7) Figure 3 Section 4 Figure 6 Figure 6 Flash 7

Claims (1)

[Claims] +11 Means for generating a frequency four times that of the carrier wave by receiving a carrier wave that has been four-phase PSK modulated by a digital signal including a frame synchronization signal, data, and a high IJ characteristic of the data; The four-phase PSK modulated method is performed by means of dividing a quadruple frequency by four to obtain four carrier frequency signals having a phase difference of 90° from each other, and using two carrier frequency signals among the four carrier frequency signals. A demodulation circuit includes a means for synchronously detecting a carrier wave, a means for reproducing 2-pit parallel digital signal data, and a switching means, and the digital signal data demodulated by the demodulation circuit detects a frame synchronization signal pattern and correctly a means for determining whether or not a frame synchronization signal is being reproduced; when the determination means determines that the frame synchronization signal is not being reproduced correctly, the switching means is configured to perform a switching operation so that the frame synchronization signal is correctly reproduced; A QpSK reference phase selection device comprising: a control means for the switching means that stops the switching operation of the switching means when it is determined that the switching means is being reproduced. (2) A patented QPSK reference phase selection device characterized in that the switching means selects two carrier wave frequency signals from among the four carrier wave frequency signals having a phase difference of 90°. (3) The switching means selects two data from among the reproduced 2-bit parallel digital signal data and data obtained by inverting 1 and 0 of the 2-bit parallel digital signal. A QPSK reference phase selection device according to claim 1. (4) Means for generating a frequency four times that of the carrier wave by inputting a carrier wave that is four-phase PSX-modulated by a digital signal including a frame synchronization signal, data, and the parity of the data; Means for obtaining four carrier wave frequency signals having a phase difference of 90 degrees from each other by dividing the frequency by four, and synchronously detecting the four-phase PSX modulated carrier wave using two carrier wave frequency signals among the four carrier wave frequency signals. a demodulation circuit including a means for reproducing 2-bit parallel digital signal data and a switching means; a means for detecting errors in the reproduced data based on parity contained in the P+ generated digital signal data; means for determining whether errors in the data are at a predetermined rate or higher; and when the determining unit determines that the data errors are at a predetermined rate or higher, causing the switching unit to perform a switching operation;
A QPSK reference phase selection device characterized by comprising a control means for the switching means that stops the switching operation of the switching means when it is determined that the data error is smaller than the predetermined ratio. (5) A patented QPSK reference phase selection device characterized in that the switching means selects two carrier wave frequency signals from among the four carrier wave frequency signals having a phase difference of 90°. (6) The switching means selects two data from among the 2-bit parallel digital signal data and the data obtained by inverting 1 and 0 of the 2-bit parallel digital signal. A QpSK reference phase selection device according to claim 4, characterized in that: