JPS63316523A - By-phase signal demodulating circuit - Google Patents

Abstract

PURPOSE:To minimize an error rate by limiting the input period to the higher harmonic removing means of a multiplication output to 1/2 tome slot period of the latter half, and removing a waveform distortion due to the impedance mismatching of an input by-phase signal with a simple circuit constitution. CONSTITUTION:An input bi-pass signal S(t) inputted from an input terminal 31 is inputted through a limiter amplifier 32 to a delaying circuit 33 and an exclusive 'or' circuit 34, multiplied with a bi-phase signal S(t-tau) delayed only by a time tau of one time slot and outputs an output signal (f). An AND circuit 40 receives the signal (f) and a clock (g) reproduced by a clock reproducing circuit 37 and inputs a signal (h) limited only to the latter half time slot period of the signal (f) to an analog integrator 35. The integrator 35 resets by the fall of a signal (g) or a resetting signal from a limit signal generating circuit 39, and an identifying circuit 36 compares and identifies an output (i) with a threshold value. An identification result (j) is inputted to a differential decoding circuit 38 and demodulating data (k) are outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a demodulation circuit in a dinotal data transmission system using biphase signals.

[Conventional technology]

For in-home data transmission, time-division multiplex communication is used between the main transmission device and multiple terminal devices using the same bus to reduce the number of lines used, connect multiple terminal devices at the same time, and facilitate the movement of terminal devices. A bus-type transmission system that performs this is becoming widely used.

FIG. 1 conceptually explains an in-home transmission system using a bus type.

In the figure, 1 is the main transmission device, 2-1.・・・・・・
......, 2-n is 0 terminal devices, 3 is the bus line,
4-1. ........., 4-n indicates n branch lines, 5 indicates a terminal circuit, and an information outlet (not shown) is arranged in parallel to the bus line 3 extending from the main transmission device 1. This shows that the branch Is4 to which a plurality of terminal devices are connected is connected in a socket format.

As a transmission code in a bus-type transmission system as shown in Figure 1, it has the following advantages: ■No direct current component and small low frequency component, ■Easy timing extraction, ■Simple modulation/demodulation circuit configuration. Biphase signals (also called Manchester signals) are often used.

Figure 2 shows the code conversion rule for biphase signals.
N RZ (N on -Return-to
-Zero) This is a code sequence in which "10" of the signal corresponds to 1 of the original data, and "01" of the signal corresponds to O of the original data.

Of course, reverse the correspondence and replace 1 in the original data with "01"
Alternatively, 0 may correspond to "10". Here, the former case is shown as an example.

Figure tIS3 is a diagram showing an example when the original NRZ data is encoded using the code conversion rule shown in Figure 2, and (a) is the original NRZ data.
(b) shows the biphase signal.

Biphase signals can be detected directly as baseband signals, but in bus-type transmission systems where waveform distortion is relatively large, it is more advantageous to detect biphase signals as modulated signals.

Demodulation methods include a synchronous detection method and a delay detection method, but the delay detection method, which does not require exact lock regeneration, has a simpler demodulation circuit configuration and can be realized at a lower cost.

FIG. 4 is a block diagram showing the basic configuration of a biphase signal demodulation circuit using a conventional delay detection method.

In the figure, an input Bianese signal s (t) applied to an input terminal 21 is applied to a delay circuit 22 and a clock recovery circuit 26, and is further delayed by the delay circuit 22 by the time (τ) of one time slot of the original data. The multiplier circuit 23 multiplies the biphase signal s (-τ).

The output of the multiplication circuit 23 is inputted to the identification circuit 25 after having harmonic components removed by a harmonic removal circuit 24 composed of an integrator or the like.

In the clock regeneration circuit 26, the input Bianese signal s
A reproduced clock is created based on (t) and an identification timing signal is provided to the identification circuit 25.

Note that when an integrator is used as the harmonic removal circuit 24, the identification timing signal is adjusted to be immediately before the data conversion time of the original data. The identification circuit 25 determines whether the output of the harmonic removal circuit 24 is above or below a certain threshold at the identification timing. If the output of the identification circuit 25 is 1, the differential decoding circuit 27 inverts the value of the demodulated data of the previous time slot and uses it as the demodulated data at the identification timing, and if the output of the identification circuit 25 is 0, it inverts the demodulated data of the previous time slot. Differential decoding is performed to maintain and generate demodulated data. In this way, demodulated data can finally be obtained from the output terminal 28.

In the actual circuit configuration, the input Bianese signal is converted to a binary digital signal by a limiter amplifier (not shown).
For example, the delay circuit 22 is a shift register circuit, the multiplication circuit 2 is
By configuring 3 as an exclusive OR circuit and the harmonic removal circuit 24 as a digital integration circuit using a counter, it is possible to implement the system as an all-4-digital circuit.

In the bus type transmission system as shown in Fig. 1, the termination circuit 5
is designed to provide matched termination of the bus line 3.

On the other hand, the input impedance of the receiver (not shown) in the terminal device 2 is designed to be sufficiently large to eliminate the influence on the signal waveform when connected in parallel. Therefore, a branch line with an open end is connected to the bus line, and there is a problem in that impedance matching cannot be achieved at the connection point between the bus line and the branch line, resulting in waveform deterioration due to impedance mismatch.

[Problem that the invention seeks to solve]

In general, the causes of waveform deterioration in bus-type transmission systems include (1) reflections due to impedance mismatch, and (2) losses in bus lines and branch lines. Of these, the loss in ■ is mainly caused by the bus line because the branch line is short, and the loss characteristics are determined when the cable (bus line) is laid. It is possible to compensate by using a converter.

On the other hand, as the terminal device moves, the connection point of the branch line changes, so the influence of reflection changes.

Therefore, in order to compensate for the waveform deterioration due to the reflection of ■,
Automatic isovolume with adaptive control becomes necessary, complex,
Generally, compensation for waveform deterioration due to reflection is not implemented because it is expensive.

The reflected waves caused by the impedance mismatch caused by the connection between the bus line and the branch line are described in the document ``Transactions of the Institute of Electronics, Information and Communication Engineers '87/2 Vo1.J70-B No. 2.
The analysis results were published in p. 195-203J, and the reflected wave at one connection point is almost a differentiated form of the transmitted pulse waveform, and the reflected voltage has the opposite polarity according to the changing voltage of the pulse. It is known that a round trip delay on a branch line occurs at each change point, and that when there are multiple connection points, the reflected waves at each connection point are superimposed.

According to the analysis results, in the worst-case wiring system, the voltage of the reflected wave increases as the number of connected terminal devices (number of branch lines) increases.

FIG. 5 is a diagram showing an example of a biphase signal waveform subjected to waveform distortion due to impedance mismatch, in which (a) represents the transmitted biphase signal, and (c) represents the biphase signal subjected to waveform distortion. ing.

In the figure, the signal waveform when it is not affected by reflection is shown by a broken line.

As described above, waveform distortion occurs when there is a level transition of the Biarney signal. In other words, distortion in time slot (A) is caused by rising edge (A).

The same applies to (a) and (tsu). The reason why there is no distortion in time slot (1) is because the output bi-phase signal has not fallen at the time of (D). The operation of the conventional demodulation circuit using the delay detection method in this case will be explained with reference to FIG. 6, which shows signal waveforms at various parts.

However, the biphase signal demodulation circuit is realized by a digital circuit except that an analog integrator is used as the harmonic removal circuit 24.

In Fig. 6, (a) is the original NRZ of the biphase signal.
As data, a bi-phase signal (b) corresponding to 0 and 1 of this data is transmitted.

(e) is a biphase signal subjected to waveform distortion due to the reflected wave shown in FIG. 5, and is converted into a binary signal sequence shown in (d) by a limiter amplifier (not shown). Here, a case is shown in which polarity is incorrectly identified as waveform distortion in the 1/6 time slot width of the first half and the 1/6 time slot width of the latter half.

A signal obtained by delaying the binarized input bi-phase signal of (d) by one time slot τ by the delay circuit (shift renostar) 2 is shown in (e).

A multiplication circuit 23 configured with an exclusive OR, (d) and (
(f) shows the result of comparing the phases of the signals in e) and multiplying them. When (f) is added to the harmonic removal circuit 24, which is an analog integrator, the output is (g).

However, the analog integrator receives a reset signal (not shown) from the clock recovery circuit 26 immediately after the end of each time slot.
shall be reset by.

(g) is the result of identification by the identification circuit 25 using the identification timing signal (not shown) from the clock regeneration circuit 26 just before the end of each time slot, and (h) is input to the differential decoding circuit 27 to demodulate. Data (i) is output from the output terminal 28.

However, the discrimination margin of the discrimination circuit 25 is reduced due to the influence of waveform distortion due to reflection.

Figure 7 is an overlay of the integral level locus in Figure 6(g), and shows that the discrimination margin β is reduced by about 30% compared to the discrimination margin a without waveform distortion. There is.

Therefore, there is a drawback that the error rate characteristics tend to deteriorate due to other foreign noise and the like. Therefore, it was necessary to limit the number of terminal devices connected and the transmission speed.

In view of these conventional problems, the present invention can be realized at low cost with a simple circuit configuration, and eliminates the influence of waveform distortion caused by impedance mismatch of input Bianese signals. It is an object of the present invention to provide a biphase signal demodulation circuit that can obtain demodulated data with a small error rate.

[Means for solving problems]

According to the invention, the above objects are achieved by the means specified in the claims.

In other words, in a bi-phase signal demodulation circuit using a differential detection method, the influence of waveform distortion due to impedance mismatch does not appear in the latter half time slot period of the multiplication output of the input Bianese signal and its delayed signal. Focusing on this point, the present invention is characterized in that the input period of the multiplication output to the harmonic removal means is limited to the same 1/2 time slot period in which no waveform distortion appears.

That is, since a level transition always occurs in the biphase signal at the center of the time slot τ of the original data as shown in FIG. 2, distortion always occurs as shown in FIG. 5. Since this distortion occurs at the same time within a time slot (in this example, the first and second half of the time slot), the distortion can definitely be removed by performing exclusive OR with a 1-bit delay. . In other words, since distortion occurring in the latter half of the time slot can be removed, only this portion is demodulated.

Specifically, in the biphase signal demodulation circuit of the present invention,
It differs from conventional demodulation circuits in that it has a control means between the multiplication means and the harmonic removal means, which has a function of inputting the multiplication output to the harmonic removal means only during the latter 1/2 time slot period.

〔Example〕

FIG. 8 is a block diagram showing the basic configuration of a bi-phase signal demodulation circuit according to an embodiment of the present invention, and shows the basic configuration when everything other than the harmonic removal circuit is realized by digital circuits.

In the figure, 31 is an input terminal, 32 is a limiter amplifier, 33 is a shift register that operates at high speed and locks and operates as a delay circuit, 34 is an exclusive OR that operates as a multiplier circuit, and 35 is a harmonic removal circuit. 36 is an identification circuit, 37 is a clock recovery circuit, 38 is a differential decoding circuit, 39 is a control signal generation circuit, 4
0 is an AND circuit operating as a control circuit, 41 is a high speed clock generation circuit, and 42 is an output circuit.

FIG. 9 is a diagram showing waveforms of various parts in this embodiment.

Figures 9(,) to (f) show the conventional example (,) shown in Figure 6.
) − Same as (f), (a) is the original NRZ data,
(b) is a biphase signal, (e) is a biphase signal subjected to waveform distortion due to reflection, and (d) is the limiter amplifier 3.
2, (e) shows a signal obtained by delaying the binarized signal by the shift register 33, and (f) shows an output signal of the exclusive OR circuit 34.

121 In this embodiment, the output signal (f
) is input to the AND circuit 40.

The clock (g) reproduced by the clock reproduction circuit 37 is input to the other input terminal of the AND circuit 40 .

Therefore, the output of the AND circuit 40 becomes a signal (h) limited only to the latter half time slot period of the exclusive OR circuit output signal (f), and is input to the analog integrator 34. The analog integrator 35 is reset by a reset signal generated by the control signal generation circuit 38 at or immediately after the fall of the reproduced clock signal (g).

The output (i) of this analog integrator 35 is
, and the control signal generation circuit 38 identifies it as 1 if it is greater than the threshold value, and 0 if it is less than the threshold value, at the timing of the identification timing signal that occurs at the falling edge of the reproduced clock signal (g) or at the time immediately before it. be done. By inputting the identified result (j) to the differential decoding circuit 38, demodulated data (k) is obtained from the output terminal 41.

As is clear from Fig. 9(f), in the delayed detection method of the P7E signal, the polarity error in the limiter amplifier due to waveform distortion due to impedance mismatch is multiplied by a signal delayed by one time slot. Accordingly, the second half
/2 time slot period, they will attack each other.

In the present invention, the analog integrator has the latter half of the multiplication output.
Only the time slot is entered.

Therefore, the analog integrator integrates the signal excluding the influence of waveform distortion, and unlike the conventional demodulation circuit, the discrimination margin does not decrease in the discrimination circuit, and it is stable against foreign noise. Accurate identification becomes possible.

Note that if the waveform distortion is extremely large, distortion and jitter may also occur in the reproduced clock reproduced by the clock reproduction circuit 37.

Even in such a case, since there is only a variation in the integration period of the analog integrator, the characteristics can be expected to be improved, and the 1jtli11! The characteristics will not deteriorate.

The present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the essential aspects thereof.

For example, although the integrator in FIG. 8 is constructed of an analog integration circuit, a digital integration circuit using a counter may also be used.

In this case, the output of the AND circuit is applied to the enable terminal of the counter to control the integration period, and the integration is performed by counting the high-speed clock N times (Nu! number) the clock frequency f0 of the original data series during the same period. is executed.

Furthermore, it is also possible to use a low-pass filter instead of the integrator as the harmonic removal circuit.

In this case, there is no need for a reset signal, and the identification timing signal is approximately 3/4τ from the time of data conversion of the original data.
(However, the delay of the low-pass filter itself is excluded) 1゜ [Effects of the Invention] As explained above, the present invention provides the output of the multiplication of the input biphase signal and its delayed signal. Since only the portion that is not affected by waveform distortion due to reflected waves is extracted and input to the harmonic removal means for data identification, demodulation errors are greatly reduced and stable, high-quality demodulation is possible. .

Therefore, when the present invention is applied to a bus-type transmission system, it is possible to increase the number of connectable terminal devices and increase the transmission speed.

[Brief explanation of the drawing]

Figure 1 is a conceptual diagram showing a bus-type in-home transmission system, tItJ2
Figure 3 shows a code conversion rule for bi-phase signals, Figure 3 shows an example of code conversion using the bi-phase code conversion rule, and Figure 4 shows the basic configuration of a bi-phase signal demodulation circuit using a conventional delay detection method. 5 is a diagram showing an example of a biphase signal waveform subjected to waveform distortion due to impedance mismatch, FIG. 6 is a diagram showing waveforms of various parts in the circuit of FIG. 5, and FIG. 8 shows the basic configuration of a bi-phase signal demodulation circuit using a delay detection method according to an embodiment of the present invention, and FIG. 9 shows the circuit of FIG. 8. It is a figure which shows the waveform of each part in. 1... Main transmission device, 2-1 to 2-n...
...Terminal device, 3 ...Bus line, 4-
1~4-n...branch line, 5...
・Termination circuit, 21 ... Input terminal, 22
...delay circuit, 23 ...multiplication circuit,
24...Harmonic removal circuit, 25 ・
...Identification circuit, 26 ...Clock regeneration circuit, 27 ...Differential decoding circuit,
28... Output terminal, 31...
...Input terminal, 32 ...Limiter amplifier, 33 ...Shift register, 34
...exclusive OR circuit, 35 ...
...analog integrator, 36 ...identification circuit, 37 ...clock regeneration circuit,
38...Differential decoding circuit, 39...
...Control signal generation circuit, 40 ...AND
Circuit, 41...High-speed clock generation circuit, 42...Output circuit agent Patent attorney
Honma Takashi〆-＾ Zu Naki

Claims (1)

[Claims] a delay means for delaying a bi-phase encoded input signal for a certain period of time; a means for multiplying the bi-phase signal output from the delay means by the bi-phase encoded input signal; A biphase signal demodulation circuit comprising means for removing harmonic components and identification means for identifying an output signal of the harmonic removal means at a predetermined timing to obtain demodulated data, the multiplication means and the harmonic removal means 2. A biphase signal demodulation circuit characterized in that a means for inputting the output signal of the multiplication means to the harmonic removal means only during the latter half of each time slot is provided between the two.