JPS6324343B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a synchronization detection method for training signals used for high-speed data transmission using telephone lines. In high-speed data transmission, such as 9600 bit/sec, using telephone lines, in order to pull the signal into various circuits on the receiving side such as AGC circuit, carrier regeneration circuit, timing regeneration circuit, automatic equalizer, etc.
A specific training signal is transmitted prior to starting transmission of data signals. The format of this training signal is shown in the table below (CCITT document)
According to COM.SP.A−No.148). Here, "S" means a segment, and "total" means the entire training signal.

[Table] Pattern
SAD1……Scrambled all data 1
Segment 1 of the training signal does not contain any signal, but the transition point with segment 2 is used to detect the start of data reception. Segment 2 of the training signal consists of repetitions of two signal elements. As shown in FIG. 1, the first signal element A has a relative amplitude of 3 and defines an absolute phase reference of 180 degrees. The second signal element B changes with the data rate, (1-j) at 7200 bit/sec, 9600 bit/sec
When , there are 3 (1-j) vectors. Segment 2 repeats ABAB... for a 128 symbol interval. Segment 3 of the training signal is
It consists of two signal elements that vary according to an equalizer conditioning pattern, also called a PN code. The first signal element C has a relative amplitude of 3 and an absolute phase of 0°, and the second signal element D varies with the data rate, at 7200 bit/sec (-1 + j),
At 9600 bit/sec, there are 3 (-1+j) vectors. The equalizer conditioning pattern is a pseudo-random sequence, and when this sequence is 0, C occurs, and when this sequence is 1, D occurs. Furthermore, the signal of segment 4 is used to pull in the descrambler circuit. This segment 2 signal includes a demodulation carrier. That is, vectors A and B are vectors
It can be considered as the sum of A' and CAR and the sum of vector B' and CAR, and segment 2 is A, B, A, B
When iterating, the invariant component is CAR, and the alternating component is
A' and B', the sum of alternating components A' and B' is zero, and the constant component CAR is the carrier signal. Similarly, when calculating the invariant component and therefore the carrier component for segment 3, vectors C and D
are vector A′ and CAR′ and vector B′ and
Since it is the sum of CAR′, the carrier component is CAR′, which is the carrier component CAR of segment 2.
The phase is shifted by 180°. When pulling in the equalizer (automatic equalizer), the transmitting side sends out the signal of segment 3, and the receiving side also generates the same signal, and for example, compares the two to find the signal necessary for waveform correction. To carry out such an operation, it is necessary to detect the start point of segment 3 and to start generating the above-mentioned signal on the receiving side. Conventionally, in order to detect the transition point between segments 2 and 3, carrier signals CAR and CAR' are smoothed, and a synchronization signal is obtained when the polarity of these signals is reversed. However, these conventional methods have the disadvantage that phase rotation occurs due to the phase characteristics of the line, and furthermore, the conversion point between segments 2 and 3 cannot be accurately detected due to the amount of delay during smoothing. are doing. SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a synchronization detection method that can accurately detect conversion points between signal groups. In order to achieve the above object, in the present invention, segment S ₂ of the training signal has a signal whose polarity changes alternately, and the first symbol of segment 3 and the last symbol of segment 2 are symbols of the same polarity. Focusing on a certain point, multiplying the polarity between each symbol of segment 2 results in negative polarity, and detecting that it becomes positive polarity when it moves to the changing point position, and extracting the changing point as a synchronization signal. This is what I did. Examples will be described in detail below. FIGS. 2 and 3 are a block diagram and a time chart of an embodiment of the present invention. In the figure, PC ₁ and PC ₂ are phase comparators, LF ₁ and LF ₂ are roll-off filters, and VCO is a voltage controlled oscillator.
If the phase of the output of terminal t is 0°, terminal _t2 produces an output with a phase difference of 90°, OP is a polarity detector,
RG is a register that stores the polarity of one symbol, M is a multiplier, A is an AND gate, FF
is a flip-flop. A VCO is a voltage controlled oscillator. The oscillator VCO outputs from both terminals such that if the output of terminal t ₁ is 0°, the output of terminal t ₂ is 90°.
Produces outputs that are 90° out of phase. The terminal t ₁ of the oscillator VCO is connected to one input terminal of a phase comparator PC ₁ , to the other input terminal of which an input signal, in this example a training signal S ₀ , is applied,
The phase comparator PC ₁ produces an output proportional to the cosine of the phase difference between the two signals. This output is passed through a roll-off filter _LF1 (not shown) and then applied to the input terminal of the oscillator VCO by a known method to control its oscillation frequency (phase). In other words, PC ₁ , LF ₁ , VCO
constitutes a known PLL (phase-locked loop) circuit, and the output of terminal _t1 of the oscillator VCO is the input signal.
Synchronized with S ₀ . If the input signal S ₀ is a training signal as described above, the roll-off filter LF ₁
After synchronization, the output of the phase comparator PC ₁ corresponds to the invariant component, that is, the carrier signal CAR or CAR′, and is connected to the terminals of the oscillator VCO controlled by this output.
The output from t ₁ corresponds to the carrier signal CAR shifted by 90°. The second output terminal t ₂ of the voltage controlled oscillator VCO is applied to one input terminal of the second phase comparator PC ₂ ,
The other input terminal of this phase comparator has an input signal S ₀
are added, and its output, which is proportional to the cosine of the phase angle of these input signals, is output through a roll-off filter LF ₂ . Although this output is not shown, it is applied to the comparator CP through a smoothing circuit. In this circuit, demodulation is performed by a PLL circuit consisting of PC ₁ , LF ₁ and VCO, and a signal X as shown in FIG. 3X is output from the roll-off filter LF ₁ . The input training signal S ₀ is segment 2 (S ₂ ) at time ta
to segment 3 (S ₃ ), and the phase of the carrier component changes by 180°, so the phase of the signal X is also reversed at this point. Phase comparator PC ₂ is the input training signal
S ₀ and synchronize with the signal (that is, 90° phase difference)
and produces an output proportional to the cosine of the phase difference with the signal S ₂ which is 90 DEG out of phase (eventually 180 DEG out of phase), so that the output Y from the roll-off filter LF ₂ is as shown in FIG. 3Y. That is, input signal S ₀ is segment 2
(S ₂ ) is a negative wave, and at time ta, segment 3
When the signal enters , the carrier component is reversed and turns into a positive wave. The polarity detector OP detects the polarity of the signal X, and outputs a signal _x1 of level "0" if it is negative, and "1" if it is positive, for example. This output is a register
Stored in RG. Next symbol polarity signal x ₁ to polarity detector OP
outputs a value indicating this polarity and register RG
The polarity value of the previous symbol stored in is input to and multiplied by a multiplier M, that is, a multiplier M having an inverter added to the output of an exclusive OR gate. In the multiplier having the configuration shown in the figure, a signal of level "1" is output from the output of the inverter when the multiplied value has positive polarity. It is initially reset, and its output always outputs level "1". Therefore, when a symbol of the same polarity arrives at the conversion point time ta, a level "1" is output from the multiplier M, which becomes the output x ₃ via the AND gate, that is, the synchronization detection signal. The flip-flop is activated by this synchronization detection signal x ₃ .
FF is set and its Q output is set to level “1”.
Set the Q output to level “0”. Therefore, the AND gate A to which the output of the flip-flop FF is input is closed, and no signal whose polarity becomes positive will be output from the subsequent multiplied value. As explained above, according to the present invention, if the conversion point is detected by the signal _Y in _FIG . Although synchronization cannot be detected for one symbol, in the present invention, since the polarity of the signal X is used for detection, accurate synchronization can be detected.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining a training signal, and FIGS. 2 and 3 are a block diagram and a main part time chart of an embodiment of the present invention. In the drawing, VCO is a voltage controlled oscillator, PC ₁ is a phase comparator, LF ₁ is a roll-off filter, PC ₂ and LF ₁
is a second phase comparator and a roll-off filter,
OP is a polarity detector, RG is a register, M is a multiplier,
A is an AND gate, and FF is a flip-flop.

Claims (1)

[Claims] 1 The polarity of one of the carrier signal components whose phases are orthogonal to each other in the received signal is alternately inverted according to different rules within the signal groups of the received signal, and at least between each signal group. In the synchronization detection method, a training signal in which the carrier signal components at the change point positions of the signals have the same polarity is received, and a synchronization signal is obtained by detecting the change points of each signal group. A synchronization detection method characterized in that a means for multiplying is provided, and a synchronization signal is obtained by detecting that the polarity of the multiplied value is reversed.