JPS60263534A - Correlation detecting circuit for error signal - Google Patents

Abstract

PURPOSE:To improve both the converging performance and the accuracy of error detection control by monitoring the levels of discrimination and error signals and changing the time constant of an integrator based on the information on said monitoring. CONSTITUTION:An input 16-QAM signal 40 is transmitted through orthogonal phase wave detectors 41 and 41'. Thus the base bands of in-phase and orthogonal components are obtained and discriminated by A/D converters 43 and 43' after they passed through higher harmonic suppressor filters 42 and 42'. These in-phase and orthogonal components are supplied to D/A converters 51 and 52 by paths 3 and 4 as well as 3 and 5 through exclusive OR circuits 46, 47, 49 and 50 respectively. The outputs of both converters are added and vary the time constant of an integrator 53. In this respect, the capacity of the integrator 53 is controlled. The error is maximum with the step-out and therefore the capacity of the integrator 53 is reduced to decrease the time constant. This improves the converging performance. When the error degree is small, the capacity of the integrator 53 is increased to increase the time constant. Thus the control accuracy is improved. The correlation is secured between the polarity of the discrimination signal of the in-phase component and that of the error signal of the orthogonal component by means of exclusive ORs 45 and 48.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a carrier regeneration control circuit in a quadrature amplitude modulation method using the Costas method, an automatic waveform equalizer using a transversal filter, and interference compensation between cross side waves. The present invention relates to an error signal correlation detection circuit used in a tap weight control circuit of a device, etc.

(Prior Art) As an example of the prior art, consider a 16 QAM carrier recovery circuit. By passing the four-value coded baseband waveform of in-phase and quadrature components as shown in FIG. 1 through a 3-bit A/D converter, the first bit (most significant bit) represents the polarity of the identification signal, Further, the third bit represents the polarity of the error signal.

As shown in FIG. 2, an exclusive OR circuit 6 (or an exclusive OR circuit 6) that takes the correlation between the polarity of the identification signal of the in-phase component and the polarity of the error signal of the orthogonal component (or The VCO control signal was obtained by passing the output signal of the exclusive inverting OR circuit 7), which correlates with the polarity of the error signal, through a loop filter 8 for integration.

FIG. 3 shows an example of an automatic waveform equalizer and tap weight control circuit using a transversal filter for a 16QAM signal. The polarity 11 of the identification signal of the in-phase (or quadrature component) and the polarity 12 of the error signal of the in-phase (or quadrature) component shown in FIG. The signal is inputted to the integrators A to M through the OR circuits 21 to 27, and the output thereof becomes the tap weight control signal. An example of the integrator is shown in FIG. 4. In the configuration of FIGS. 2 and 3, When holding synchronization and pulling in synchronization, or when holding the 61' period, which uses an integrator with the same time constant regardless of the magnitude of the identification signal or the error signal, increase the time constant when the error signal is small. It was not possible to improve the control accuracy by reducing the time constant and shorten the pull-in time when the error signal was a dog during synchronous pull-in.

(Problems to be solved by the invention) The present invention aims to improve the above problem, and provides an error signal correlation detection circuit that monitors the magnitude of an identification signal and the magnitude of an error signal, and can vary the time constant of an integrator based on the information. DESCRIPTION OF THE PREFERRED EMBODIMENTS (Structure and operation of the invention) As one embodiment of the present invention, a 16 QAM signal will be explained. As shown in Fig. 5, for example, a 5-pin A/D signal is
Identification by converter. As a result, the upper 2 bits (Path
1. Path 2) becomes the identification signal, and the top 3
From pit to 5 bits (Path 3.
4. Path 5 ) represents the error signal. Here P
ath 3 represents the direction of the error, and two bits, Path 4 and Patb5, represent the amount of error. In other words, as shown in FIG.
Take the exclusive OR of b and set it as the th Path 4', and take the exclusive OR of the 3rd Path and the 5th Path and set it as the th Path 5'.
4' and the third ath5', the magnitude of the error can be differentiated into 22=4 levels. Therefore, these 2 pins are used as input signals and converted into analog signals by passing through a 2-bit D/A converter, and this information is used to vary the time constant of the integrator. In other words, as shown in Fig. 7, the variable capacitor constituting the integrator is controlled by the output signal of the D/A converter (the time constant of the integrator can be similarly varied even if the resistance value is controlled by a variable resistance element). ).

As an embodiment of claim 1, a 16 QAM carrier regeneration circuit will be described. FIG. 8 shows the circuit configuration. 1GQAM signal is input, and the quadrature phase detector 41
．． 41' to obtain baseband signals of in-phase components and quadrature components. Harmonic removal filters 42 and 42' respectively
is identified by a 5-bit A/D converter 43'. Path 3 and Pa for in-phase and quadrature components
Circuit that takes exclusive OR of tb4 and Patb3 and Path 5 46.47.49. ! # and input to 2-bit D/A converters 51 and 52, respectively. The outputs are added in an analog manner to control the capacity for varying the time constant of the integrator. Here, the amount of error is the largest in the case of out-of-synchronization. In this case, it is necessary to reduce the time constant of the integrator in order to reduce the synchronization pull-in time.
Reduce the capacitance of the capacitor. On the other hand, the smaller the amount of error,
The time constant of the integrator is increased and the time constant of the integrator is automatically switched according to the amount of error so as to perform more precise control.

The carrier phase error signal can be realized by correlating the polarity of the identification signal of the in-phase component and the polarity of the error signal of the orthogonal component, as in the conventional case.

As an embodiment of claim 2, a tap weight control circuit for an automatic waveform equalizer and cross-side interference compensator using a 16QAM transversal filter will be described. FIG. 9 shows the circuit configuration. The polarity 60 of the identification signal and the polarity 61 of the error signal for the in-phase component are input signals, (the polarity of the identification signal and the polarity of the error signal of the quadrature component, or the polarity of the identification signal of the in-phase component and the polarity of the error signal of the quadrature component, (The same applies to the polarity of the identification signal of the orthogonal component and the polarity of the error signal of the in-phase component) Through delay circuits 64 to 71 that delay by a clock period, and through circuits 72 to 78 that take correlation between each time slot, to an integrator. Enter from 94 to 100. On the other hand, Path4' and Path5' indicating the magnitude of the error signal are input to the m and number terminals. The signals are respectively input to 2-bit input D/A converters 87-93 through circuits 79-86 which are delayed by a clock period, and the time constant of the integrator is controlled by the output signal thereof. In other words, if the error is large,
Improve convergence by reducing the time constant and increasing the control speed. On the other hand, when the error is small, the time constant of the integrator is automatically switched according to the magnitude of the error signal so as to increase the time constant and improve control accuracy.

Regarding the above two sides, if the number of bits to monitor the error size is (J-N) bits, the time constant is 2(J-N) bits.
N) Can be varied in stages.

Furthermore, it can be applied in the same manner as on the second side even when the number of multi-values increases, such as 64 QAM, 256 QAM, etc.

Further, the above example can be similarly applied to the clock recovery circuit.

(Effects of the Invention) As described above, since the error signal correlation detection circuit according to the present invention can vary the time constant of the integrator depending on the amount of error signal, when the amount of error signal is large, the time constant of the integrator can be changed. Synchronous pull-in by reducing the constant.

The range can be expanded and control convergence can be improved. Furthermore, when the amount of error signal is small, control accuracy can be improved by setting the time constant of the integrator to dog. Therefore, it is possible to realize an error signal correlation detection circuit such as a carrier wave regeneration circuit and a tap weight control circuit, which can improve the overall characteristics.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing identification of four-valued codes by the conventional method, Figs. 2 and 3 are conventional error signal detection circuits, Fig. 4 is a conventional integrator, and Fig. 5 is the method of the present invention. FIG. 6 is a detailed explanatory diagram of the present invention, FIG. 7 is an example of the configuration of an integrator applied to the present invention, and FIG. 8 is error signal detection according to the present invention. Circuit FIG. 9 is another error signal detection circuit according to the present invention. 1...x61QAM signal input terminal, 2,2'...Quadrature phase detector, 3.3'-...Low pass filter, 4,
4'... Discriminator, 5.5'... Conversion timing input terminal, 6... Exclusive OR circuit, 7... Exclusive inverting OR circuit, 8... Loop filter (integrator ), 9
...vCOllo...90° phase shifter, 11...Identification signal polarity input terminal, 12...Error signal polarity input terminal, 13-20...Krolev period delay circuit, 21-
27...Exclusive OR circuit, u~M...Integrator,
40-16QAM signal input terminal, 41.41'...Quadrature phase detector, 42.42'...Low pass filter,
43.43'... Discriminator, required, 44'... Conversion timing, 45.46.47, 49.50... Exclusive OR circuit, North... Exclusive inversion OR circuit, 51 .5
2...D/A converter,...integrator, 舅...■C
O1. Group...900 phase shifter, Mark...Identification signal polarity input terminal, 61...Error signal polarity input terminal, 61.62
...Bit input terminal representing the amount of error signal, 64~
71.79~a5... Clock cycle delay circuit, 72~
78... Exclusive OR circuit, η~kuo... D/A converter, 94-100... Integrator. Patent applicant Nippon Telegraph and Telephone Public Corporation Patent application agent Megumi Yamamoto - #3 Figure Zi Figure Qin b Figure 7 of the book

Claims (2)

[Claims] (1) Means for quadrature phase detection of a multilevel quadrature amplitude modulated wave according to the output of a controlled oscillator, and J bit (J is an integer satisfying J≧N+2), and the correlation between the in-phase component or quadrature component identification signal N bits and the quadrature component or in-phase component error signal (J-N) bits. In the error signal correlation detection circuit, the error signal correlation detection circuit has an exclusive OR circuit that provides a control signal from the N-bit identification signal and a control circuit that controls the controlled oscillator according to the control signal. An error signal correlation detection circuit comprising an integrator whose time constant changes depending on at least one of the error signals. (2) Input multiple 2N-value (N is an integer) multi-value signal and
Plural A/D converters that provide digital signals (J is an integer that satisfies J≧N+2), identification signals of N and 2 of their outputs, and delayed identification signals. and an exclusive OR circuit that correlates error signals, and a control circuit that controls tap weights according to the output of the exclusive OR circuit, wherein the control circuit detects an N-bit identification signal and (J-N) bits. An error signal correlation detection circuit comprising an integrator whose time constant changes depending on at least one of the error signals.