JP2850565B2 - Data receiving device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data receiving apparatus for reproducing a data signal from a quadrature modulated wave in which a modulated signal of another system coexists as an interference wave signal.

[0002]

2. Description of the Related Art As is well known, in digital wireless communication,
16QAM (Quadratur) for the purpose of high efficiency transmission
e Amplitude Modulation), 6
Development and commercialization of multi-level quadrature amplitude modulation schemes such as 4QAM and 256QAM have been promoted, but transmission signals based on such multi-level quadrature amplitude modulation schemes are affected by transmission signals based on other coexisting modulation schemes. Therefore, a method of removing the interference is a problem.

[0003] As a conventional interference elimination method, for example, a method described in Japanese Patent Application Laid-Open No. 1-095641 is known.
FIG. 2 shows a specific example, and its operation will be described.
The input signal is a quaternary (ie, when n = 2) baseband signal, which includes an interference wave signal composed of a signal wave based on another modulation method such as an FM wave. This input signal is converted by the AD converter 2 into a binary data signal of 6 bits (6 columns). The output of the AD converter 2 is a delay circuit 16
, And an error data signal f (D _{3 to} D ₆ ) which is a part thereof is supplied to the interference wave extraction circuit 25.
The interference wave extraction circuit 25 includes the DA converter 12, the bandpass filter 24, and the AD converter 14. DA converter 1
2 converts the data signal f (D _{3 to} D ₆ ) into an analog signal and supplies it to the bandpass filter 24. The bandpass filter 24 suppresses various noises included in the output of the DA converter 12 to extract an interference wave signal component, and supplies the signal component to the AD converter 14. The AD converter 14 converts the extracted interference wave signal into a binary signal, and outputs a 3-bit data signal d (D ₁ ′ to
D ₃ ′) is formed and applied to the multiplier 21 and the correlator 23. The delay circuit 16 is composed of, for example, a shift register, and delays the data signals a (D ₁ , D ₂ ) and f (D _{3 to} D ₆ ) in the signal path from the interference wave extraction circuit 25 through the multiplier 21 (bit shift). ) Is performed, and the delayed signal b is supplied to the digital adder 18. The digital adder 18 uses the delayed signal b and the multiplier 2
1 and the signal c output from the main data signal (D ₁ ,
D ₂ ) is sent out as reproduction data, while an error data signal e (D _{3 to} D ₆ ) is given to the correlator 23. Correlator 23
Is the data signal d (D ₁ ′ to D ₃ ′) and the error data signal e
Digital correlation processing is performed on (D _{3 to} D ₆ ) to generate a multi-bit control signal, which is provided to the multiplier 21. The multiplier 21 weights the digital signal d (D ₁ ′ to D ₃ ′) in response to the multi-bit control signal, and supplies the weighted signal to the digital adder 18 as a multiplier output c. That is, the output c of the multiplier is controlled by the control signal so as to be a signal having the same amplitude level and the opposite polarity as the interference wave signal included in the delay signal b. As a result, the digital adder 18 outputs the main data signals (D ₁ , D ₂ ) and the error data signal e (D
_{3 to} D ₆ ).

[0004]

As described above, even in the conventional example shown in FIG. 2, an efficient interference compensator can be realized by digital processing. However, the filtering means of the interference extraction circuit uses a band-pass filter having a fixed center frequency. It is composed of a shape filter, and has a drawback that it cannot flexibly cope with a change in the frequency of the target interference wave. In addition, the filtering means includes a PCO including a voltage controlled oscillator.
Although an LL circuit can be used, even in that case, the voltage-controlled oscillator to be used is in the baseband, the frequency variable range is narrow, and little effect can be expected.

SUMMARY OF THE INVENTION The present invention is to eliminate such a drawback, and to provide a digital receiving apparatus provided with an interference compensating means capable of flexibly coping with a change in the frequency of the target interference wave over a wide frequency range. With the goal.

[0006]

SUMMARY OF THE INVENTION The present invention provides a detecting means for synchronously detecting a quadrature modulated wave in which a modulation signal of another system coexists as an interference wave signal with a reference carrier, and an in-phase of the quadrature modulated wave synchronously detected by the detecting means. conversion means for the component and quadrature component by multi-level decision to generate Lud over data string such from the main signal bits and error bits, digitally subtracts the extracted interference wave signal by weighting the data sequence output from the conversion means In the data receiving apparatus provided with an interference compensating means for reproducing the main data signal, the means for obtaining the extracted interference wave signal comprises: a voltage-controlled oscillator controlled by a control signal; and an output of the voltage-controlled oscillator, the reference carrier wave. A quadrature detector that performs quadrature detection with an analog-to-digital converter that converts the output of the quadrature detector into a digital signal and outputs the extracted interference wave signal. A digital-to-analog converter that converts at least one error bit of the in-phase component and the quadrature component of the quadrature modulated wave into an analog quantity, and compares the phase of the output of the digital-to-analog converter with the output of the quadrature detector. A phase comparator for generating a control signal.

Here, the digital-to-analog converter includes:
A means for converting each of the error bits of the in-phase component and the quadrature component of the quadrature modulated wave synchronously detected by the detection means, obtains the sum of the outputs of the digital-analog converter, and supplies the sum to the phase comparator. An adder may be provided.

[0008]

The operation of obtaining the extracted interference wave signal d for reproducing the main data signal by digitally subtracting the main data signal including the interference wave is as follows. The output of the voltage controlled oscillator 7 is subjected to quadrature detection with the output of the voltage controlled oscillator 5 to output i and q. The control signal of the voltage-controlled oscillator 7 is obtained as an output of a phase comparator for comparing the output of at least one of the outputs I 'and Q', which is obtained by digital-to-analog conversion of the signal f, with at least one of i and q. Can be i and q are A
An analog-to-digital conversion is performed by the D converters 14 and 15 to obtain an extracted interference wave signal d.

[0009]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of an embodiment according to the present invention. In this embodiment, as shown in FIG. 1, quadrature detectors 1 and 1 ', A / D converters 2, 3, 14, and 15, a logic circuit 4, voltage controlled oscillators 5 and 7, an interference wave extraction circuit 6, low-pass filter 8, phase comparator 9, phase shifter 10, analog adder 11, DA converters 12 and 13, delay circuits 16 and 17, digital adders 18 and 19, , Multipliers 20 and 21 and correlator 2
2 and 23. That is, in this embodiment, as shown in FIG. 1, a quadrature detector 1, a logic circuit 4, and a voltage control unit, which are detection means for synchronously detecting a quadrature modulated wave in which a modulation signal of another system coexists as an interference wave signal with a reference carrier, are used. an oscillator 5, AD converter 2 is a conversion means for generating a Lud over data string such from the main signal bits and error bits by multi-level decision-phase and quadrature components of the quadrature modulated wave synchronous detection with this detecting means And 3 and a delay circuit 1 as an interference compensating means for reproducing a main data signal by digitally subtracting the weighted extracted interference wave signal from the data string output by the converting means.
6, 17, digital adders 18, 19, multipliers 20, 2
1, the correlator 22, 23 and the interference wave extraction circuit 6, and the interference wave extraction circuit 6, which is a means for obtaining the extracted interference wave signal, is controlled by a control signal. Voltage-controlled oscillator 7, a quadrature detector 1 'for orthogonally detecting the output of the voltage-controlled oscillator 7 with the reference carrier, and digitally converting the output of the quadrature detector 1' to output the extracted interference wave signal. AD converter 14
And 15 and a DA converter 12 or 1 for converting at least one error bit of the in-phase component and the quadrature component of the quadrature modulated wave synchronously detected by the detection means into an analog quantity.
3, and a phase comparator 9 for comparing the output of the DA converter 12 or 13 with the output of the quadrature detector 1 'to generate the control signal. The digital-to-analog converters are DA converters 12 and 13 which are means for converting error bits of the in-phase component and the quadrature component of the quadrature modulated wave synchronously detected by the detection means, respectively.
An analog adder 11 that obtains the sum of the outputs of the A converters 12 and 13 and supplies the sum to the phase comparator 9 may be provided.

Next, the operation of this embodiment will be described. FM
The 16QAM wave including the interference wave of another modulation method such as a wave is synchronously detected by the quadrature detector 1 by the reference carrier from the voltage controlled oscillator 5, and is converted into I and Q quaternary baseband signals. The I and Q signals are converted into 6-bit (six columns) binary data by AD converters 2 and 3, respectively.
This 6-bit binary data signal is transferred to the most significant bit (MS
Data signal a (D ₁ , D ₂ ) from B) to the second bit
And the data signal f (D ₃
Separating the a to D _6), the data signal a (D _1, D ₂₎ corresponds to the main data signal, the data signal f (D ₃ ~D ₆₎ corresponds to the error data signal. This data signal f (D ₃ to
D ₆ ) indicates how much the quaternary input signal deviates from the level it should originally have, and includes an interference wave signal. Therefore, the outputs of AD converters 2 and 3 are applied to delay circuits 16 and 17, respectively, and data signal f is applied to interference wave extraction circuit 6. D ₁ of the outputs of the AD converters 2 and 3
D ₂ then enters logic circuit 4 where a phase control signal for controlling voltage controlled oscillator 5 is created. The configuration and operation of the logic circuit 4 are described in, for example, Japanese Patent Application Laid-Open No. 57-1311.
51 (57.8.13) "Carrier recovery circuit".

Next, an interference wave extraction circuit 6 which is a feature of the present invention.
Will be described. The f signal of the outputs of the AD converters 2 and 3 is converted into an analog amount by the DA converters 12 and 13, added by the analog adder 11, and input to the phase comparator 9. The other input signal of the phase comparator 9 is obtained by passing the output i and q signals of the quadrature detector 1 'through a phase shifter 10. The output of the phase comparator 9 controls the voltage controlled oscillator 7 after the high frequency jitter component is removed by the low frequency filter 8. The frequency band of the voltage controlled oscillator 7 is the same as the frequency band of the interference wave signal included in the input 16 QAM wave, and the output of the voltage controlled oscillator 7 is output from the quadrature detector 1 ′ to the reference carrier of the voltage controlled oscillator 5. , The orthogonally related i and q signals are
It has the same frequency as the output of the analog adder 11, which is the interference wave extracted from the 6QAM signal. Therefore, the PLL circuit including the voltage controlled oscillator 7, the low-pass filter 8, the phase comparator 9, the phase shifter, and the quadrature detector 1 'outputs a phase signal to the output of the analog adder 11, which is the extracted interference wave signal. It is possible to output i and q signals as extracted interference wave signals in synchronization with the jitter component suppressed. The i and q signals are finally converted into 3-bit data signals d (D ₁ ′ to D ₃ ′) by AD converters 14 and 15, respectively, and output from the interference wave extraction circuit 6. Here, the d signal is 3 bits, but can be selected to a value before or after this in consideration of the characteristics and the circuit scale. Voltage controlled oscillator 7
Can be selected as the intermediate frequency band as described above, so that the variable range of the frequency can be widened.

FIG. 1 shows a configuration in which I 'and Q' are used as inputs to the phase comparator 9, but either one of them can be operated. Further, the phase shifter 10 provided at the other input of the phase comparator 9 can be configured as a resistor addition, and the phase can be changed by changing its value. By changing this phase, the phase of the extracted interference signals i and q can be changed, and this is used to adjust the phase at the input points of the digital adders 18 and 19, but it becomes unnecessary depending on the circuit configuration. . In that case, i or q is directly converted to the phase comparator 9
Enter it in

The i and q d signals (D ₁ ′ to D ₃ ′) of the interference wave extraction circuit 6 are multiplied by multipliers 20 and 21 and a correlator 2.
2 and 23, a circuit including a delay circuit 16, a digital adder 18, a multiplier 21, and a correlator 23 and a delay circuit 17, a digital adder 19, a multiplier 20, and a correlator shown in FIG. The operation of the circuit composed of the delay circuit 16, the digital adder 18, the multiplier 21,
The operation is the same as that of the circuit constituted by the correlator 23.

[0014]

As described above, according to the present invention, the intermediate frequency band can be selected as the operating frequency band of the voltage controlled oscillator and the frequency variable range can be widened. This has the effect of being able to flexibly respond over a wide frequency range.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a conventional example.

[Explanation of symbols]

 1, 1 'quadrature detector (QAMDET) 2, 3, 14, 15 AD converter (AD) 4 Logic circuit (LOGIC) 5, 7 Voltage-controlled oscillator (VCO) 6, 25 Interference wave extraction circuit 8 Low-pass filtering (Fs) 9 Phase comparator (PHDET) 10 Phase shifter (φ) 11 Analog adder (+) 12, 13 DA converter (DA) 16, 17 Delay circuit (SR) 18, 19 Digital adder (+) 20, 21 Multiplier (×) 22, 23 Correlator (×) 24 Bandpass filter (Fb)

Claims (2)

(57) [Claims] 1. A detecting means for synchronously detecting, using a reference carrier, a quadrature modulated wave in which a modulated signal of another system coexists as an interference wave signal, and multi-level identification of an in-phase component and a quadrature component of the quadrature modulated wave synchronously detected by the detecting means. to a conversion means for generating a Lud over data string such from the main signal bits and error bits, the extraction interference wave signal by weighting the data sequence output from the converting means to a digital subtraction for reproducing the main data signal interference In a data receiving apparatus provided with a compensating means, the means for obtaining the extracted interference wave signal includes: a voltage-controlled oscillator controlled by a control signal; and a quadrature detector that performs quadrature detection on the output of the voltage-controlled oscillator with the reference carrier. An analog-to-digital converter that converts the output of the quadrature detector to a digital signal and outputs the extracted interference wave signal, and an in-phase component of the quadrature modulated wave synchronously detected by the detection means. A digital-to-analog converter for converting at least one error bit of the quadrature component into an analog quantity, and a phase comparison for generating the control signal by comparing the phase of the output of the digital-to-analog converter with the output of the quadrature detector A data receiving device, comprising: 2. The digital-to-analog converter is means for converting each of the error bits of the in-phase component and the quadrature component of the quadrature modulated wave synchronously detected by the detection means, and calculates the sum of the outputs of the digital-analog converter. 2. The data receiving apparatus according to claim 1, further comprising an analog adder for obtaining the sum and providing the sum to the phase comparator.