JP2012085142A - Clock regeneration circuit and clock data regeneration circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock regeneration circuit which can generate stabilized regeneration clock signals at a high speed.SOLUTION: The clock regeneration circuit comprises a first sample-and-hold circuit (312) which samples and holds a first clock signal in synchronism with input data, a second sample-and-hold circuit (313) which inputs a second clock signal having the same frequency as that of the first clock signal and a phase different from that of the first clock signal by 90°, and samples and holds a second clock signal in synchronism with the input data, a first mixer circuit (314) which mixes the first clock signal and an output signal from the second sample-and-hold circuit (313), a second mixer circuit (315) which mixes the second clock signal and an output signal from the first sample-and-hold circuit, and a subtractor (316) which outputs a regeneration clock signal by subtracting an output signal of the first mixer circuit from an output signal of the second mixer circuit.

Description

  The present invention relates to a clock recovery circuit and a clock data recovery circuit.

  FIGS. 1A to 1C are diagrams for explaining a clock data recovery (CDR) circuit. FIG. 1A is a block diagram illustrating a configuration example of a clock data recovery circuit. The clock data recovery circuit includes a clock recovery circuit 101 and a data recovery circuit 102. The clock recovery circuit 101 is a gated voltage controlled oscillator (VCO) and generates a recovered clock signal CKo synchronized with input data Di. The data reproduction circuit 102 reproduces the input data Di in synchronization with the reproduction clock signal CKo, and outputs the reproduction data Do.

  FIG. 1B is a circuit diagram illustrating a configuration example of the clock recovery circuit 101, and FIG. 1C is a timing chart for explaining an operation example of the circuit in FIG. The clock recovery circuit 101 is configured by a gated VCO, and includes, for example, four inverters 111 and a negative logical sum (NOR) circuit 112. The series connection circuit of the four inverters 111 has an input terminal connected to the output terminal of the NOR circuit 112. The NOR circuit 112 outputs the output signal of the series connection circuit of the four inverters 111 and the negative logical sum signal of the input data Di as the reproduction clock signal CKo. A loop circuit including four inverters 111 constitutes a ring oscillator and oscillates a clock signal. When the input data Di is at the high level, the NOR circuit 112 outputs the low level reproduction clock signal CKo, and the clock is stopped. When the input data Di falls from the high level to the low level, the NOR circuit 112 starts outputting the reproduction clock signal CKo of the pulse train and enters the clock output state. Thereby, the reproduction clock signal CKo becomes a clock signal synchronized with the falling edge of the input data Di. The reproduction clock signal CKo is a continuous pulse train when inputted to the data reproduction circuit 102. The inverter 111 is a delay element. The delay time of the inverter 111 is controlled by the control voltage Vc, and the oscillation frequency of the ring oscillator is set to be substantially the same as the fundamental frequency of the input data Di.

  A clock data recovery circuit including a clock recovery circuit that inputs input data and generates a recovery clock synchronized with the edge timing, and a data identification circuit that inputs the input data and identifies the data of the input data using the recovery clock Is known (see, for example, Patent Document 1).

JP 2008-227786 A

  1A to 1C, input data Di is selectively input from a plurality of transmission devices. Input data Di input from each transmitter has a frequency and phase shift from each other. In the case of the gated VCO shown in FIG. 1B, signal fluctuation occurs in the loop circuit formed by the gated VCO shown in FIG. 1B simultaneously with the input of the input data Di at the moment when the transmission device is switched. This fluctuation is called a phase jump in the gated VCO, and a signal component different from the waveform that is constantly generated in the ring oscillator is input. This degrades the stability of the ring oscillator. In other words, the ring oscillator returns to the stable state after a certain amount of time from the switching of the transmission device and can generate the recovered clock signal CKo, but it is necessary to wait until the loop circuit converges to the stable state, It takes a long time to generate timing.

  An object of the present invention is to provide a clock recovery circuit and a clock data recovery circuit capable of generating a stable recovered clock signal at high speed.

  The clock recovery circuit includes a first sample-and-hold circuit that samples and holds a first clock signal in synchronization with input data, and a second sample that has the same frequency and a phase that is 90 degrees different from the first clock signal. A second sample and hold circuit that inputs a clock signal, samples and holds the second clock signal in synchronization with the input data, and outputs the first clock signal and the output signal of the second sample and hold circuit. A first mixer circuit for mixing, a second mixer circuit for mixing the second clock signal and the output signal of the first sample and hold circuit, and the first mixer circuit from the output signal of the second mixer circuit. And a subtractor that outputs a recovered clock signal by subtracting the output signal of the mixer circuit.

  Since the reproduction clock signal can be generated without using the loop circuit, a stable reproduction clock signal can be generated at high speed.

1A to 1C are diagrams for explaining a clock data recovery circuit. It is a figure which shows the structural example of the communication system by 1st Embodiment. FIG. 3A is a diagram illustrating a configuration example of a clock data recovery circuit, and FIG. 3B is a timing chart of input data and a recovered clock signal. 4 is a timing chart for explaining the operation of the clock recovery circuit of FIG. 5A to 5C are IQ plane views for explaining the operation of the clock recovery circuit. FIG. 4 is a circuit diagram illustrating a configuration example of a first sample and hold circuit in FIG. FIG. 4 is a circuit diagram illustrating a configuration example of a first mixer circuit, a second mixer circuit, and a subtracter in FIG. It is a figure which shows the structural example of the clock reproduction circuit by 2nd Embodiment. FIGS. 9A and 9B are diagrams showing a configuration example of the data reproducing circuit according to the third embodiment.

(First embodiment)
FIG. 2 is a diagram illustrating a configuration example of a communication system according to the first embodiment. The plurality of subscriber side devices 201 and the station side device 203 are connected by an optical access network (for example, FTTH (Fiber To The Home) network). The station-side apparatus 203 uses a PON (Passive Optical Network) system in which one optical fiber is branched by a splitter 202 and connected to a plurality of subscriber-side apparatuses 201 to perform time division multiplex communication. Since the subscriber-side device 201 exists in a plurality of subscriber houses, the signal received by the station-side device 203 varies depending on the distance from the station-side device 203 to each subscriber-side device 201 and the communication quality. . Since the signal to be transmitted and received is only a data signal, the station side device 203 needs to generate a signal reception timing signal (regenerated clock signal). Since the time division multiplexing method is used, it is necessary to generate a different reception timing signal every time the subscriber side apparatus 201 performing transmission / reception is switched. While the reception timing signal is being generated, data cannot be transmitted / received correctly. Therefore, it is necessary to generate the reception timing signal at a high speed in order to improve communication efficiency. In general, in the PON system, a synchronization pattern is first transmitted from the subscriber side device 201, and the station side device 203 generates a reception timing signal during reception of the synchronization pattern. This is generally called a burst mode CDR.

  The station side device 203 includes a transmission circuit 204 and a reception circuit 205. The reception circuit 205 includes a photodetector 211, a transimpedance amplifier 212, a limiting amplifier 213, and a clock data recovery (CDR) circuit 214. The photodetector 211 converts an optical signal received from the subscriber side device 201 via an optical fiber into a current signal. The transimpedance amplifier 212 amplifies by controlling the gain so that the amplitude of the output signal is constant because the amplitude of the current signal differs depending on the distance to the subscriber side device 201 and the like. Since the amplitude of the output signal of the transimpedance amplifier 212 is small, the limiting amplifier 213 amplifies the output signal of the transimpedance amplifier 212. The clock data reproduction circuit 214 reproduces the clock signal and data based on the output signal of the limiting amplifier 213.

  The performance required for the clock data recovery circuit 214 will be described. The internal clock signals of the subscriber side apparatus 201 and the station side apparatus 203 are set to values determined by the standard. According to the standard, this internal clock signal needs to allow an error within a certain range. It is necessary to allow a frequency offset of approximately 100 ppm between the subscriber side device 201 and the station side device 203. It is also necessary to allow low frequency fluctuations of these internal clock signals. Therefore, the reception circuit 205 of the station side device 203 needs to generate a reception timing signal (reproduced clock signal) corresponding to the frequency fluctuation and phase fluctuation of the input data.

  FIG. 3A is a diagram showing a configuration example of the clock data recovery circuit 214, and FIG. 3B is a timing chart of the input data Di and the recovery clock signal CKo. The clock data recovery circuit 214 includes a clock recovery circuit 301 and a data recovery circuit 302. The clock recovery circuit 301 outputs a recovered clock signal CKo synchronized with the input data Di. The data reproduction circuit 302 reproduces the input data Di in synchronization with the reproduction clock signal CKo, and outputs the reproduction data Do. The signal frequency of the input data Di and the frequency of the recovered clock signal CKo are the same. For example, the signal frequency of the input data Di is 1 G [bps], and the frequency of the recovered clock signal CKo is 1 G [Hz]. One unit interval (1 UI) 320 is a period between changing points of the input data Di, and is a one-bit period. The clock recovery circuit 301 generates a recovered clock signal CKo such that the changing point of the input data Di matches the rising edge of the recovered clock signal CKo, for example. The data recovery circuit 302 performs binary determination of the input data Di in synchronization with, for example, the falling edge of the recovered clock signal CKo, thereby generating stable data near the center of the 1-unit interval 320 of the input data Di. Can be output as

  4 is a timing chart for explaining the operation of the clock recovery circuit 301 in FIG. 3A. FIGS. 5A to 5C are IQ plane views for explaining the operation of the clock recovery circuit 301. FIG. It is. The clock recovery circuit 301 includes a voltage controlled oscillator (VCO) 311, a first sample hold circuit 312, a second sample hold circuit 313, a first mixer circuit 314, a second mixer circuit 315, and a subtractor 316. Note that the voltage controlled oscillator 311 may be provided outside the clock recovery circuit 301.

  As shown in FIG. 5A, the voltage controlled oscillator 311 generates a first clock signal CKq and a second clock signal CKi. The second clock signal CKi is a signal having the same frequency and a phase difference of 90 degrees with respect to the first clock signal CKq. The first clock signal CKq is a cosine wave signal (Q signal) of cos (ωt), and the second clock signal CKi is a sine wave signal (I signal) of sin (ωt).

  The frequency ω of the first clock signal CKq and the second clock signal CKi is substantially the same as the signal frequency ω0 of the input data Di. For example, the frequency ω of the first clock signal CKq and the second clock signal CKi is 1 GHz, and the signal frequency ω0 of the input data Di is 1 G [bps]. However, the first clock signal CKq and the second clock signal CKi have a frequency and phase shift with respect to the input data Di. Based on the first clock signal CKq and the second clock signal CKi, the clock recovery circuit 301 generates a recovered clock signal CKo having the same frequency and phase as the input data Di.

  The first sample hold circuit 312 samples and holds the first clock signal CKq in synchronization with the rising edge and falling edge of the input data Di, and outputs a signal SCKq. The second sample and hold circuit 313 samples and holds the second clock signal CKi in synchronization with the rising edge and falling edge of the input data Di, and outputs a signal SCKi.

  Note that the sample hold circuits 312 and 313 are not limited to the case of synchronizing with both the rising edge and the falling edge of the input data Di, and sampling and holding in synchronization with one of the rising edge or the falling edge of the input data Di. May be performed.

  Since the first sample and hold circuit 312 functions as sampling mixers 601 to 604 in FIG. 6 to be described later, the first clock signal CKq (= cos (ωt)) is input and the clock signal SCKq (= cos (ωt0)). ) Is output. Here, the phase difference t0 is a phase difference between the first clock signal CKq and the input data Di. Similarly, since the second sample and hold circuit 313 functions as sampling mixers 601 to 604 in FIG. 6 described later, the second clock signal CKi (= sin (ωt)) is input and the clock signal SCKI (= sin). (Ωt0)) is output.

As shown in FIG. 5B, the first mixer circuit 314 includes a first clock signal CKq (= cos (ωt)) and an output signal SCKi (= sin (ωt0)) of the second sample and hold circuit 313. Are mixed (multiplied) to output a signal CK1. The signal CK1 is expressed by the following equation.
CK1 = CKq × SCKI
= Cos (ωt) × sin (ωt0)

As shown in FIG. 5B, the second mixer circuit 315 includes a second clock signal CKi (= sin (ωt)) and an output signal SCKq (= cos (ωt0)) of the first sample hold circuit 312. Are mixed (multiplied) to output a signal CK2. The signal CK2 is expressed by the following equation.
CK2 = CKi × SCKq
= Sin (ωt) × cos (ωt0)

As shown in FIG. 5C, the subtractor 316 outputs the reproduction clock signal CKo by subtracting the output signal CK1 of the first mixer circuit 314 from the output signal CK2 of the second mixer circuit 315. The recovered clock signal CKo is expressed by the following equation.
CKo = CK2-CK1
= Sin (ωt) × cos (ωt0) −cos (ωt) × sin (ωt0)
= Sin (ω (t−t0))

  The reproduced clock signal CKo is a clock signal obtained by correcting the phase difference t0 with respect to the second clock signal CKi (= sin (ωt)). By correcting the phase difference t0, the frequency shift is also corrected. As a result, the recovered clock signal CKo is a signal having the same frequency and phase as the input data Di. The clock recovery circuit 301 can generate a recovered clock signal CKo with the phase difference t0 corrected. This corresponds to sampling phase adjustment for reception.

  The update of the phase difference t0 is continuously performed at the transition timing of the input data Di. Updating the phase difference continuously is equivalent to adjusting the frequency deviation and can absorb the frequency offset between the transmitting and receiving apparatuses. As shown in FIG. 4, when the transition interval of the input data Di is a short period, the change in the phase difference t0 is extremely small, and the frequency and phase of the recovered clock signal CKo hardly change. However, when the transition interval of the input data Di is long, the change in the phase difference t0 becomes large, so that the phase of the recovered clock signal CKo changes as in the period 401. However, the clock recovery circuit 301 of this embodiment can generate the recovered clock signal CKo without using a loop circuit as compared with the clock recovery circuit (gated VCO) in FIG. In addition, a stable reproduction clock signal CKo can be generated at high speed. The clock data recovery circuit 214 of the present embodiment can recover the clock signal of the subscriber side device 201 from the input data Di as a recovered clock signal CKo, and can recover the data Do at an optimal sampling timing.

  FIG. 6 is a circuit diagram illustrating a configuration example of the first sample hold circuit 312 in FIG. Although the configuration of the first sample and hold circuit 312 will be described as an example, the configuration of the second sample and hold circuit 313 is the same as the configuration of the first sample and hold circuit 312. FIG. 6 shows an example of a sample / hold circuit of a double edge trigger that performs sampling at both the rising edge and falling edge timings of the input data Di.

  Although FIG. 3A illustrates the case of a single-ended signal as an example, it may be a single-ended signal or a differential signal. Hereinafter, the case of differential signals will be described as an example. The voltage controlled oscillator 311 in FIG. 3A generates four-phase clock signals CKq, / CKq, CKi, / CKi. The first clock signals CKq and / CKq are differential signals whose phases are inverted from each other. The second clock signals CKi and / CKi are differential signals whose phases are inverted from each other. The input data Di and / Di are differential signals whose phases are inverted from each other. The first sample hold circuit 312 receives the first clock signals CKq and / CKq and the input data Di and / Di, and outputs the clock signals SCKq and / SCKq. The clock signals SCKq, / SCKq are differential signals whose phases are inverted from each other. Similarly, the second sample and hold circuit 313 receives the second clock signals CKi and / CKi and the input data Di and / Di, and outputs the clock signals SCKI and / SCKI. The clock signals SCKi, / SCKi are differential signals whose phases are mutually inverted.

  The first sample and hold circuit 312 includes sampling mixers 601 to 604, a differential amplifier circuit 605, and selection circuits 606 to 609. The sampling mixer 601 includes p-channel field effect transistors 611 and 612, and receives the first clock signal CKq and the input data Di and / Di. Sampling mixer 602 has p-channel field effect transistors 613 and 614, and receives first clock signal / CKq and input data Di and / Di. The sampling mixer 603 includes p-channel field effect transistors 615 and 616, and receives the first clock signal CKq and the input data Di and / Di. Sampling mixer 604 has p-channel field effect transistors 617 and 618, and receives first clock signal / CKq and input data Di and / Di.

  The differential amplifier circuit 605 includes n-channel field effect transistors 623 to 626, current sources 621 and 622, and resistors 627 to 630, amplifies output signals of the sampling mixers 601 to 604 as differential input signals, and outputs differential outputs. Output a signal.

  The selection circuit 606 includes a p-channel field effect transistor 641 and an n-channel field effect transistor 642, receives input data Di and / Di, and outputs a signal to the terminal of the output signal / SCKq. The selection circuit 607 includes a p-channel field effect transistor 643 and an n-channel field effect transistor 644, inputs the input data Di, / Di, and outputs a signal to the terminal of the output signal SCKq. The selection circuit 608 includes a p-channel field effect transistor 645 and an n-channel field effect transistor 646, inputs the input data Di and / Di, and outputs a signal to the terminal of the output signal / SCKq. The selection circuit 609 includes a p-channel field effect transistor 647 and an n-channel field effect transistor 648, inputs the input data Di and / Di, and outputs a signal to the terminal of the output signal SCKq.

  Since the output signals of the sampling mixers 601 to 604 are very close to the signal frequency ω0 of the input data Di, / Di and the frequency ω of the clock signals CKq, CKi, the level of the input data Di, / Di and the clock signals CKq, / CKq The signal has a phase difference t0. The differential amplifier circuit 605 amplifies the signal having the phase difference t0. The selection circuits 606 to 609 select the amplified signal having the phase difference t0 and output the clock signals SCKq and / SCKq. The clock signal SCKq is a signal of cos (ωt0). As described above, the first sample hold circuit 312 samples and holds the first clock signal CKq (= cos (ωt)) at the timing of both the rising edge and the falling edge of the input data Di. The clock signal SCKq (= cos (ωt0)) is output.

  FIG. 7 is a circuit diagram illustrating a configuration example of the first mixer circuit 314, the second mixer circuit 315, and the subtractor 316 in FIG. A case of differential signals will be described as an example. The first mixer circuit 314 includes n-channel field effect transistors 701 to 706 and is connected to an n-channel field effect transistor 721 serving as a current source. The second mixer circuit 315 includes n-channel field effect transistors 711 to 716 and is connected to an n-channel field effect transistor 722 serving as a current source. A bias potential Vb is supplied to the gates of the n-channel field effect transistors 721 and 722. The first mixer circuit 314 receives the first clock signals CKq and / CKq and the clock signals SCKI and / SCKI and outputs the clock signals CK1 and / CK1. The clock signals CK1 and / CK1 are differential signals whose phases are inverted from each other. The second mixer circuit 315 receives the second clock signals CKi and / CKi and the clock signals SCKq and / SCKq and outputs the clock signals CK2 and / CK2. The clock signals CK2 and / CK2 are differential signals whose phases are inverted from each other. The subtractor 316 connects the output line of the first mixer circuit 314 and the output line of the second mixer circuit 315 by wiring, and regenerates a signal obtained by subtracting the clock signals CK1 and / CK1 from the clock signals CK2 and / CK2. Output as signals CKo, / CKo. The reproduction clock signals CKo and / CKo are differential signals whose phases are inverted from each other. The resistor 723 is connected between the node of the reproduction clock signal CKo and the node of the power supply potential VDD, and the resistor 724 is connected between the node of the reproduction clock signal / CKo and the node of the power supply potential VDD.

  The first mixer circuit 314 weights the component of the first clock signal CKq by the ratio of the signal SCKi and outputs a current. The second mixer circuit 315 weights the component of the second clock signal CKi by the ratio of the signal SCKq and outputs a current. The subtractor 316 subtracts the output currents of the mixer circuits 314 and 315 by wiring connection, converts the voltage with the resistors 723 and 724, and generates the regenerated clock signals CKo and / CKo.

(Second Embodiment)
FIG. 8 is a diagram illustrating a configuration example of the clock recovery circuit 301 according to the second embodiment. In the present embodiment (FIG. 8), low-pass filters 801 and 802 are added to the first embodiment (FIG. 3A). Hereinafter, differences of the present embodiment (FIG. 8) from the first embodiment (FIG. 3A) will be described. The first low-pass filter 801 filters the output signal SCKq of the first sample and hold circuit 312, attenuates the high frequency band signal, and passes the low frequency band signal. The second low-pass filter 802 filters the output signal SCKi of the second sample-and-hold circuit 313, attenuates the high-frequency band signal, and passes the low-frequency band signal. The first mixer circuit 314 mixes the first clock signal CKq and the output signal of the second low-pass filter 802, and outputs a signal CK1. The second mixer circuit 315 mixes the second clock signal CKi and the output signal of the first low-pass filter 801, and outputs a signal CK2.

  Since the sample hold circuits 312 and 313 perform phase difference detection for each transition of the input data Di, there are cases where high-frequency phase fluctuation (jitter) is superimposed on the phase of the input data Di. Jitter is uncorrelated with the frequency and phase fluctuations of the input data Di, and is merely noise that hinders frequency phase adjustment between the transmitting and receiving apparatuses. Therefore, it is necessary to remove this jitter. In the present embodiment, a first low-pass filter 801 is provided after the first sample-and-hold circuit 312, and a second low-pass filter 802 is provided after the second sample-and-hold circuit 313. Since the low-pass filters 801 and 802 can remove high-frequency jitter from the output signals of the sample hold circuits 312 and 313, a stable reproduction clock signal CKo can be generated.

(Third embodiment)
FIGS. 9A and 9B are diagrams showing a configuration example of the data reproduction circuit 302 (FIG. 3A) according to the third embodiment. FIG. 9A is a diagram illustrating a configuration example of the data reproduction circuit 302. The data reproduction circuit 302 includes a buffer 901, a delay lock loop (DLL) circuit 902, and a data determination circuit 903. The buffer 901 buffers (amplifies) the recovered clock signal CKo for amplification and timing adjustment, and outputs the recovered clock signal CK3. The delay lock loop circuit 902 delays the input data Di so as to synchronize with the reproduction clock signal CK3 buffered by the buffer 901, and outputs the data D1. Since the buffer 901 buffers the recovered clock signal CKo, the recovered clock signal CK3 is delayed with respect to the input data Di. Therefore, the delay locked loop circuit 902 corrects the phase shift of the recovered clock signal CK3 caused by the buffer 901. Since the delay lock loop circuit 902 delays the input data Di, the phases of the input data D1 and the recovered clock signal CK3 are the same. The data determination circuit 903 is, for example, a D-type flip-flop, and performs binary determination on the output data D1 of the delay lock loop circuit 902 in synchronization with the reproduction clock signal CK3 buffered by the buffer 901, and outputs the reproduction data Do. . When the data determination circuit 903 is a D-type flip-flop, the data D1 is input to the D terminal, the reproduction clock signal CK3 is input to the clock terminal, and the reproduction data Do is output from the Q terminal. Specifically, the data determination circuit 903 is a slicer circuit, and, for example, similarly to FIG. 3B, the data D1 (Di) 2 is synchronized with the falling edge of the reproduction clock signal CK3 (CKo). Perform value judgment. When the data D1 is larger than the threshold, the high-level reproduction data Do of “1” is output, and when the data D1 is smaller than the threshold, the low-level reproduction data Do of “0” is output.

  FIG. 9B is a diagram illustrating a configuration example of the delay locked loop circuit 902 in FIG. The delay lock loop circuit 902 includes a digitally controlled delay line (DCDL) 911, a phase detector (PD) 912, and an up / down counter 913. The digital control delay line 911 delays the input data Di by a delay time corresponding to the delay code DC and outputs data D1. The phase detector 912 detects the phase difference of the data D1 with respect to the reproduced clock signal CK3, and outputs an up signal UP or a down signal DN according to the phase difference. The up / down counter 913 counts the up signal UP and the down signal DN, and outputs a delay code DC to the digital control delay line 911 according to the count value. This loop circuit operates so that the phase difference between the data D1 and the recovered clock signal CK3 approaches 0, and the phases of the data D1 and the recovered clock signal CK3 eventually become the same.

  According to the first to third embodiments, the clock recovery circuit 301 can generate the recovered clock signal CKo without using a loop circuit such as the gated VCO of FIG. The clock signal CKo can be generated at high speed.

  The data clock recovery circuit 214 can be applied to a high-speed interface that performs inter-chip communication and internal (in-between) data communication in addition to the communication system of FIG. 2, and is particularly applicable to a burst transmission receiver.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

301 clock recovery circuit 302 data recovery circuit 311 voltage controlled oscillator 312 first sample hold circuit 313 second sample hold circuit 314 first mixer circuit 315 second mixer circuit 316 subtractor

Claims (5)

A first sample and hold circuit that samples and holds a first clock signal in synchronization with input data;
A second sample hold for inputting a second clock signal having the same frequency and a phase difference of 90 degrees with respect to the first clock signal, and sampling and holding the second clock signal in synchronization with the input data. Circuit,
A first mixer circuit for mixing the first clock signal and the output signal of the second sample and hold circuit;
A second mixer circuit for mixing the second clock signal and the output signal of the first sample and hold circuit;
A clock recovery circuit comprising: a subtractor that outputs a recovered clock signal by subtracting the output signal of the first mixer circuit from the output signal of the second mixer circuit. A first low pass filter for filtering the output signal of the first sample and hold circuit;
A second low pass filter for filtering the output signal of the second sample and hold circuit;
The first mixer circuit mixes the first clock signal and the output signal of the second low-pass filter,
2. The clock recovery circuit according to claim 1, wherein the second mixer circuit mixes the second clock signal and an output signal of the first low-pass filter. A clock recovery circuit for outputting a recovered clock signal synchronized with input data;
A data reproduction circuit for reproducing the input data in synchronization with the reproduction clock signal;
The clock recovery circuit includes:
A first sample and hold circuit that samples and holds a first clock signal in synchronization with the input data;
A second sample hold for inputting a second clock signal having the same frequency and a phase difference of 90 degrees with respect to the first clock signal, and sampling and holding the second clock signal in synchronization with the input data. Circuit,
A first mixer circuit for mixing the first clock signal and the output signal of the second sample and hold circuit;
A second mixer circuit for mixing the second clock signal and the output signal of the first sample and hold circuit;
A clock data recovery circuit comprising: a subtractor that outputs a recovered clock signal by subtracting the output signal of the first mixer circuit from the output signal of the second mixer circuit. The clock recovery circuit includes:
A first low pass filter for filtering the output signal of the first sample and hold circuit;
A second low pass filter for filtering the output signal of the second sample and hold circuit;
The first mixer circuit mixes the first clock signal and the output signal of the second low-pass filter,
4. The clock data recovery circuit according to claim 3, wherein the second mixer circuit mixes the second clock signal and the output signal of the first low-pass filter. The data reproduction circuit includes:
A buffer for buffering the recovered clock signal;
A delay-locked loop circuit that delays the input data to synchronize with the recovered clock signal buffered by the buffer;
5. The clock data recovery circuit according to claim 3, further comprising a data determination circuit that binary-determines the output data of the delay lock loop circuit in synchronization with the recovery clock signal buffered by the buffer.

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