JP2008227786A - Method and circuit for reproductive clock data - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To conduct a normal discriminating operation even when the duty of input data is displaced largely from 100%. <P>SOLUTION: In a method for reproducing a clock data, a reproductive clock synchronizing with the edge timing of the input data is generated, and the input data is discriminated by the reproductive clock. In the method for reproducing the clock data, a correction data correcting the duty of the input data in response to the level of a correction signal is obtained, and the duty of the correction data is detected by the reproductive clock and the correction signal is generated. The generation of the reproductive clock and the discrimination of the data are conducted on the basis of the correction data. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a clock / data recovery method and circuit for recovering a clock from input data with a disturbed waveform and identifying input data based on the clock, and more particularly to a clock for identifying data by correcting the duty of input data. -It relates to a data reproduction method and circuit.

  FIG. 8 shows a conventional clock / data recovery circuit, and FIG. 9 shows details thereof (see, for example, Non-Patent Document 1). The conventional clock / data recovery circuit includes a clock recovery circuit 100 and a data identification circuit 200. For example, as shown in FIG. 9, the clock recovery circuit 100 includes a gating circuit 110 including a buffer 111, a delay circuit 112, and a NAND circuit 113, and a gated VCO circuit including inverters 121 and 122 and a NAND circuit 123. . The gating circuit 110 detects the rising edge of the input data, and the gated VCO 120 generates a reproduction clock that is phase-synchronized with the rising edge. The data identification circuit 200 is configured by a D-type flip-flop circuit.

FIGS. 10A and 10B show the operation of the conventional clock / data recovery circuit. FIG. 10A shows the case where the duty of the input data is 100%, and the conventional clock / data recovery circuit operates normally. The gating circuit 110 generates a pulse having a width of 1/2 UI at the rising edge of the input data (not shown in FIG. 10) and inputs the pulse to the NAND circuit 123 of the gated VCO circuit 120, thereby changing the phase of the recovered clock to the input data. To match the phase. As a result, the clock recovery circuit 100 outputs a recovered clock whose rising time coincides with the rising edge of the input data. In the data identification circuit 200, input data is input to the D input of the flip-flop circuit, and a recovered clock is input to the CK input. Since the phase of the recovered clock matches the phase of the input data, the waveform is shaped starting from the falling edge of the recovered clock, and recovered output data is obtained from the Q output.
M. Nogawa, et.al., "A lOGb / s Burst-Mode CDR IC in 0.13um CMOS", ISSCC 2005 Dig. Tech. Papers, PP.228-229, Figure 12.5.4.

  FIG. 10B shows a case where the duty of the input data is extremely smaller than 100%, that is, the time width of H of the input data signal is about half or less of 1 UI. Also in this case, the gating circuit 110 and the gated VCO circuit 120 operate and a reproduction clock is output.

  However, in the flip-flop circuit as the data identification circuit 200, when attention is paid to H when the data string is L, H, L, the data has already dropped to L at the fall time of the reproduction clock, Incorrect data strings L, L, and L are output.

  Here, an example in which the duty is small is illustrated, but erroneous data is also output when the duty is extremely larger than 100%. That is, in the flip-flop circuit as the data identification circuit 200, when the data string is L such as H, L, and H, the previous H data still remains at the clock falling time, which is erroneous. Data H, H, and H are output.

  As described above, when the duty of the input data is greatly different from 100%, there is a problem of outputting erroneous data.

  An object of the present invention is to provide a clock / data recovery method and circuit that allow a normal identification operation to be performed even when the duty of input data is shifted more than 100%.

In order to achieve the above object, a clock data recovery method according to claim 1 of the present invention generates a recovered clock synchronized with the edge timing of input data, and identifies the data of the input data using the recovered clock. In the data reproduction method, correction data obtained by correcting the duty of the input data according to the level of the correction signal is obtained, the correction signal is generated by detecting the duty of the correction data using the reproduction clock, and based on the correction data The reproduction clock is generated and the data is identified.
According to a second aspect of the present invention, there is provided a clock / data recovery circuit that receives input data and generates a recovery clock synchronized with the edge timing of the input data, and inputs the input data and outputs the input data by the recovery clock. In a clock data recovery circuit comprising a data identification circuit for performing data identification, a data duty correction circuit for outputting correction data obtained by correcting the duty of the input data in accordance with the level of the correction signal, and a duty of the correction data A data duty detection circuit that detects the recovery clock and generates the correction signal, wherein the correction data is input to the clock recovery circuit and the data identification circuit in place of the input data.
According to a third aspect of the present invention, in the clock / data recovery circuit according to the second aspect, the data duty correction circuit has a duty ratio of the input data in accordance with a digital value of the correction signal output from the data duty detection circuit. It is characterized by correcting.
According to a fourth aspect of the present invention, in the clock and data recovery circuit according to the second or third aspect, the clock recovery circuit is output from the gating circuit that detects an edge of the correction data and the gating circuit. It is characterized by comprising a gated VCO circuit that generates a reproduction clock synchronized by an edge detection signal.
According to a fifth aspect of the present invention, in the clock / data recovery circuit according to the second, third, or fourth aspect, the data duty detection circuit is configured by a flip-flop circuit and a low-pass filter, and is used as a D input of the flip-flop circuit. The recovered clock is input, an inverted signal of the correction data is input to the CK input of the flip-flop circuit, the Q output of the flip-flop circuit is used as the input of the low-pass filter, and the output of the low-pass filter is used as the correction signal. It is characterized by doing.

  According to the present invention, it is possible to perform a normal identification operation even when the duty of input data deviates more than 100%. That is, if the duty of the input data differs by more than 100%, whether the difference is fixed in time or fluctuates, the duty correction amount changed according to the difference from 100% of the duty is changed. A correction signal can be obtained, and a normal identification operation can be performed by performing duty correction of the input data in accordance with the correction signal. In addition, the duty of input data is detected not by the average value of data H and L, but by comparing the time position of the (falling) edge of the data and the recovered clock, thereby making it dependent on the continuous code length of the data. The time when the duty correction is completed can be determined. As a result, duty correction of input data can be realized at high speed even for data in which consecutive bits of the same code continue for a long time. Furthermore, by digitizing the correction signal, it is possible to perform duty correction in a tolerant manner against noise coming to the correction signal, without depending largely on variations in devices such as transistors, and stable identification operation. Can be achieved.

<First embodiment>
FIG. 1 shows a first embodiment of the clock and data recovery circuit of the present invention. The clock recovery circuit 100 and the data identification circuit 200 are configured by the same circuit as the conventional one described in FIG. Reference numeral 300 denotes a data duty detection circuit, and reference numeral 400 denotes a data duty correction circuit.

  The data duty detection circuit 300 includes a D-type flip-flop circuit 301 and a low-pass filter 302 as shown in FIG. The data duty detection circuit 300 inputs a reproduction clock to the D input of the flip-flop circuit 301 and inputs an inverted signal of correction data to the CK input. A low-pass filter 302 is connected to the Q output, and the output of the low-pass filter 302 becomes the output of the data duty detection circuit 300.

  The data duty correction circuit 400 includes a driver 401, a capacitor 402, and a threshold circuit 402 as shown in FIG. Input data is connected to the input of the driver 401, and the capacitor 402 and the input of the threshold circuit 403 are connected to the output of the driver 401. The other end of the capacitor 402 is connected to GND, for example. The threshold circuit 403 determines the threshold value of the integral value of the input data using the correction signal and outputs the result, which becomes the output of the data duty correction circuit 400.

  The operation of the data duty detection circuit 300 in FIG. 3 will be described with reference to FIGS. FIG. 4A shows a case where the correction data has already approached 100% duty. Since the recovered clock is in phase with the correction data, the time when the correction data (inverted) falls and the time when the recovered clock rises substantially coincide. Here, if the duty is 100%, the rising edge of the correction data (inverted) appears at a time point that is a natural multiple of 1 UI from an arbitrary rising time point of the data. This indicates that the time when the correction data (inversion) rises substantially coincides with the time when the reproduction clock rises. Therefore, the flip-flop circuit 301 outputs H or L to the output Q of the flip-flop circuit 301 at the rising edge of the correction data (inversion) in response to a slight fluctuation of the reproduction clock. The correction signal, which is the output of the data duty detection circuit 300, is a time average of the output of the flip-flop circuit 301 by the low-pass filter 302. When the averaging time is long, the average value indicates an intermediate value between H and L, and the fact that the data duty is close to 100% is displayed as a correction signal.

  On the other hand, as shown in FIG. 4B, when the duty of the correction data is smaller than 100%, the probability that the rising edge of the correction data (inversion) is located at the time when the reproduction clock is L increases. The probability that the output of the flip-flop circuit 301 becomes L increases, the voltage level as a result of time averaging by the low-pass filter 302 approaches L, and the fact that the data duty is smaller than 100% is displayed as a correction signal.

  Further, as shown in FIG. 4C, when the duty of the correction data is larger than 100%, the probability that the rising edge of the correction data (inverted) is located at the time when the reproduction clock is H increases. The probability that the output of the flip-flop circuit 301 becomes H increases, the voltage level as a result of time averaging by the low-pass filter 302 approaches H, and the fact that the data duty is greater than 100% is displayed as a correction signal.

  As described above, the data duty detection circuit 300 shown in FIG. 3 has a correction signal having a voltage level lower than the center voltage level when the data duty is smaller than 100% according to the deviation amount from 100% of the duty of the correction data. When the data duty is larger than 100%, a correction signal having a voltage level higher than the center voltage level is output.

  Next, the operation of the data duty correction circuit 400 of FIG. 5 will be described with reference to FIG. In the data duty correction circuit 400, the rising time and the falling time of the input data of the data 1 that is the output of the driver 401 are extended by the capacitor 402 connected to the output of the driver 401. The threshold circuit 403 in the next stage sets the voltage level of the correction signal as a threshold, outputs H to the output terminal when the input data voltage exceeds the threshold, and sets L to the output terminal when the input data voltage falls below the threshold. This is an existing circuit to output.

  When a signal with a duty of 100% is input as input data with respect to data 1 in which the rise and fall times of the input data are extended, the voltage level of the correction signal at which the duty of the output data becomes 100% is the center voltage of the correction signal. Set to. When the correction signal becomes lower than the center potential, the data duty correction circuit 400 outputs a signal having a duty larger than the input data as correction data. When the correction signal becomes higher than the center potential, the data duty correction circuit 400 outputs a signal having a duty smaller than that of the input data as correction data. As described above, the data duty correction circuit 400 corrects the duty of the input data in accordance with the level of the correction signal and outputs it as correction data.

  By using the correction signal that is the output of the data duty detection circuit 300 as the threshold value of the data duty correction circuit 400 and the correction data that is the output of the data duty correction circuit 400 as the input of the data duty detection circuit 300, FIG. As shown in FIG. 2A, when the duty of the input data is 100%, the correction signal stops at the center potential, and the input data is output as it is as correction data. The clock / data recovery circuit operates normally as in the conventional example.

  On the other hand, as shown in FIG. 2B, when the duty of the input data is extremely smaller than 100%, the correction signal moves to a potential lower than the center potential, and the duty of the input data is increased and output as correction data. The Unlike the conventional example, the clock / data recovery circuit outputs normal data. Although not particularly shown in FIG. 2, when the duty of the input data is extremely larger than 100%, the correction signal moves to a potential higher than the center potential, and the duty of the input data is reduced and output as correction data. Unlike the conventional example, the clock / data recovery circuit outputs normal data.

  Here, the time required for the data duty correction of the first embodiment will be mentioned. In the first embodiment, the average value of the input data itself, which is used in a conventional amplifier circuit or the like (example), is taken, and a correction signal corresponding to the H time and the L time is not used. This is because, in this conventional method, the potential fluctuation of the correction signal largely depends on the continuous bit length of the same code of the input data. (That is, if the averaging time is not set longer as the continuous bit length becomes longer, the voltage level of the correction signal largely fluctuates until the end of the continuous signal, and the duty also fluctuates greatly.)

  On the other hand, in the first embodiment, using the fact that the rise time of the correction data and the reproduction clock coincide with each other, the data fall only when there is a data transition in the data duty detection circuit 300. The duty of the input data is detected from the relationship between the edge time and the rising edge time of the recovered clock. As a result, the data duty correction time is determined without depending on the continuous bit length of the same code of the input data (noting only the variation of the average value of the output of the low-pass filter 302 of the data duty detection circuit 300). Has design freedom to As a result, duty correction can be performed at high speed even for input data in which consecutive bits of the same code continue for a long time.

  The characteristics of the first embodiment are summarized as follows. First, even when the duty of the input data deviates more than 100%, a normal identification operation can be performed. That is, when the duty of the input data differs by more than 100%, whether the difference is fixed in time or fluctuates, the duty is within the design range of the low-pass filter 302 in the data duty detection circuit 300. A duty correction amount changed according to the difference from 100% can be obtained, and the data duty correction circuit 400 performs duty correction of the input data according to the correction signal indicating the duty correction amount. Identification operation is enabled. Next, since the duty of the input data is detected not by the average value of data H and L but by comparing the time position of the (falling) edge of the data and the recovered clock, the continuous code length of the data is calculated. The time for completing the duty correction can be determined without depending on it. As a result, duty correction of input data can be realized at high speed even for data in which consecutive bits of the same code continue for a long time.

<Second embodiment>
A second embodiment of the present invention will be described with reference to FIG. The difference from the first embodiment is that the output of the data duty detection circuit 300 is fed back to the data duty correction circuit 400 as a digital signal. The output of the data duty detection circuit 300 shown in FIG. 3 is divided into an intermediate value indicating the vicinity of 100% duty, L indicating that the duty is decreasing, and H indicating that the duty is increasing. .

  Therefore, as shown in FIG. 7, it is necessary to add an analog / digital conversion circuit 500 to the output of the data duty detection circuit 300 to increase the 2-bit digital signal LH and the duty when the duty correction is unnecessary. The case is represented by LL, and the case where the duty needs to be reduced is represented by HH. A digital / analog conversion circuit 600 is added in front of the data duty correction circuit 400, an analog signal is generated according to these two bits, and is input to the data duty correction circuit 400 as a threshold value. In this way, the duty can be roughly corrected, but can be corrected to the extent that the data identification unit 200 does not make a mistake. Also, the accuracy of duty correction can be improved by increasing the conversion accuracy of the number of digital bits for analog / digital conversion and digital / analog conversion from the above-mentioned 2 bits to more bits.

  In the second embodiment, by digitizing the correction signal, it is possible to perform duty correction in a tolerant manner with respect to noise arriving at the correction signal, without depending largely on variations in devices such as transistors. , Stable identification operation can be achieved.

1 is a block diagram of a clock / data recovery circuit according to a first embodiment of the present invention. FIG. (a) is an operation waveform diagram of the clock / data recovery circuit of FIG. 1 when the duty of the input data is 100%, and (b) is an operation waveform diagram when the input data is extremely smaller than 100%. FIG. 2 is a block diagram showing a configuration of a data duty detection circuit of the clock / data recovery circuit of FIG. 1. 3A is an operation waveform diagram of the data duty detection circuit of FIG. 3 when the correction data is close to 100%, FIG. 3B is an operation waveform diagram when the correction data is less than 100%, and FIG. It is an operation | movement waveform diagram in the case of larger than%. 2 is a block diagram showing a configuration of a data duty correction circuit of the clock / data recovery circuit of FIG. 1; FIG. 6 is an operation waveform diagram of the data duty correction circuit of FIG. 5. FIG. 5 is a block diagram of a clock / data recovery circuit according to a second embodiment of the present invention. It is a block diagram of a conventional clock and data recovery circuit. FIG. 9 is a detailed block diagram of the clock / data recovery circuit of FIG. 8. (a) is an operation waveform diagram of the clock / data recovery circuit of FIG. 9 when the duty of the input data is 100%, and (b) is an operation waveform diagram when the input data is extremely smaller than 100%.

Explanation of symbols

100: clock recovery circuit, 110: gating circuit, 111: buffer, 112: delay circuit, 113: NAND circuit, 120: gated VCO, 121, 122: inverter, 123: NAND circuit 200: data identification circuit 300: data duty Detection circuit 301: Flip-flop circuit 302: Low-pass filter 400: Data duty correction circuit 401: Driver 402: Capacitance 403: Threshold circuit 500: Analog / digital conversion circuit 600: Digital / analog conversion circuit

Claims (5)

In a clock and data recovery method for generating a recovered clock synchronized with the edge timing of input data and performing data identification of the input data by the recovered clock,
Correction data obtained by correcting the duty of the input data according to the level of the correction signal is obtained, the correction signal is generated by detecting the duty of the correction data using the reproduction clock, and the reproduction clock is generated based on the correction data And a clock and data recovery method, wherein the data identification is performed. Clock data including a clock recovery circuit that inputs input data and generates a recovered clock synchronized with the edge timing, and a data identification circuit that inputs the input data and identifies the input data by the recovered clock In the playback circuit,
A data duty correction circuit for outputting correction data obtained by correcting the duty of the input data in accordance with the level of the correction signal; and a data duty detection circuit for generating the correction signal by detecting the duty of the correction data by the reproduction clock; The clock data recovery circuit is characterized in that the correction data is input to the clock recovery circuit and the data identification circuit in place of the input data. The clock and data recovery circuit according to claim 2,
The clock data recovery circuit, wherein the data duty correction circuit corrects the duty of the input data in accordance with a digital value of the correction signal output from the data duty detection circuit. The clock / data recovery circuit according to claim 2 or 3,
The clock recovery circuit includes a gating circuit that detects an edge of the correction data and a gated VCO circuit that generates a recovery clock synchronized with an edge detection signal output from the gating circuit. Clock and data recovery circuit. The clock / data recovery circuit according to claim 2, 3 or 4,
The data duty detection circuit is composed of a flip-flop circuit and a low-pass filter, the reproduced clock is input to the D input of the flip-flop circuit, and the inverted signal of the correction data is input to the CK input of the flip-flop circuit, A clock / data recovery circuit, wherein a Q output of the flip-flop circuit is used as an input of the low-pass filter, and an output of the low-pass filter is used as the correction signal.

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