CN101606349A - Clock/data recovery circuit - Google Patents
Clock/data recovery circuit Download PDFInfo
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- CN101606349A CN101606349A CNA200780051221XA CN200780051221A CN101606349A CN 101606349 A CN101606349 A CN 101606349A CN A200780051221X A CNA200780051221X A CN A200780051221XA CN 200780051221 A CN200780051221 A CN 200780051221A CN 101606349 A CN101606349 A CN 101606349A
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Abstract
The invention provides a kind of clock/data recovery circuit, comprising: data duty cycle correcting circuit (400), by the data of the duty ratio of input data being proofreaied and correct output calibration according to the level of correction signal; Clock recovery circuitry (100), the clock recovered that generation is regularly synchronous with the edge of the data of described correction; Data decision circuit (200) comes the data of described correction are carried out data decision based on described clock recovered; And data duty cycle testing circuit (300), detect the duty ratio of the data of described correction based on described clock recovered, and represent the correction signal of duty cycle correction amount to described data duty cycle correcting circuit output.
Description
Technical field
The present invention relates to clock/data recovery circuit, recovered clock and discern the input data from input data based on this clock with waveform fluctuation, more specifically, the present invention relates to the duty ratio clock/data recovery circuit proofreading and correct and discern to the input data.
Background technology
Figure 23 shows the layout of traditional clock/data recovery circuit.Figure 24 shows its detailed arrangement.For example list of references " M.Nogawa, et al. " A 10Gb/s Burst-ModeCDR IC in 0.13 μ m CMOS ", ISSCC 2005Dig.Tech.Papers, PP 228-229, Figure 12.5.4 " in this clock/data recovery circuit is disclosed.
This traditional clock/data recovery circuit comprises clock recovery circuitry 100 and data decision circuit 200.For example, as shown in figure 24, clock recovery circuitry 100 comprises gating circuit 110 and by the VCO of gate (voltage controlled oscillator) 120.Gating circuit 110 comprises buffer 111, delay circuit 112 and NAND circuit 113.Comprised inversion device 121 and 122 and NAND circuit 123 by the VCO 120 of gate.Gating circuit 110 detects the rising edge of input data DIN.Produced the clock recovered RCK of the rising edge homophase of data DIN and import by the VCO 120 of gate.Data decision circuit 200 is formed by the d type flip flop circuit.
The operation of traditional clock/data recovery circuit is described with reference to figure 25A to 25C and 26A to 26C.The duty ratio that Figure 25 A to 25C shows input data DIN is 100% situation, and, the clock/data recovery circuit operate as normal that this is traditional.Rising edge place at the input data DIN shown in Figure 25 A, it is the pulse of 1/2UI (unit gap) that gating circuit 110 produces width, and this pulse is input to by the NAND circuit 123 among the VCO 120 of gate, thereby make the phase place of phase place and input data DIN of clock recovered RCK be complementary.Thus, the clock recovered RCK (Figure 25 B) of the rising edge homophase of clock recovery circuitry 100 outputs and input data DIN.Data decision circuit 200 receives input data DIN via the data input pin D of flip-flop circuit, and receives clock recovered RCK via input end of clock CK.Clock recovered RCK and input data DIN homophase.The flip-flop circuit that comprises in the data decision circuit 200 begins the waveform of input data DIN is carried out shaping from the trailing edge of clock recovered RCK, and exports the dateout DOUT (Figure 25 C) that recovers from output Q.
Summary of the invention
The problem to be solved in the present invention
The duty ratio that Figure 26 A to 26C shows input data DIN is promptly imported the time width of data DIN at H level place and is shorter than 1/2 of about 1UI far below 100% situation.In this case, clock recovery circuitry 100 is also exported clock recovered RCK (Figure 26 B).
Note the H level part of the data flow L-H-L among the input data DIN shown in Figure 26 A.Among Figure 26 B, during the fall time of clock recovered RCK, the level of input data DIN is reduced to L from H.Therefore, the data flow L-L-L of the flip-flop circuit of composition data decision circuit 200 output error in dateout DOUT.
Figure 26 A to 26C has illustrated the example when input data DIN has low duty ratio.When the duty ratio of input data DIN far above 100% the time, the also dateout DOUT of output error.For example, note the L level part of the data flow H-L-H among the input data DIN.During the fall time of clock recovered RCK, input data DIN does not leave the L level as yet.The data flow H-H-H of the flip-flop circuit output error in dateout DOUT that therefore, comprises in the data decision circuit 200.
As mentioned above, if the duty ratio and 100% of input data DIN has than large deviation the data of then traditional clock/data recovery circuit output error.
Even the purpose of this invention is to provide the clock/data recovery circuit that when the duty ratio and 100% of input data is offset greatly, also can carry out normal data decision operation.
The scheme of dealing with problems
A kind of clock/data recovery circuit of the present invention comprises: the data duty cycle correcting circuit, by the data of the duty ratio of input data being proofreaied and correct output calibration according to the level of correction signal; Clock recovery circuitry, the clock recovered that generation is regularly synchronous with the edge of the data of described correction; The data decision circuit comes the data of described correction are carried out data decision based on described clock recovered; And the data duty cycle testing circuit, detect the duty ratio of the data of described correction based on described clock recovered, and represent the correction signal of duty cycle correction amount to described data duty cycle correcting circuit output.
Effect of the present invention
As mentioned above, according to the present invention,, also can carry out normal data decision operation even when the duty ratio and 100% of input data is offset greatly.More specifically, in the present invention, if the duty ratio and 100% deviation of input data are a lot, then can obtain correction signal, this correction signal is represented the duty cycle correction amount that changes according to the duty ratio of input data and 100% difference, and has nothing to do with fixing in time still variation of this difference.According to this correction signal the duty ratio of input data is proofreaied and correct and to have realized the operation of normal data decision.In the present invention, do not use the input H level of data and the mean value of L level, but the time location at the time location at the edge by will import data and the edge of clock recovered compares, the duty ratio of importing data is detected.This feasible length that can be independent of the consecutive identical numerical digit of data is determined the concluding time of duty cycle correction.Thereby, in the present invention, even, also can realize duty cycle correction at a high speed for wherein consecutive identical numerical digit is lasting than long input data.In addition, in the present invention, correction signal is carried out digitlization make and duty ratio to be proofreaied and correct not depending on largely under the situation that device (as transistor) changes, and guarantee to arrive the noise margin of correction signal simultaneously.This has realized the stable data decision operation.
Description of drawings
Fig. 1 is the block diagram that illustrates according to the layout of the clock/data recovery circuit of first embodiment of the invention;
Fig. 2 is the block diagram that illustrates according to the layout of the data duty cycle testing circuit of clock/data recovery circuit shown in Figure 1;
Fig. 3 is the block diagram that illustrates according to the layout of the data duty cycle correcting circuit of clock/data recovery circuit shown in Figure 1;
Fig. 4 A is the timing diagram that the waveform data duty cycle testing circuit, clock recovered that inputs among Fig. 2 is shown;
Fig. 4 B is illustrated in to be almost 100% duty ratio place, inputs to the timing diagram of the waveform of the data data duty cycle testing circuit, that proofread and correct among Fig. 2;
Fig. 4 C illustrates when the duty ratio of the data of proofreading and correct is almost 100% the timing diagram of the output waveform of the flip-flop circuit of the data duty cycle testing circuit among Fig. 2;
Fig. 4 D illustrates when the duty ratio of the data of proofreading and correct is almost 100%, the timing diagram of the waveform of the correction signal of the data duty cycle testing circuit output among Fig. 2;
Fig. 5 A is the timing diagram that the waveform data duty cycle testing circuit, clock recovered that inputs among Fig. 2 is shown;
Fig. 5 B is illustrated in to be lower than 100% duty ratio place, inputs to the timing diagram of the waveform of the data data duty cycle testing circuit, that proofread and correct among Fig. 2;
Fig. 5 C is that the duty ratio that is illustrated in the data of correction is lower than at 100% o'clock, the timing diagram of the output waveform of the flip-flop circuit of the data duty cycle testing circuit among Fig. 2;
Fig. 5 D is that the duty ratio that is illustrated in the data of correction is lower than at 100% o'clock, the timing diagram of the waveform of the correction signal of the data duty cycle testing circuit output among Fig. 2;
Fig. 6 A is the timing diagram that the waveform data duty cycle testing circuit, clock recovered that inputs among Fig. 2 is shown;
Fig. 6 B is illustrated in to be higher than 100% duty ratio place, inputs to the timing diagram of the waveform of the data data duty cycle testing circuit, that proofread and correct among Fig. 2;
Fig. 6 C is that the duty ratio that is illustrated in the data of correction is higher than at 100% o'clock, the timing diagram of the output waveform of the flip-flop circuit of the data duty cycle testing circuit among Fig. 2;
Fig. 6 D is that the duty ratio that is illustrated in the data of correction is higher than at 100% o'clock, the timing diagram of the waveform of the correction signal of the data duty cycle testing circuit output among Fig. 2;
Fig. 7 A is the timing diagram of waveform that the input data of the data duty cycle correcting circuit that inputs among Fig. 3 are shown;
Fig. 7 B is the timing diagram of waveform of dateout that the buffer of the data duty cycle correcting circuit among Fig. 3 is shown;
Fig. 7 C is the timing diagram that illustrates from the waveform of the data data duty cycle correcting circuit among Fig. 3, that proofread and correct;
Fig. 8 A is the timing diagram that the waveform of input data clock/data recovery circuit, that have 100% duty ratio that input among Fig. 1 is shown;
Fig. 8 B be illustrated in the input data duty ratio be 100% o'clock, the timing diagram of the waveform of the correction signal that clock/data recovery circuit produced among Fig. 1;
Fig. 8 C be illustrated in the input data duty ratio be 100% o'clock, the timing diagram of the waveform of the data of the correction that clock/data recovery circuit produced among Fig. 1;
Fig. 8 D be illustrated in the input data duty ratio be 100% o'clock, the timing diagram of the waveform of the clock recovered that clock/data recovery circuit produced among Fig. 1;
Fig. 8 E is that the duty ratio that is illustrated in the input data is 100% o'clock, the timing diagram of the waveform of the dateout of clock/data recovery circuit among Fig. 1 output;
Fig. 9 A illustrates timing diagram clock/data recovery circuit, that have the waveform of the input data that are lower than 100% duty ratio that inputs among Fig. 1;
Fig. 9 B is that the duty ratio that is illustrated in the input data is lower than at 100% o'clock, the timing diagram of the waveform of the correction signal that clock/data recovery circuit produced among Fig. 1;
Fig. 9 C is that the duty ratio that is illustrated in the input data is lower than at 100% o'clock, the timing diagram of the waveform of the data of the correction that clock/data recovery circuit produced among Fig. 1;
Fig. 9 D is that the duty ratio that is illustrated in the input data is lower than at 100% o'clock, the timing diagram of the waveform of the clock recovered that clock/data recovery circuit produced among Fig. 1;
Fig. 9 E is that the duty ratio that is illustrated in the input data is lower than at 100% o'clock, the timing diagram of the waveform of the dateout of the clock/data recovery circuit output among Fig. 1;
Figure 10 is the block diagram that illustrates according to the layout of the clock/data recovery circuit of second embodiment of the invention;
Figure 11 is the block diagram that illustrates according to the layout of the data duty cycle testing circuit of third embodiment of the invention;
Figure 12 A is the timing diagram that the waveform of the data data duty cycle testing circuit, that proofread and correct that input among Figure 11 is shown;
Figure 12 B illustrates the timing diagram data duty cycle testing circuit, the clock recovered waveform that inputs among Figure 11;
Figure 12 C is the timing diagram of output waveform that first flip-flop circuit of the data duty cycle testing circuit among Figure 11 is shown;
Figure 12 D is the timing diagram of output waveform that first XOR circuit of the data duty cycle testing circuit among Figure 11 is shown;
Figure 12 E is the timing diagram of waveform that the signal of the data duty cycle testing circuit output among Figure 11 is shown;
Figure 12 F is the timing diagram of output waveform that second flip-flop circuit of the data duty cycle testing circuit among Figure 11 is shown;
Figure 12 G is the timing diagram of output waveform that second XOR circuit of the data duty cycle testing circuit among Figure 11 is shown;
Figure 12 H is the timing diagram of waveform that the reference signal of the data duty cycle testing circuit output among Figure 11 is shown;
Figure 13 is the figure that the characteristic of the signal of the data duty cycle testing circuit output among Figure 11 and reference signal is shown;
Figure 14 illustrates the block diagram that is added with data duty cycle testing circuit output circuit, among Figure 11;
Figure 15 A is the timing diagram that the waveform of the data data duty cycle testing circuit, that proofread and correct that input among Figure 14 is shown;
Figure 15 B is the timing diagram that the output waveform of the output circuit among Figure 14 is shown;
Figure 16 is the block diagram that illustrates according to the layout of the data duty cycle testing circuit of fourth embodiment of the invention;
Figure 17 A is the timing diagram that the waveform of the data data duty cycle testing circuit, that proofread and correct that input among Figure 16 is shown;
Figure 17 B is the timing diagram that the waveform data duty cycle testing circuit, clock recovered that inputs among Figure 16 is shown;
Figure 17 C is the timing diagram of output waveform that first flip-flop circuit of the data duty cycle testing circuit among Figure 16 is shown;
Figure 17 D be illustrate to the data duty cycle testing circuit among Figure 16 the 3rd with the timing diagram of the waveform of the input of circuit;
Figure 17 E is the timing diagram of waveform that the signal of the data duty cycle testing circuit output among Figure 16 is shown;
Figure 17 F is the timing diagram of output waveform that second flip-flop circuit of the data duty cycle testing circuit among Figure 16 is shown;
Figure 17 G be illustrate to the data duty cycle testing circuit among Figure 16 the 4th with the timing diagram of the waveform of the input of circuit;
Figure 17 H is the timing diagram of waveform that the reference signal of the data duty cycle testing circuit output among Figure 16 is shown;
Figure 18 is the block diagram that illustrates according to the layout of the data duty cycle correcting circuit of fifth embodiment of the invention;
Figure 19 is the block diagram that data duty cycle that the data duty cycle correcting circuit among Figure 18 is shown reduces the layout of circuit;
Figure 20 illustrates the block diagram of layout that data duty cycle among Figure 19 reduces the buffer of circuit;
Figure 21 illustrates the block diagram of layout that data duty cycle among Figure 19 reduces the emitter follower circuit of circuit;
Figure 22 is the block diagram that data duty cycle that the data duty cycle correcting circuit among Figure 18 is shown increases the layout of circuit;
Figure 23 is the block diagram that the layout of traditional clock/data recovery circuit is shown;
Figure 24 is the block diagram that the detailed arrangement of the traditional clock/data recovery circuit among Figure 23 is shown;
Figure 25 A is the timing diagram that the waveform of input data clock/data recovery circuit, that have 100% duty ratio that input among Figure 23 is shown;
Figure 25 B be illustrated in the input data duty ratio be 100% o'clock, the timing diagram of the waveform of the clock recovered that clock/data recovery circuit produced among Figure 23;
Figure 25 C is that the duty ratio that is illustrated in the input data is 100% o'clock, the timing diagram of the waveform of the dateout of clock/data recovery circuit among Figure 23 output;
Figure 26 A illustrates the timing diagram clock/data recovery circuit that inputs among Figure 23, that have the waveform of the input data that are lower than 100% duty ratio;
Figure 26 B is that the duty ratio that is illustrated in the input data is lower than at 100% o'clock, the timing diagram of the waveform of the clock recovered that clock/data recovery circuit produced among Figure 23; And
Figure 26 C is that the duty ratio that is illustrated in the input data is lower than at 100% o'clock, the timing diagram of the waveform of the dateout of the clock/data recovery circuit output among Figure 23.
Embodiment
First embodiment
Fig. 1 shows the layout according to the clock/data recovery circuit of first embodiment of the invention.Clock recovery circuitry 100 and data decision circuit 200 have with reference to Figure 23 circuit arrangement identical with the described prior art of Figure 24.Reference number 300 expression data duty cycle testing circuits, 400 expression data duty cycle correcting circuits.
As shown in Figure 2, data duty cycle testing circuit 300 comprises d type flip flop circuit 301 and low pass filter 302.Data duty cycle testing circuit 300 inputs to the data input pin D of flip-flop circuit 301 with clock recovered RCK, and the reverse signal of the data DCO that proofreaies and correct is inputed to input end of clock CK.Output Q is connected to the input of low pass filter 302.Low pass filter 302 is with the output of correction signal SCO output as data duty cycle testing circuit 300.
As shown in Figure 3, data duty cycle correcting circuit 400 comprises driver 401, capacitor 402 and threshold circuit 403.Input data DIN is connected to the input of driver 401.The output of driver 401 is connected to the input of capacitor 402 and threshold circuit 403.The other end of capacitor 402 for example is connected to (GND).Driver 401 and capacitor 402 form integrating circuit.Threshold circuit 403 uses correction signals to determine the integrated value of input data DIN as threshold value, and the data DCO that proofreaies and correct is exported with the output as data duty cycle correcting circuit 400.
Come the operation of the data duty cycle testing circuit 300 among Fig. 2 is described with reference to figure 4A to 4D, 5A to 5D and 6A to 6D.Fig. 4 B, 5B and 6B show DCO, and DCO is the reverse signal of data DCO of the correction of data duty cycle correcting circuit 400 output.
The duty ratio that Fig. 4 A to 4D shows the data DCO of correction has been almost 100% situation.The data DCO homophase of the correction shown in the clock recovered RCK shown in Fig. 4 A and Fig. 4 B.Therefore, the decline of the reverse signal DCO of the data DCO of correction is almost mated constantly with the rising of clock recovered RCK constantly.At 100% duty ratio place, the rising edge of the reverse signal DCO of the data DCO of correction appears at 1UI and multiply by the corresponding time point of the natural product place of putting from any rise time of these data.This show correction data DCO reverse signal DCO rising constantly with the rising of clock recovered RCK also coupling almost constantly.Therefore, according to the slight fluctuations of clock recovered RCK, flip-flop circuit 301 is exported the signal (Fig. 4 C) of H level or L level to output Q at the rising edge of the reverse signal DCO of the data DCO that proofreaies and correct.Time average is carried out in output by 302 pairs of flip-flop circuits 301 of low pass filter, obtains the correction signal SCO as the output of data duty cycle testing circuit 300.If average time is longer, then mean value shows the median between H level and the L level, and correction signal SCO represents that the duty ratio of the data DCO that proofreaies and correct is almost 100% (Fig. 4 D).
On the other hand, shown in Fig. 5 A to 5D, suppose that the duty ratio of the data DCO of correction is lower than 100%.In this case, to be positioned at the clock recovered RCK shown in Fig. 5 A be that probability during the L level rises to the rising edge of the reverse signal DCO of the data DCO of the correction shown in Fig. 5 B.The output Q of flip-flop circuit 301 changes into L level (Fig. 5 C) with high probability more.Carry out the voltage level that time average obtained by the output of 302 pairs of flip-flop circuits 301 of low pass filter and approach the L level.Therefore, correction signal SCO represents that the duty ratio of the data DCO that proofreaies and correct is lower than 100% (Fig. 5 D).
In addition, shown in Fig. 6 A to 6D, suppose that the duty ratio of the data DCO of correction is higher than 100%.In this case, to be positioned at the clock recovered RCK shown in Fig. 6 A be that probability during the H level rises to the rising edge of the reverse signal DCO of the data DCO of the correction shown in Fig. 6 B.The output Q of flip-flop circuit 301 changes into H level (Fig. 6 C) with high probability more.Carry out the voltage level that time average obtained by the output of 302 pairs of flip-flop circuits 301 of low pass filter and approach the H level.Therefore, correction signal SCO represents that the duty ratio of the data DCO that proofreaies and correct is higher than 100% (Fig. 6 D).
As mentioned above, be lower than 100% place in duty ratio, according to the duty ratio of the data DCO that proofreaies and correct and 100% side-play amount, data duty cycle testing circuit 300 outputs shown in Figure 2 have the correction signal SCO of the voltage level lower than center voltage level.Be higher than 100% place in duty ratio, 300 outputs of data duty cycle testing circuit have the correction signal SCO of the voltage level higher than center voltage level.
Next, the operation of data duty cycle correcting circuit 400 shown in Figure 3 is described with reference to figure 7A to 7C.The capacitor 402 of output that is connected to the driver 401 of data duty cycle correcting circuit 400 has prolonged rise time and the fall time of the input data DIN shown in Fig. 7 A, makes the output of driver 401 become data DIN2 (Fig. 7 B).At the next stage place, threshold circuit 403 uses the voltage level of correction signal SCO as threshold value TH.When the voltage of input data DIN2 surpassed threshold value TH, threshold circuit 403 was to the data DCO of the correction of output output H level.When the voltage of input data DIN2 during less than threshold value TH, the data DCO (Fig. 7 C) of threshold circuit 403 after the correction of output output L level.
The voltage level of correction signal SCO is set to the center voltage of correction signal SCO, voltage level place at correction signal SCO, with respect to the input data DIN2 that produces the rise time by prolonging input data DIN and fall time, the signal that has 100% duty ratio when input is during as input data DIN, and the duty ratio of dateout DOUT is 100%.If the voltage level of correction signal SCO is lower than central potential, then data duty cycle correcting circuit 400 output duty cycles are higher than the signal of the duty ratio of importing data DIN as the data DCO that proofreaies and correct.If the voltage level of correction signal SCO is higher than central potential, then data duty cycle correcting circuit 400 output duty cycles are lower than the signal of the duty ratio of importing data DIN as the data DCO that proofreaies and correct.In other words, data duty cycle correcting circuit 400 is proofreaied and correct the duty ratio of input data DIN according to the level of correction signal SCO, and the data DCO of output calibration.
To be used as the threshold value of data duty cycle correcting circuit 400 from the correction signal SCO of data duty cycle testing circuit 300 outputs.Will be from the data DCO of the correction of data duty cycle correcting circuit 400 output as input to data duty detection circuit 300.Use this layout, when the duty ratio of input data DIN was 100%, shown in Fig. 8 A, correction signal SCO is at the central potential place (Fig. 8 B) still.DIN directly exports as the data DCO (Fig. 8 C) that proofreaies and correct with the input data.Therefore, according to clock/data recovery circuit operate as normal as prior art of first embodiment.
On the other hand, when the duty ratio of input data DIN far below 100% the time, shown in Fig. 9 A, correction signal SCO moves (Fig. 9 B) to the current potential that is lower than central potential.To have the data DCO (Fig. 9 C) that the more input data DIN output conduct of high duty ratio is proofreaied and correct.Therefore, unlike the prior art, according to the clock/data recovery circuit output correct data of first embodiment.
Though do not specifically illustrate, when the duty ratio of input data DIN far above 100% the time, correction signal SCO moves to the current potential that is higher than central potential.To have the data DCO that the more input data DIN output conduct of low duty ratio is proofreaied and correct.Therefore, unlike the prior art, according to the clock/data recovery circuit output correct data of first embodiment.
The data duty cycle required moment of correction to first embodiment describes.Though traditional amplifying circuit etc. self average the input data,, in first embodiment, do not use such correction signal to produce and the moment of H level and the corresponding correction signal of the moment of L level.This is because in conventional method, and the potential change of correction signal depends on largely in the length of the consecutive identical numerical digit of input data.More specifically, the length of the successive bits of input data is long more, needs the average time of setting long more.Otherwise up to the ending of continuous signal, the voltage level of correction signal greatly changes, and makes duty ratio also greatly change.
Yet, in first embodiment, use the rising coupling constantly of the data DCO and the clock recovered RCK of correction, only when transformation of data taking place, data duty cycle testing circuit 300 detects the duty ratio of input data DIN based on the relation between the rising edge of the trailing edge of importing data DIN and clock recovered RCK.In first embodiment, this has guaranteed the length of determining be independent of the consecutive identical numerical digit of importing data DIN of the degree of freedom of design with permission data duty cycle corrected time, and the only variation of the mean value of the output of the low pass filter 302 of concentrated focused data duty detection circuit 300.Therefore, in first embodiment, even, also can carry out duty cycle correction at a high speed for wherein consecutive identical numerical digit is lasting than long input data DIN.
The characteristic feature of first embodiment is summarized as follows.At first, in first embodiment,, also can carry out normal data decision operation even when the duty ratio and 100% of input data DIN is offset greatly.More specifically, if the duty ratio of input data DIN and 100% difference are bigger, then can obtain the duty cycle correction amount that changes with 100% duty cycle difference according in the scope of design of the low pass filter 302 of data duty cycle testing circuit 300, and with this difference go up in time fixing still change irrelevant.Data duty cycle correcting circuit 400 comes the duty ratio of input signal DIN is proofreaied and correct based on the correction signal SCO of this duty cycle correction amount of expression.This has realized normal data decision operation.Next, in first embodiment, do not use the H level of input data DIN and the mean value of L level, but the time location of the time location of the trailing edge by will import data DIN and the trailing edge of clock recovered RCK compares, the duty ratio of importing data DIN is detected.This makes the length that can be independent of the consecutive identical numerical digit of importing data DIN determine the concluding time of duty cycle correction.Thereby in first embodiment, even, also can realize duty cycle correction at a high speed to wherein consecutive identical numerical digit is lasting than long input data DIN.
Second embodiment
Next with reference to Figure 10 the second embodiment of the present invention is described.Different with first embodiment, the correction signal SCO that data duty cycle testing circuit 300 is exported is converted to digital signal, then it is fed back to data duty cycle correcting circuit 400.The correction signal SCO that describes among first embodiment takes to represent that the duty ratio of the data DCO that proofreaies and correct is almost the H level that 100% median, L level that the expression duty ratio reduces and expression duty ratio raise.
As shown in figure 10, A/D change-over circuit 500 is added into the output of data duty cycle testing circuit 300.2 bit digital signal LH do not need to represent duty cycle correction.LL represents that duty ratio need become higher.HH represents that duty ratio need become lower.D/A change-over circuit 600 is added to the previous stage of data duty cycle correcting circuit 400.D/A change-over circuit 600 produces analog signal according to this 2 bit signal, and this analog signal is inputed to data duty cycle correcting circuit 400 as threshold value.This makes and can proofread and correct not cause data decision circuit 200 to produce any mistake duty ratio roughly.The digital bit number of A/D conversion and D/A conversion is increased to more from two, has improved the accuracy of duty cycle correction with the raising conversion accuracy.
In a second embodiment, can duty ratio be proofreaied and correct not depending on largely under the situation that device (as transistor) changes, guarantee to arrive the noise margin of correction signal SCO simultaneously.This has realized the stable data decision operation.
The 3rd embodiment
Next the third embodiment of the present invention is described.Figure 11 is the block diagram of layout that the data duty cycle testing circuit 300 of a third embodiment in accordance with the invention is shown.The data duty cycle testing circuit 300 of this embodiment comprise flip- flop circuit 303 and 304, XOR circuit 305 and 307 and with circuit 306 and 308.
Frequency and the phase locked clock recovered RCK of the data DCO that data duty cycle testing circuit 300 receptions of this embodiment are proofreaied and correct and the data DCO of frequency and phase place and correction, and output signal Err and reference signal Ref, the pulse duration of signal Err indicated the data DCO that proofreaies and correct duty ratio and 100% poor, reference signal Ref represents the reference pulse width when output signal Err.
The connection that next the data duty cycle testing circuit 300 of this embodiment is described is arranged.Flip-flop circuit 303 receives the data DCO that proofreaies and correct via data input pin D, and receives clock recovered RCK via input end of clock C.Flip-flop circuit 304 receives output signal Q1 via the output Q of data input pin D slave flipflop circuit 303, and receives the counter-rotating clock of clock recovered RCK via input end of clock C.XOR circuit 305 receives the data DCO that proofreaies and correct, and the output Q of slave flipflop circuit 303 receives output signal Q1.The output Q of XOR circuit 307 slave flipflop circuit 303 receives output signal Q1, and the output Q of slave flipflop circuit 304 receives output signal Q2.Receive output signal Q1 with circuit 306 from the output Q that XOR circuit 305 receives output signal and slave flipflop circuit 303, and output signal Err.Receive output signal with circuit 308 from XOR circuit 307, and the output Q of slave flipflop circuit 304 reception output signal Q2, and output reference signal Ref.
Come the duty ratio detecting operation according to the data duty cycle testing circuit 300 of this embodiment is described with reference to the timing diagram shown in the figure 12A to 12H.In the example shown in Figure 12 A to 12H, press the data DCO of the order input correction of H, L, H, H, L, L, H and L.When the duty ratio of the data DCO of the correction shown in Figure 12 A was 100%, 1 Bit data of H level continued unit interval T.The duty ratio of the data DCO that proofreaies and correct and 100% difference represented by time δ T, and the data DCO that time δ T appears at correction is when the H level is changed into the L level.By make differential time δ T with 100% duty ratio show as signal Err pulse duration increase or reduce, come duty ratio is detected and indicates.
The data duty cycle testing circuit 300 of this embodiment makes trigger 303 receive data DCO after the correction in response to clock recovered RCK, and the data DCO output of the correction that will receive at the falling edge of clock recovered RCK is as signal Q1.At the falling edge of the clock recovered RCK shown in Figure 12 B, the signal Q1 shown in Figure 12 C switches H and L state.Therefore, signal Q1 is that duty ratio is 100% data, and these data comprise the data flow identical with the data DCO that proofreaies and correct but have the timing that has postponed T/2.When the data DCO that proofreaies and correct represented different data with signal Q1, the output R1 of XOR circuit 305 transferred H (Figure 12 D) to.Because the data DCO of signal Q1 relative correction has postponed T/2, therefore at forward position and the falling edge of the data DCO that proofreaies and correct, XOR circuit 305 is exported the H pulses.The pulse duration at H level place and T/2 time of delay of signal Q1 are complementary.The pulse duration at L level place with by to/add/deduct that from T/2 time of delay of signal Q1 the time that the δ T as the change in duty cycle amount of the data DCO that proofreaies and correct obtains is corresponding.Carry out and operation with the output R1 of 306 couples of signal Q1 of circuit and XOR circuit 305, to eliminate H pulse output at the rising edge place of the data DCO that proofreaies and correct.Therefore, only when the data DCO that proofreaies and correct takes place to change, transfer the H level to from signal Err with circuit 306 outputs.The pulse duration of this signal Err represent by to/add/deduct the time (Figure 12 E) that obtains as δ T with the difference of 100% duty ratio from T/2.From Figure 12 A to 12H, it is evident that, only when the data DCO of the correction shown in Figure 12 A when the H level transitions is the L level, signal Err just transfers H level (Figure 12 E) to.If the data of H level or L level continue, signal Err does not transfer H to.
On the other hand, signal Q1 inputs to flip-flop circuit 304.Trigger 304 receives data based on the counter-rotating clock of clock recovered RCK, and thereby at the output signal Q2 of the rising edge place of clock recovered RCK (Figure 12 F).Signal Q2 relative signal Q1 has postponed T/2.307 couples of signal Q1 of XOR circuit and Q2 carry out xor operation, and output has the pulse (Figure 12 G) of the time width of T/2.Carry out and operation with the output R2 and the signal Q2 of 308 pairs of XOR circuit 307 of circuit, to eliminate pulse output at the rising edge place of signal Q1.Therefore, only when taking place to change, just exports the data DCO that proofreaies and correct reference signal Ref with circuit 308.The pulse duration of reference signal Ref is T/2 (Figure 12 H).From Figure 12 A to 12H, it is evident that, only when signal Q1 when the H level transitions is the L level, reference signal Ref just transfers the H level to.If the signal Q of H level or L level 1 continues, then reference signal Ref does not transfer H to.
Figure 13 is the figure that illustrates from the pulse duration (with the ratio of unit interval T) of the signal Err of data duty cycle testing circuit 300 output of this embodiment and reference signal Ref.When the duty ratio of the data DCO that proofreaies and correct when 60% becomes 140%, the pulse duration of signal Err becomes 0.1 linearly from 0.9, and this duty ratio is represented.Signal Ref has 0.5 isopulse width, and T/2 is expressed as the reference of pulse duration when the data DCO that proofreaies and correct changes.
Add output circuit 20 output of the data duty cycle testing circuit 300 of this embodiment shown in Figure 14 to, realized detecting quickly and accurately the duty ratio of the data DCO that proofreaies and correct.Below this situation will be described.Referring to Figure 14, the output circuit 20 that produces output Out from the signal Err and the Ref of data duty cycle testing circuit shown in Figure 11 300 output comprises current source Ie and Ir, switch SW e and SWr and capacitor C.
The current source Ie that is connected to power supply uses constant current I that capacitor C is charged.The current source Ir that is connected to ground (GND) emits constant current I from capacitor C.During the H of signal Err level, charge by only connecting switch SW e.During the H of reference signal Ref level, discharge by only connecting switch SW r.When importing the data DCO of the correction shown in Figure 15 A, as described with reference to figure 12A to 12H, only when the data DCO that proofreaies and correct changes, only by represent and the δ T of the difference of 100% duty ratio is added into the time durations that T/2 obtains that signal Err transfers the H level to.On the other hand, only when the data DCO that proofreaies and correct changed, during time T/2, reference signal Ref transferred the H level to.When signal Err and Ref transferred H to, switch SW e and SWr connected corresponding number of times.If the data DCO that proofreaies and correct changes once, then during time δ T ± T/2, use electric current I to capacitor C charging, and during time T/2, emit electric current I from capacitor C.
Therefore, the voltage at capacitor C two ends (being the output Out of output circuit 20) is from the current potential Vo voltage Δ V (Figure 15 B) that descended, the following Δ V that provides:
ΔV＝-η·δ·T·I·(1/C)·N (1)
Wherein, η is the transition probabilities of the data DCO of correction, and N is the input bit number, and I is the charge/discharge current of capacitor C.Equation (1) has been indicated by the duty ratio of the data DCO that proofreaies and correct and 100% difference δ and has been represented voltage difference delta V.
As the characteristic feature of this embodiment, only when the data DCO that proofreaies and correct changed, signal Err and Ref transferred the H level to.Even when the data DCO of the correction with consecutive identical numerical digit continues, switch SW e and SWr keep connecting to keep the current potential of capacitor C.Therefore in this embodiment, can correctly indicate the duty ratio of data DCO of correction and 100% difference δ, and quickly and accurately duty ratio be detected.
The 4th embodiment
Figure 16 shows the data duty cycle testing circuit 300 of a fourth embodiment in accordance with the invention.The circuit of this embodiment is similar to the circuit of the 3rd embodiment, therefore no longer repeats detailed description.In the 3rd embodiment, the data duty cycle testing circuit use flip- flop circuit 303 and 304, XOR circuit 305 and 307 and with circuit 306 and 308.The 4th embodiment can use still less circuit (be flip-flop circuit 309 and 310 and with circuit 311 and 312) form data duty cycle testing circuit 300.
In this embodiment, can import with the 3rd embodiment in the data DCO and the clock recovered RCK of identical correction, and identical signal Err and Ref among output and the 3rd embodiment.
The 5th embodiment
Figure 18 shows data duty cycle correcting circuit 400 according to a fifth embodiment of the invention.The data duty cycle correcting circuit 400 of this embodiment comprises that data duty cycle reduces circuit 404 and data duty cycle increases circuit 405.Notice that this embodiment handles differential signal.Input data DINP complimentary to one another and DINN are imported as input data DIN.The data DCP and the DCN of correction complimentary to one another are exported as the data DCO that proofreaies and correct.
Data duty cycle reduces the duty ratio that circuit 404 reduces to import data DINP and DINN.
Data duty cycle increase circuit 405 increases from data duty cycle according to correction signal SCO and reduces the output DOP1 of circuit 404 and the duty ratio of DON1, and the data DCP of output calibration and DCN.
Figure 19 illustrates the block diagram that data duty cycle reduces the layout of circuit 404.Data duty cycle reduce circuit 404 comprise buffer 4040,4042 and 4046, emitter follower circuit 4041,4043 and 4048, capacitor 4044 and 4045 and with circuit 4047.
Figure 20 is the block diagram that the layout of buffer 4040 is shown.Buffer 4040 comprises transistor 5000 and 5001, resistor 5002 and 5003 and current source 5004.Referring to Figure 20, INP and INN are input signals complimentary to one another.OUTP and OUTN are output signals complimentary to one another.All the other buffers 4042 and 4046 have the layout identical with buffer 4040.
Figure 21 is the block diagram that the layout of emitter follower circuit 4041 is shown.Emitter follower circuit 4041 comprises transistor 5005 and 5006 and current source 5007 and 5008.All the other emitter follower circuits 4043 and 4048 have the layout identical with emitter follower circuit 4041.
Use above-mentioned layout, data duty cycle reduces the duty ratio that circuit 404 reduces to import data DINP and DINN, and exports signal DOP1 and DON1 complimentary to one another after reducing duty ratio.
Figure 22 illustrates the block diagram that data duty cycle increases the layout of circuit 405.Data duty cycle increases circuit 405 and comprises buffer 4050,4054 and 4055, emitter follower circuit 4051 and 4056 and capacitor 4052 and 4053.Buffer 4050,4054 and 4055 has the layout identical with buffer shown in Figure 20 4040.Emitter follower circuit 4051 and 4056 has the layout identical with emitter follower circuit shown in Figure 21 4041.
Use above-mentioned layout, data duty cycle increase circuit 405 increases from data duty cycle according to correction signal SCO and reduces the output DOP1 of circuit 404 and the duty ratio of DON1, and the data DCP of output calibration and DCN.
Industrial applicibility
The present invention can be applicable to from the input data recovered clock and based on this clock identification input The technology of data.
Claims (14)
1, a kind of clock/data recovery circuit comprises:
The data duty cycle correcting circuit is proofreaied and correct the duty ratio of input data by the level according to correction signal, comes the data of output calibration;
Clock recovery circuitry, the clock recovered that generation is regularly synchronous with the edge of the data of described correction;
The data decision circuit comes the data of described correction are carried out data decision based on described clock recovered; And
The data duty cycle testing circuit detects the duty ratio of the data of described correction based on described clock recovered, and represents the correction signal of duty cycle correction amount to described data duty cycle correcting circuit output.
2, clock/data recovery circuit according to claim 1 also comprises:
The A/D change-over circuit that provides between described data duty cycle testing circuit and described data duty cycle correcting circuit is used for the correction signal from described data duty cycle testing circuit output is converted to digital signal; And
Between described data duty cycle testing circuit and described data duty cycle correcting circuit, provide D/A change-over circuit, be used for the output of described A/D change-over circuit is converted to analog signal, and export described analog signal to described data duty cycle correcting circuit.
3, clock/data recovery circuit according to claim 1, wherein, described clock recovery circuitry comprises:
Gating circuit detects the edge of the data of described correction; And
VCO circuit by gate produces described clock recovered, and described clock recovered is come synchronously by the edge detection signal from described gating circuit output.
4, clock/data recovery circuit according to claim 1, wherein, described data duty cycle testing circuit comprises:
Flip-flop circuit receives described clock recovered via data input pin, and receives the reverse signal of the data of described correction via input end of clock; And
Low pass filter receives the output of described flip-flop circuit, and exports described correction signal.
5, clock/data recovery circuit according to claim 1, wherein, described data duty cycle correcting circuit comprises:
Integrating circuit carries out integration to described input data; And
Threshold circuit uses described correction signal to determine the output of described integrating circuit as threshold value, and exports the data of described correction.
6, clock/data recovery circuit according to claim 1, wherein, described data duty cycle correcting circuit comprises:
Data duty cycle reduces circuit, reduces the duty ratio of described input data; And
Data duty cycle increases circuit, increases the duty ratio that described data duty cycle reduces the output of circuit according to described correction signal, and exports the data of described correction.
7, clock/data recovery circuit according to claim 1, wherein, described data duty cycle testing circuit comprises: the data and the described clock recovered that are used to receive described correction, and the device of output calibration signal just when the transformation of data of described correction only, described correction signal represent described correction data duty ratio and 100% poor.
8, clock/data recovery circuit according to claim 7, wherein, represent that the duty ratio of data of described correction and the described correction signal of 100% difference are pulse signals, described pulse signal have by to/from adding/deduct the time width that the corresponding time of difference with the duty ratio of the data of described correction and 100% obtains with the corresponding unit interval of 100% duty ratio.
9, clock/data recovery circuit according to claim 7, wherein, described data duty cycle testing circuit comprises:
First flip-flop circuit receives the data of described correction in response to described clock recovered; And
First logical circuit, when the transformation of data of described correction, come output signal based on the data of described correction and the output signal of described first flip-flop circuit, the signal of being exported have by to/from adding/deduct the duty ratio of data of described correction and the time width that the difference of described unit interval obtains with the corresponding unit interval of 100% duty ratio.
10, clock/data recovery circuit according to claim 9, wherein, described data duty cycle testing circuit comprises:
Second flip-flop circuit in response to the counter-rotating clock of described clock recovered, receives the output signal of described first flip-flop circuit; And
Second logical circuit, only when the transformation of data of described correction, just based on the output signal of described first flip-flop circuit and the output signal of described second flip-flop circuit, output has the signal with described corresponding pulse duration of unit interval.
11, clock/data recovery circuit according to claim 9, wherein, described first logical circuit comprises:
First XOR circuit is carried out XOR to the data of described correction and the output signal of described first flip-flop circuit; And
First and circuit, the output signal of described first XOR circuit and the output signal of described first flip-flop circuit are carried out and operation.
12, clock/data recovery circuit according to claim 10, wherein, described second logical circuit comprises:
Second XOR circuit is carried out XOR to the output of described first flip-flop circuit and the output of described second flip-flop circuit; And
Second and circuit, the output signal of described second XOR circuit and the output signal of described second flip-flop circuit are carried out and operation.
13, clock/data recovery circuit according to claim 9, wherein, described first logical circuit comprises: the 3rd and circuit, the reverse signal of the data of described correction and the output signal of described first flip-flop circuit are carried out and operation.
14, clock/data recovery circuit according to claim 10, wherein, described second logical circuit comprises: the 4th and circuit, the reverse signal of the output signal of described first flip-flop circuit and the output signal of described second flip-flop circuit are carried out and operation.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP061298/2007 | 2007-03-12 | ||
| JP2007061298A JP4731511B2 (en) | 2007-03-12 | 2007-03-12 | Clock data recovery method and circuit |
| JP2007075749A JP5093838B2 (en) | 2007-03-23 | 2007-03-23 | Duty detection circuit |
| JP075749/2007 | 2007-03-23 | ||
| PCT/JP2007/064338 WO2008111241A1 (en) | 2007-03-12 | 2007-07-20 | Clock/data recovery circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101606349A true CN101606349A (en) | 2009-12-16 |
| CN101606349B CN101606349B (en) | 2013-04-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200780051221.XA Expired - Fee Related CN101606349B (en) | 2007-03-12 | 2007-07-20 | Clock/data recovery circuit |
Country Status (2)
| Country | Link |
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| JP (1) | JP4731511B2 (en) |
| CN (1) | CN101606349B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5397025B2 (en) * | 2009-06-02 | 2014-01-22 | ソニー株式会社 | Clock reproduction device and electronic device |
| JP5672931B2 (en) * | 2010-10-13 | 2015-02-18 | 富士通株式会社 | Clock recovery circuit and clock data recovery circuit |
| WO2012105334A1 (en) | 2011-01-31 | 2012-08-09 | 日本電信電話株式会社 | Signal multiplexing device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0910192A2 (en) * | 1997-10-16 | 1999-04-21 | Fujitsu Limited | Clock extraction circuit |
| US6121805A (en) * | 1998-10-08 | 2000-09-19 | Exar Corporation | Universal duty cycle adjustment circuit |
| US20040046596A1 (en) * | 2002-09-10 | 2004-03-11 | Nec Corporation | Clock recovery circuit and electronic device using a clock recovery circuit |
| US20050031065A1 (en) * | 2003-08-06 | 2005-02-10 | Gupta Atul K. | System and method for automatically correcting duty cycle distortion |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0923247A (en) * | 1995-07-04 | 1997-01-21 | Sony Corp | Signal slice circuit |
| JP4106646B2 (en) * | 2001-03-13 | 2008-06-25 | 日本ビクター株式会社 | Digital signal reproduction device |
-
2007
- 2007-03-12 JP JP2007061298A patent/JP4731511B2/en active Active
- 2007-07-20 CN CN200780051221.XA patent/CN101606349B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0910192A2 (en) * | 1997-10-16 | 1999-04-21 | Fujitsu Limited | Clock extraction circuit |
| US6121805A (en) * | 1998-10-08 | 2000-09-19 | Exar Corporation | Universal duty cycle adjustment circuit |
| US20040046596A1 (en) * | 2002-09-10 | 2004-03-11 | Nec Corporation | Clock recovery circuit and electronic device using a clock recovery circuit |
| US20050031065A1 (en) * | 2003-08-06 | 2005-02-10 | Gupta Atul K. | System and method for automatically correcting duty cycle distortion |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101606349B (en) | 2013-04-17 |
| JP2008227786A (en) | 2008-09-25 |
| JP4731511B2 (en) | 2011-07-27 |
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