JP2006333262A - Clock recovery circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock recovery circuit which is simple in its circuit configuration, and reproduces a clock immediately after data is received even at a high transmission rate of data. <P>SOLUTION: The clock recovery circuit 100 has: a pulse signal generation circuit 1 for detecting a transition of reception data to generate a pulse signal; a delay element group 2 in which a plurality of delay elements corresponding to a number which subtracts one from the number of a maximum non-transition period of the reception data are series-connected; a delay time control circuit 3 which is controlled according to a delay time control signal so as to make delay times of the respective delay elements of the delay element group 2 equal to 1 data period portion of the reception data, on the basis of a preset transmission rate of the reception data; a delay pulse signal generation circuit 4 which inputs the pulse signal to the delay element group 2 and outputs a plurality of delay pulse signals which are delayed sequentially by one data period portion of the reception data; and an OR circuit 5 which makes a logical adding of the pulse signal and the plurality of delay pulse signals and outputs it as a reproduced clock signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a clock recovery circuit that recovers a clock from received data.

  In high-speed serial transmission, synchronization between the transmission side and the reception side is very important for correctly transmitting data. As a method for achieving this synchronization, a clock data recovery method is often used at a transmission rate exceeding 1 Gbs.

  In the clock data recovery method, when data transmitted from the transmission side is received on the reception side, a clock for reading data is reproduced from the received data on the reception side. Such reproduction from the received data is called clock recovery, and a circuit for that purpose is called a clock recovery circuit.

  The clock recovery circuit regenerates the clock based on the transition information of the received data. Therefore, it is desirable that sufficient transition information is given from the received data to the clock recovery circuit. Therefore, when serial data transmission is performed by the clock data recovery method, an effort has been made so that the period of no data transition does not become long in encoding of transmission data. One of them is the 8B10B encoding method.

  The 8B10B encoding method encodes 8-bit data into 10-bit data by adding 12 special characters to 8-bit data, so that the continuation of bits of the same value is 5 at the maximum. This is a devised coding method. That is, in the 8B10B encoding method, the period without data transition is a maximum of 5 data periods.

  Conventionally, a PLL (Phase Locked Loop) that corrects the phase error and the frequency error of the recovered clock by feeding back the phase relationship between the received data and the recovered clock is often used for the clock recovery circuit. However, when the PLL is used, there is a problem that it takes time until the recovered clock is stabilized, and it takes time until synchronization with the transmission side is started after data is received. In view of this, a clock recovery circuit that uses a synchronous delay circuit to synchronize the recovered clock in a short time without using a PLL has been proposed (see, for example, Patent Document 1).

However, the proposed synchronous delay circuit has a delay circuit composed of multi-stage gate circuits, and the delay time can be adjusted only stepwise, and the minimum delay time unit is considered to be large. Therefore, when further improvement in transmission speed is required in the future, it is expected that the request cannot be sufficiently met.
Japanese Patent Laid-Open No. 11-68729 (page 3, FIG. 2)

  SUMMARY OF THE INVENTION An object of the present invention is to provide a clock recovery circuit that has a simple circuit configuration and can regenerate a clock immediately after data reception even if the data transmission rate is high.

  According to one aspect of the present invention, a pulse signal generation circuit that generates a pulse signal by detecting a transition of received data that is transmitted at a preset transmission rate and has a non-transition period defined as a maximum N data period A delay element group in which (N−1) delay elements whose delay times are controlled by a delay time control signal are connected in series, and the delay time of the delay elements based on the preset transmission rate A delay time control circuit that outputs the delay time control signal that controls the received data to be one data period; and the pulse signal is input to the delay element group, and the pulse signal is set to 1 of the received data. A delay pulse signal generation circuit for outputting (N−1) delay pulse signals sequentially delayed by a data period one by one from the (N−1) delay elements of the delay element group; The clock recovery circuit, characterized by comprising a logic OR circuit which takes the logical sum of the signal and the (N-1) number of delay pulse signal.

  According to the present invention, the number of delay elements whose delay time is controlled to one data period of received data based on a preset data transmission rate is one less than the maximum number of periods without data transition. Since the recovered clock can be generated, the circuit configuration is simple, and the clock is generated from the data transition. Therefore, even if the data transmission speed is high, the clock that can always read the data is set immediately after receiving the data. Can be played.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a circuit diagram showing an example of the configuration of a clock recovery circuit according to an embodiment of the present invention. Here, the reception data input to the clock recovery circuit of the present embodiment has a data transmission speed set in advance with the transmission side, and the transmission side encodes the transmission data using the 8B10B encoding method. It is assumed that the maximum non-transition period (N) of data is 5 data periods.

  The clock recovery circuit 100 according to this embodiment includes a pulse signal generation circuit 1 that detects a transition of received data and generates a pulse signal, and four delay elements 21 and 22 whose delay times are controlled by a delay time control signal. , 23, 24 connected in series, delay time control circuit 3 for outputting a delay time control signal for controlling the delay time of delay elements 2122, 23, 24, and pulse signal generating circuit 1 A pulse signal is input to the delay element group 2, from the output of the delay element 21 to the delay pulse signal 1, from the output of the delay element 22 to the delay pulse signal 2, from the output of the delay element 23 to the delay pulse signal 3 and from the output of the delay element 24. Delay pulse signal generation circuit 4 that outputs delayed pulse signal 4 and pulse signal output from pulse signal generation circuit 1 and output from delay pulse signal generation circuit 4 Enter the extension pulse signal 1-4, and an OR circuit 4 for outputting the logical sum output as a reproduction clock signal.

  Here, in the present embodiment, the number of delay elements included in the delay element group 2 is 4, but the number n of delay elements is determined as n = N−1 from the value of the maximum no-transition period N of received data. It is what is done. In this embodiment, since data of the 8B10B encoding method with N = 5 is received, n = 5-1 = 4.

  FIG. 2 is a circuit diagram showing an example of the configuration of the pulse signal generation circuit 1.

  The pulse signal generation circuit 1 includes a delay circuit 11 that delays received data, and an exclusive OR circuit 12 that receives the received data and the output of the delay circuit 11.

  FIG. 3 is an operation waveform diagram showing an example of the operation of the pulse signal generation circuit 1 shown in FIG.

  The exclusive OR circuit 12 takes an exclusive OR of the received data and a signal obtained by delaying the received data by the delay circuit 11. Therefore, the output of the exclusive OR circuit 12 has a waveform that outputs logic “1” by the delay of the delay circuit 11 from the transition end of the received data. In other words, the exclusive OR circuit 12 detects the transition of the received data and outputs a pulse signal having a pulse width corresponding to the delay of the delay circuit 11 from the transition end.

  Here, the delay width of the delay circuit 11 is determined based on the value of the minimum pulse width necessary for the operation of the circuit that operates by receiving the recovered clock signal output from the clock recovery circuit 100.

  FIG. 4 is a circuit diagram showing an example of the configuration of the delay time control circuit 3 shown in FIG. Here, an example in which a delay time control voltage is output as the delay time control signal is shown. In FIG. 4, the number of delay elements connected in series to the oscillator 31 is two, but the number of delay elements is determined in conjunction with the oscillation period of the oscillator 31 as will be described later. It is not fixed to two.

  The delay time control circuit 3 includes an oscillator 31, a delay element 32 to which an output signal of the oscillator 31 is input, a delay element 33 connected in series to the delay element 32, a phase of the output signal of the oscillator 31, and the delay element 32. , 33 for comparing the phase of the output signal of the oscillator 31 delayed by the phase comparator 34, and the output signal of the oscillator 31 delayed by the delay elements 32, 33 based on the result of the phase comparison by the phase comparator 34 The delay time control voltage adjustment circuit 35 adjusts the value of the delay time control voltage that controls the delay time of the delay elements 32 and 33 so that the phase of the output signal of the oscillator 31 matches the phase of the output signal of the oscillator 31.

Here, the oscillation period of the oscillator 31 is set to be ^2m times (m is a positive integer) one data period of the received data. Further, the number of serially connected delay elements that delay the phase of the output signal of the oscillator 31 in association with the oscillation period of the oscillator 31 is 2 ^m .

  FIG. 4 shows an example when m = 1. In this case, if one data period of the received data is T, the oscillation period of the oscillator 31 is 2T, and the number of delay elements is two.

  FIG. 5 shows a specific configuration example of the delay element whose delay time is controlled by the control voltage. Delay elements as shown in FIG. 5 are used as the delay elements 32 and 33. When delay elements are used in FIG. 5 as the delay elements 32 and 33, the delay elements are also used in FIG. 5 as the delay elements 21, 22, 23, and 24 shown in FIG. That is, the delay element used in the delay time control circuit 3 and the delay element used in the delay pulse signal generation circuit 4 have the same delay characteristics with respect to the delay time control signal.

  The delay element shown in FIG. 5 includes a driver 3A having a voltage-controlled variable capacitor C as a load. The capacity of the voltage control type variable capacitor C varies depending on the magnitude of the delay time control voltage. As the capacitance of the voltage-controlled variable capacitor C, which is a load, changes, the time required for the output of the driver 3A that drives this load changes. That is, the output delay time of the driver 3A can be controlled by the delay time control voltage.

  FIG. 6 is a waveform diagram showing how the delay time control circuit 3 shown in FIG. 4 operates. If one data period of the received data is T, the oscillation period of the oscillator 31 is set to 2T.

  A phase comparator 34 compares the phase of the output of the oscillator 31 and the phase of the signal obtained by delaying the output of the oscillator 31 by the delay elements 32 and 33. In response to the comparison result of the phase comparator 34, the delay time control voltage adjustment circuit 35 delays the delay element 32 so that the phase of the signal delayed by the delay elements 32 and 33 matches the phase of the output of the oscillator 31. , 33 is adjusted.

  When the delay times of the delay elements 32 and 33 respectively become T, the phase delay of the output signal of the delay element 33 with respect to the output of the oscillator 31 becomes 2T, and the output of the oscillator 31 delayed by the delay elements 32 and 33 is The phase coincides with the phase of the output of the oscillator 31.

  Therefore, in this state, the value of the delay time control voltage output from the delay time control voltage adjustment circuit 35 is stabilized. That is, the delay times of the delay elements 32 and 33 are controlled to T by the delay time control voltage output from the delay time control voltage adjustment circuit 35 at this time.

  Therefore, when delay elements having the same delay characteristics as the delay elements 32 and 33 are used for the delay elements 21, 22, 23 and 24 shown in FIG. 1, the delay time control voltage output from the delay time control voltage adjustment circuit 35 The delay times of the delay elements 21, 22, 23, and 24 are also controlled to T.

  FIG. 6 is a waveform diagram showing how the clock recovery circuit 100 operates when the delay time of the delay elements 21, 22, 23, 24 is controlled to T. In FIG. Here, the operation when the no-transition period of the received data is the maximum five data periods is shown.

  A pulse signal is output from the pulse signal generation circuit 1 at the transition edge of the received data. The pulse signals are sequentially delayed by T by delay elements 21, 22, 23, and 24 each having a delay time T, and are delayed as a delay pulse signal 1, a delay pulse signal 2, a delay pulse signal 3, and a delay pulse signal 4. Output from the pulse signal generation circuit 4.

  The pulse signal output from the pulse signal generation circuit 1 and the delay pulse signal 1, the delay pulse signal 2, the delay pulse signal 3, and the delay pulse signal 4 output from the delay pulse signal generation circuit 4 are input to the OR circuit 5. And the logical sum is taken.

  As a result, the OR circuit 5 outputs a pulse train in which the pulse signal from the pulse signal generation circuit 1 and four pulse signals obtained by delaying the pulse signal by T are arranged at T intervals. As a result, the maximum non-transition period of the received data is filled with pulse signals arranged in a T cycle of one data period. Then, it continues to the next pulse signal output from the pulse signal generation circuit 1 at the next transition end of the received data.

  In this way, a continuous pulse signal with a period T can be obtained from the OR circuit 5, and the output of the OR circuit 5 becomes the reproduced clock signal output of the clock recovery circuit 100.

  As described above, the period T of the recovered clock signal output from the clock recovery circuit 100 according to the present embodiment is determined by the delay time T of the delay elements 21 to 24. The delay time T of the delay elements 21 to 24 is controlled by a delay time control signal output from the delay time control circuit 3. The delay time control circuit 3 uses the output of the oscillator 31 to generate a delay time control signal. Therefore, if the oscillation of the oscillator 31 is started before the data reception is started, the delay output from the delay time control circuit 3 so that the delay time of the delay elements 21 to 24 is set to T until the data reception start time. The signal value of the time control signal can be determined. As a result, the recovered clock signal can be output as soon as data is input, and operations such as receiving data using this recovered clock can be started immediately.

  The conventional clock recovery circuit starts an operation of determining the delay time of the delay element after data is input. In contrast, the clock recovery circuit 100 of this embodiment determines the delay time of the delay element before data is input. Therefore, as compared with the conventional clock recovery circuit, the clock recovery circuit 100 according to the present embodiment can shorten the time from when data is input until the data can actually be received.

  According to the present embodiment as described above, by using one delay element that is one simpler than the number of data periods in the maximum no-transition period of the received data and that can easily control the delay time extension. A reproduction clock can be generated. Further, by changing the oscillation frequency of the oscillator used in the delay time control circuit in accordance with the transmission speed, it is possible to generate a reproduction clock corresponding to the transmission speed even when the transmission speed becomes high. In addition, since the reproduction clock can be output immediately after the data is input, the time from when the data is input until the data can be received can be shortened.

The circuit diagram which shows the example of a structure of the clock recovery circuit based on the Example of this invention. FIG. 2 is a circuit diagram illustrating an example of a configuration of a pulse signal generation circuit illustrated in FIG. 1. FIG. 3 is a waveform diagram showing an example of the operation of the pulse signal generation circuit shown in FIG. 2. FIG. 2 is a circuit diagram showing an example of a configuration of a delay time control circuit shown in FIG. 1. The circuit diagram which shows the example of a structure of the delay element in the Example of this invention. FIG. 5 is a waveform diagram showing an example of operation of the delay time control circuit shown in FIG. 4. The wave form diagram which shows the example of operation | movement of the clock recovery circuit based on the Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Pulse signal generation circuit 2 Delay element group 3 Delay time control circuit 4 Delay pulse signal generation circuit 5 OR circuit 11 Delay circuit 12 Exclusive OR circuit 21, 22, 23, 24, 32, 33 Delay element 31 Oscillator 34 Phase Comparator 35 Delay time control voltage adjustment circuit 3A Driver C Voltage control type variable capacity 100 Clock recovery circuit

Claims (4)

A pulse signal generation circuit that generates a pulse signal by detecting a transition of received data that is transmitted at a preset transmission rate and has a no-transition period defined as a maximum N data period;
A delay element group in which (N−1) delay elements whose delay times are controlled by a delay time control signal are connected in series;
A delay time control circuit that outputs the delay time control signal for controlling the delay time of the delay element to be one data period of the received data based on the preset transmission rate;
The pulse signal is input to the delay element group, and (N−1) delayed pulse signals obtained by sequentially delaying the pulse signal by one data period of the received data are the (N−1) delay pulse groups. ) Delay pulse signal generation circuit that outputs one by one from each delay element;
A clock recovery circuit comprising: a logical sum circuit that takes a logical sum of the pulse signal and the (N-1) delayed pulse signals.   2. The clock recovery circuit according to claim 1, wherein the delay element is a voltage control type delay element, and the delay time control signal output from the delay time control circuit is a delay time control voltage. The delay time control circuit includes:
An oscillator that oscillates at a period of 2 ^m times (m is a positive integer) of one data period of the received data;
2 ^m voltage-controlled delay elements connected in series, to which an output signal of the oscillator is input and whose delay time is controlled by the delay time control voltage;
A phase comparator that compares the phase of the output signal of the oscillator with the phase of the output signal of the oscillator delayed by the 2 ^m voltage-controlled delay elements;
Based on the result of the phase comparison by the phase comparator, the delay is performed so that the phase of the output signal of the oscillator delayed by the 2 ^m voltage controlled delay elements matches the phase of the output signal of the oscillator. The clock recovery circuit according to claim 2, further comprising a delay time control voltage adjustment circuit that adjusts a value of the time control voltage. The oscillator starts oscillating before the reception data is received, and when the data is received, the delay time control voltage is set so that the delay time of the voltage controlled delay element is one data period of the reception data. 4. The clock recovery circuit according to claim 3, wherein the clock recovery circuit is adjusted.

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