JP4014164B2 - Pulse regeneration circuit - Google Patents

Description

  The present invention relates to a pulse regeneration circuit, and more particularly to a pulse regeneration circuit that regenerates a pulse synchronized with a reception side clock in a system in which a transmission clock frequency and a reception clock frequency do not exactly match.

  In the conventional logic value judgment of high-speed signals for data transmission, the clock component is extracted from the input data and the clock is shaped from the accuracy of the logic value judgment, and the clock synchronized with the data is input to the input data. A method is used in which the data is output in parallel.

This conventional method will be described with reference to FIG. FIG. 9 shows a conventional PLL (Phase
1 is a diagram illustrating a configuration example of a clock extraction type bit synchronization circuit using (Locked Loop) (Non-Patent Document 1). In this type of bit synchronization circuit, first, the clock component extraction circuit 101 extracts the clock component from the input data string p, and the phase comparator 102 extracts the extracted clock and the voltage controlled oscillator (VCO). (Voltage
Control Ocillator) 104 performs phase comparison with clock q output. When the phase comparator 102 outputs the phase difference signal of both clocks, the low pass filter 103 removes the high frequency component from the phase difference signal and inputs the low frequency component to the voltage controlled oscillator 104 again. At this time, the control signal, which is a low frequency component output from the low pass filter 103, works so as to match the frequencies of the two.

  In this way, the clock q output from the voltage controlled oscillator 104 is locked to a clock synchronized with the clock component of the input data p while following the loop constituting the feedback circuit. A clock q synchronized with p can be output.

  Therefore, the D flip-flop (D-type Flip Flop) 105 determines the input data p using the synchronized clock q. At this time, since the phase relationship between the input data p and the discrimination clock q is constantly in an ideal state, ideal discrimination becomes possible.

By the way, apart from the PLL system described above, there is a memory method in which transmission data once transmitted is temporarily stored on the receiving side using a memory function, and written again using a clock on the receiving side.
http://www.maxim-ic.com/appnotes.cfm/appnote_number/1973/ln/jp “Use of high-precision reference clock in clock data recovery circuit”

  However, in the PLL system, it is necessary to use a relatively large size component that becomes a problem in the case of LSI, such as a voltage controlled oscillator or a low-pass filter. Therefore, in the PLL system, the circuit scale is increased, and a voltage-controlled oscillator needs to be custom-made for each frequency band to be used, which hinders simplification of design.

  In addition, since a method using a memory requires a large amount of buffer for each frame required by a transmission method to be used, even if it is made into an LSI, it has hindered miniaturization and cost reduction.

  An object of the present invention is to solve the above-described problems and provide a pulse regeneration circuit that can be realized in a small size, a simple configuration, and at a low cost.

In order to solve the above problems, the invention of claim 1 uses an RZ signal having a signal duty ratio α% (α <100) as an input signal, and reads and writes the input signal with a clock having a faster rate than the input signal. A first D flip-flop that performs the following operations: an RS flip-flop that uses a signal written by the first D flip-flop as a set input and a delay signal as a reset input; the first D flip-flop; A delay circuit that delays the rising edge of the input signal through the RS flip-flop with the clock according to the signal duty ratio to generate the delayed signal, and inputs the delayed signal to the RS flip-flop; And having the output of the RS flip-flop or the output of the delay circuit as a reproduction signal, the pulse reproduction of the input signal This is a pulse regeneration circuit characterized in that
According to a second aspect of the present invention, the delay circuit is composed of second and third D flip-flops, and the second and third D flip-flops read out with a clock having the same rate as that of the first D flip-flop. The output of the RS flip-flop is used as the input signal of the second D flip-flop, the output of the second D flip-flop is used as the input signal of the third D flip-flop, and the third flip-flop is used. 2. The pulse regeneration circuit according to claim 1, wherein an output of the D flip-flop is used as a reset input of the RS flip-flop .
According to a third aspect of the present invention, there is provided a D flip-flop which takes an RZ signal having a signal duty ratio α% (α <100) as an input signal and reads and writes the input signal with a clock having a faster rate than the input signal. A T flip-flop that inputs a clock used in the D flip-flop; and an AND circuit that receives the output of the T flip-flop and the output of the D flip-flop as input signals. The pulse reproduction circuit is characterized in that the reproduction signal is a result of pulse reproduction of the input signal.

  According to the present invention, when the input signal is an RZ signal having a signal duty ratio α%, the RS flip-flop is set at the rising edge of the input signal. On the other hand, the rising edge of the input signal is delayed by a clock corresponding to the signal duty ratio, and the RS flip-flop is reset by the delayed rising signal. As a result, even if the latch result of the D flip-flop fluctuates, the final reproduction signal pulse can always be reproduced with a constant width. In addition, the reproduction signal can be synchronized with the clock. Furthermore, since a voltage controlled oscillator and a buffer are not required, the design can be simplified, reduced in size, and reduced in cost.

  Further, according to the present invention, the input signal is read and written with a clock having a faster rate than the input signal. On the other hand, this clock is divided, and thereafter, a logical product of these two signals is calculated to generate a reproduction signal. As a result, even if the latch result of the D flip-flop fluctuates, the final reproduction signal pulse can always be reproduced with a constant width. In addition, the reproduction signal can be synchronized with the clock. Furthermore, since a voltage controlled oscillator and a buffer are not required, the design can be simplified, reduced in size, and reduced in cost.

  Furthermore, this signal can be reproduced as an analog audio signal by passing the RZ signal of the reproduction signal through the low-pass filter. At this time, for example, if the rate of the input signal and the clock is adjusted so that the beat component in the analog audio signal is outside the audible band of about 20 KHz, the audio signal including no beat noise can be reproduced. .

Next, an embodiment of the present invention will be described.
[Embodiment 1]
The pulse regeneration circuit according to this embodiment is shown in FIG. The pulse regeneration circuit of FIG. 1 includes D flip-flops (D-type Flip Flop) 1, 3, and 4, RS flip-flop (Reset Set Flip Flop) 2, input terminals 5A and 5B, and an output terminal 5C. ing. In the present embodiment, the D flip-flops 3 and 4 constitute a D flip-flop group.

Input terminals 5A are data (hereinafter, referred to as the input data D _in) is the input of the input terminal 5B is for input of the clock pulse CK. The output terminal 5C is for outputting reproduction data. Each of the D flip-flops 1, 3, and 4 includes an input D terminal, an output Q terminal, and a clock pulse CK C terminal. The RS flip-flop 2 is composed of NOR gates 2A and 2B. One input terminal of the NOR gate 2A is an S terminal (set terminal), and the other input terminal of the NOR gate 2B is an R terminal (reset terminal). The output terminal of the NOR gate 2B is the Q terminal.

  The input terminal 5 A is connected to the D terminal of the D flip-flop 1, and the input terminal 5 B is connected to the C terminals of the D flip-flops 1, 3 and 4. The Q terminal of the D flip-flop 1 is connected to the S terminal of the RS flip-flop 2, and the Q terminal of the D flip-flop 4 is connected to the R terminal of the RS flip-flop 2. The Q terminal of the RS flip-flop 2 is connected to the D terminal of the D flip-flop 3. The Q terminal of the D flip-flop 3 is connected to the D terminal of the D flip-flop 4. The output terminal 5 </ b> C is connected to the Q terminal of the RS flip-flop 2.

The above is the configuration of the pulse regeneration circuit according to the present embodiment. Before describing the operation of this circuit, the input data format to be handled will be described. Input data D _in the input terminal 5A is a RZ signal (Return-to-Zero signal). As shown in FIG. 2, the duty ratio of the RZ signal is defined by comparing the NRZ signal (Non-Return-to-Zero signal) with a duty ratio of 100 [%]. FIG. 2 shows an RZ signal with a duty ratio of 50 [%] and an RZ signal with a duty ratio of 25 [%].

  In order to make the essence of the circuit operation according to the present embodiment easy to understand, a comparison target will be described with reference to FIG. FIG. 3 shows a circuit when a pulse is regenerated by the D flip-flop 1 without using the present invention. In FIG. 3, the same reference numerals are assigned to components that are considered to be the same as or the same as those in FIG. 1 described above. The circuit shown in FIG. 3 uses a D flip-flop 1, and the D terminal of the D flip-flop 1 is connected to the input terminal 5A, and the C terminal is connected to the input terminal 5B. The Q terminal of the D flip-flop 1 is connected to the output terminal 5C.

In the circuit of Figure 3, as shown in FIG. 4, the rate of the input data D _in, if where the rate of the clock pulse CK is not closely matched, with the edge of the edge and the clock pulse CK of the input data D _in Where the overlap is delicate, the reproduction data D _out can take different expected values such as the reproduction data D _out ′. As a result, the output is not constant, phase fluctuation (jitter) in the time axis direction occurs, and this phase fluctuation makes the circuit operation unstable.

Next, the operation of the present invention will be described. As described in the previous Figures 3 and 4, if the rate of the input data D _in and the clock pulse CK is not strictly match, fluctuates the pulse width output from the Q terminal of the D flip-flop 1 However, according to the present embodiment, the pulse width can be made constant by the following operation. This will be described with reference to FIG. FIG. 5 is a time chart showing the operation of the main part of the pulse regeneration circuit (FIG. 1) according to the present embodiment. Here, as the input data D _in is the input signal, indicating the case of inputting a duty of 25% RZ signal.

In the present embodiment, an example of the RS flip-flop 2 assembled by NOR gates 2A and 2B is shown. By connecting the RS flip-flop 2 and the two-stage D flip-flops 3 and 4, when the Q terminal of the D flip-flop 1 becomes “H (1)” level as shown in the time chart, the RS flip-flop at the rising edge of the second S terminal, the rising of the reproduction data D _out is, as shown in the following Table 1, to confirm the set (set), the reproduction data D _out becomes "H" level. Table 1 is a truth table of the RS flip-flop 2 for supplementing the understanding of the description.

Table 1

On the other hand, the “H” level determined by the set of the RS flip-flop 2 is maintained by 2 CLK cycles (clock cycles) of the clock pulse CK by the two-stage D flip-flops 3 and 4. The reason why the “H” level cannot be maintained after 2 CLK cycles is as follows. That is, the value of the S terminal at the position where 2 CLK cycle time has elapsed from the rising edge of the S terminal of the RS flip-flop 2 is the “L (0)” level. This is because the level is “L” due to the characteristics of the RZ signal with a duty of 25%. At this time, its own rising edge delayed by 2 CLK cycles of the S terminal of the RS flip-flop 2 by the D flip-flops 3 and 4 is input from the D flip-flop 4 to the R terminal of the RS flip-flop 2 as a delay signal. . For this reason, as shown in Table 1, the state of the RS flip-flop 2 changes at this point, and the value of the reproduction data _Dout immediately changes to the “L” level.

By repeating this operation, D flip-flop 1 of the latch result, even with fluctuation (jitter) as the reproduced data D _out and 4 reproduction data D _out ', the final reproduced data D _out pulses The width can always be reproduced with a constant width. In addition, it can be synchronized with the clock pulse CK on the receiving side. Furthermore, according to the present embodiment, since the voltage controlled oscillator and the buffer are unnecessary, the design can be simplified, the size can be reduced, and the cost can be reduced.

  In the present embodiment, an example in which the data duty ratio and speed and the clock speed have certain values has been described, but pulse reproduction can be performed in the same way with other combinations.

[Embodiment 2]
A pulse regeneration circuit according to the present embodiment is shown in FIG. The pulse regeneration circuit in FIG. 6 includes a D flip-flop 11, an AND gate 12, a T flip-flop 13, input terminals 14A and 14B, and an output terminal 14C.

Input terminal 14A is for the input of the input data D _in, input terminal 14B is for the input of the clock pulse CK. The output terminal 14C is an output of the reproduction data D _out. The D flip-flop 11 includes an input D terminal, an output Q terminal, and a clock pulse CK C terminal. The T flip-flop 13 has a T terminal for input and a Q terminal for output.

  The input terminal 14 A is connected to the D terminal of the D flip-flop 11, and the input terminal 14 B is connected to the C terminal of the D flip-flop 11 and the T terminal of the T flip-flop 13. The Q terminals of the D flip-flop 11 and the T flip-flop 13 are respectively connected to the input side of the AND gate 12, and the output side of the AND gate 12 is connected to the output terminal 14C.

The above is the configuration of the pulse regeneration circuit according to the present embodiment. As shown in FIG. 7, if the rate of the input data D _in and the clock pulse CK is not strictly match, as described in Embodiment 1, data output from the Q terminal of the D flip-flop 11, As shown in data A and data A ′, there is fluctuation. In the present embodiment, the data B output from the Q terminal of the T flip-flop 13 by the operation of the T flip-flop 13 is a half-divided waveform of the clock pulse CK. Since this data B always appears, the pulse width of the data A output from the D flip-flop 11 is always made wider than the pulse width of the data B, and the AND ( Logical product). As a result, as shown in the reproduction data _Dout , the pulse width can always be made narrower. For this purpose, it is sufficient to set a high rate of clock pulses CK than the rate of the input data D _in.

Thus, according to the present embodiment, as in the first embodiment, the final reproduction data D _out can be obtained even if there is a fluctuation (jitter) like the reproduction data D _out and reproduction data D _out ′ in FIG. Can be reproduced with a constant pulse width. In addition, it can be synchronized with the clock pulse CK on the receiving side.

[Embodiment 3]
A pulse regeneration circuit according to this embodiment is shown in FIG. In FIG. 8, components that are the same as or the same as those in FIG. 1 described above are denoted by the same reference numerals, and description thereof is omitted. In the present embodiment, a low pass filter 21 is provided between the Q terminal of the RS flip-flop 2 of FIG. 1 and the output terminal 5C. That is, the output signal S _out is limited by restricting the passage of the signal component outside the audio band of the reproduction data D _out output from the Q terminal of the RS flip-flop 2.

In the present embodiment, the RZ signal as the input data D _in described in the first embodiment is a signal obtained by digitizing an audio signal (including, by definition, a frequency component up to about 20 KHz audible to a human ear). And RS pulse width of the reproduced data D _out from the Q terminal of the flip-flop 2 is constant, the rate of the relationship between the input data D _in and the clock pulse CK is a clock pulse CK, the absolute and reproduced data D _out There is a possibility that the dynamic phase relationship fluctuates. This may be heard as a beat as an audio signal.

Therefore, in the present embodiment, the reproduction data _Dout is reproduced as an output signal _Sout, that is, an analog audio signal by passing the RZ signal through the low-pass filter 21. In this case, so that the beat component of the aforementioned audible band of approximately 20 KHz, reproduced by adjusting the rate of the input data D _in and the clock pulse CK, the audio signal does not contain a beat noise as the output signal S _out can do.

  The embodiment of the present invention has been described in detail above, but the specific configuration is not limited to this embodiment, and even if there is a design change or the like without departing from the gist of the present invention, the present invention is not limited to this embodiment. included. For example, the low pass filter 21 described in the third embodiment may be added to the second embodiment. The effect in this case is the same as that of the third embodiment.

It is a circuit block diagram which shows the pulse reproduction circuit by Embodiment 1 of this invention. It is a figure explaining the definition of input data. It is a figure explaining the latch by D flip-flop. It is a time chart explaining the operation | movement of FIG. 3 is a time chart for explaining the operation of the pulse regeneration circuit according to the first embodiment. It is a circuit block diagram which shows the pulse reproduction circuit by Embodiment 2 of this invention. 6 is a time chart for explaining the operation of the pulse regeneration circuit according to the second embodiment. It is a circuit block diagram which shows the pulse reproduction circuit by Embodiment 3 of this invention. FIG. 3 is a block diagram illustrating a configuration example of a clock extraction type bit synchronization circuit using a PLL.

Explanation of symbols

1, 3, 4 D flip-flop 2 RS flip-flop 2A, 2B NOR gate 5A, 5B Input terminal 5C Output terminal 11 D flip-flop 12 AND gate 13 T flip-flop 14A, 14B Input terminal 14C Output terminal 21 Low-pass filter

Claims (3)

A first D flip-flop (1) that takes an RZ signal having a signal duty ratio α% (α <100) as an input signal, and reads and writes the input signal at a clock rate faster than the input signal;
Said first and signal the set input exported by D flip-flop (1), an RS flip-flop to reset input of the delay signal (2),
The rising edge of the input signal that has passed through the first D flip-flop (1) and the RS flip-flop (2) is delayed by the clock according to the signal duty ratio to generate the delayed signal, A delay circuit for inputting the delay signal to the RS flip-flop (2),
A pulse reproduction circuit characterized in that the output of the RS flip-flop (2) or the output of the delay circuit is used as a reproduction signal, and the result is a pulse reproduction result of the input signal. The delay circuit is
The second and third D flip-flops (3) and (4) are configured.
The second and third D flip-flops (3), (4) read and write at the same rate clock as the first D flip-flop (1),
The output of the RS flip-flop (2) is used as the input signal of the second D flip-flop (3),
The output of the second D flip-flop (3) is used as the input signal of the third D flip-flop (4),
The pulse regeneration circuit according to claim 1, wherein an output of the third D flip-flop (4) is a reset input of the RS flip-flop (2) . A D flip-flop (11) which takes an RZ signal having a signal duty ratio α% (α <100) as an input signal and reads and writes the input signal at a clock rate faster than the input signal;
A T flip-flop (13) for inputting a clock used in the D flip-flop (11);
An AND circuit (12) having the output of the T flip-flop (13) and the output of the D flip-flop (11) as input signals;
A pulse reproduction circuit characterized in that the output of the AND circuit (12) is used as a reproduction signal to obtain a result of pulse reproduction of the input signal.

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