JPH08102698A - Sliding correlator - Google Patents

Abstract

PURPOSE: To simplify the circuit constitution of a digital type sliding correlator using no VCO. CONSTITUTION: A differentially encoded spread spectrum(SS) received signal is inputted and multiplied by cosωt, sinωt through respective multipliers 20, 21, respective products are A/D converted by A/D converters 25, 26 through LPFs 22, 23 and the A/D conversion outputs are applied to respective correlators 27, 28. The correlators 27, 28 find out correlation with a reference PN code outputted from a PNG 31, their correlation outputs are made a resultant one by the use of a composition circuit 29, the synthesized correlation output is applied to a comparing and control circuit 30, and a clock signal generator 32 and the PNG 31 are controlled by a control signal from the circuit 30. On the other hand, correlation data from the correlators 27, 28 are differentially decoded to select optimum demodulation data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sliding correlator used as a correlation circuit which is an essential part of a receiving section of a spread spectrum communication system, and a spread spectrum communication apparatus using the sliding correlator.

[0002]

[Prior Art] Spread Spectrum Communication
m Communication (hereinafter referred to as SSC) in FIG.
As shown in (a), the pseudo noise code (Pseudo Noise cod
(hereinafter referred to as PN code) is modulated with desired data to be transmitted, and a carrier signal such as a high frequency signal is further modulated with this modulated PN code and transmitted from the antenna.

In FIG. 15A, 1 is data, 2 is a modulator, 3 is a PN code generator (Pseudo Noise code Generato).
r is hereinafter referred to as PNG), 4 is a carrier signal generator, 5 is a modulator, and 6 is an antenna. On the receiving side, FIG.
As shown in (b), the signal is received, a correlator is used to correlate it with a reference PN code, and an autocorrelation spike is generated at the time when both codes match and the waveform is processed. Performs data demodulation. The amplitude of this correlation spike is proportional to the number of coincidences between the data forming the code within one cycle of both codes, but the occurrence of this correlation spike is described in Japanese Patent Publication No. 64-11178. It is written.

In FIG. 15B, 7 is an antenna, 8 is a correlator, 9 is a reference PN code generator, 10 is a data demodulator, and 1 is a reference demodulator.
1 means demodulated data. Thus, the correlator 1
One is the sliding correlator. The sliding correlator receives the received PN code and the reference PN included in the received signal.
To match the code pattern over one cycle of the code,
By changing the code clock frequency of the reference PN code, the state is maintained until the correlation value reaches a predetermined threshold, and when the correlation value between the received PN code and the reference PN code reaches a predetermined threshold, synchronization between both codes is performed. It is determined that the This operation is called initial synchronization. When the initial synchronization is performed, next, the frequency of the reference PN code clock is made to match the received PN code clock, and the synchronization is maintained, which is an operation for maintaining the synchronization obtained between the two codes. This synchronization is maintained by changing the clock frequency of the reference PN code as described above when a synchronization deviation of a predetermined amount or more is detected while monitoring the state of.

FIG. 16 shows a circuit configuration of a delay lock system which is one of the sliding correlators. In the figure,
12, 13 are multipliers, 14 and 15 are envelope detectors, 16
Is a comparator, 17 is a loop filter, 18 is a reference PN code clock oscillator composed of a voltage controlled oscillator (VCO), 1
Reference numeral 9 denotes a PN code generator, 20 denotes a delay circuit, and T denotes a delay time corresponding to one chip of the PN code. In the delay lock method, two reference PN codes PN1 and PN2, which have the same code pattern and one of which is delayed from the other, are used. As a result, as shown in FIGS. 16 and 17, the reference PN codes (PN1, PN2) are used. ) And the correlation functions (correlation outputs 1 and 2) obtained from the received PN code are shifted in time by an amount whose correlation peak value is equal to the delay amount. Therefore, the delay-lock type correlation function is finally extracted from the comparator 16 as a difference (combined correlation function) between the correlation outputs 1 and 2 obtained based on PN1 and PN2, as shown in FIG. The loop filter 17 is a kind of DC amplifier that takes out the DC component of the obtained value of the correlation function.
It is used as a control signal for O18, and at the point where the correlation function output becomes 0 (displayed as a tracking point), the received PN code clock and the reference P
The N code clocks are held synchronously.

[0006]

Conventionally, a sliding correlator as shown in FIG. 16 has been constructed by an analog circuit. However, with the recent development of semiconductor circuit technology, there has been an increasing need to implement a sliding correlator as shown in FIG. 16 with a digital circuit.
The digitization of NCO (Nume (Nume) is theoretically possible.
rical ControlledOscallater) and DDS (Direct Dig
Although it is implemented as an ital Synthesiyer), there is a problem that the data length to be handled must be long (for example, 23 bits), and the digitized VCO actually becomes a very large scale. As a result, the sliding correlator has a large and complicated circuit configuration, which is not practical. The applicant of the present invention discloses a technique for constructing a sliding correlator in a digital type without using this digitized VCO.
No. 331059 (Japanese Patent Laid-Open No. 6-164544), the sliding correlator disclosed therein has a co-frequency equal to the modulation carrier frequency of the received signal.
Multiply sωt and sinωt to obtain the sin component signal and co
Multiplying means for outputting the s-component signal, clock generating means for changing the clock based on the input of the control signal, and digital conversion of the sin component signal and the cos component signal based on the clock output by the clock generating means. A plurality of A / D converting means, and PN code generating means for changing the PN code phase based on the input of the control signal,
A plurality of correlating means for correlating the PN code with the outputs of the respective A / D converting means, a combining means for combining the outputs of the correlating means to obtain a combined correlation signal, and a predetermined correlation with the combining correlation signal of the combining means And a control means for comparing the value and outputting the control signal based on the comparison result. This sliding correlator obtains a cos component and a sin component by multiplying a received signal and cos ωt and sin ωt, which are equal to the modulation carrier frequency of the received signal, extracts a PN code chip from this component, performs A / D conversion, and then performs baseband processing. I am doing data demodulation. However, this sliding correlator separately has a circuit for initial synchronization and a synchronization holding circuit for holding synchronization based on the operation result thereof, which makes the circuit configuration complicated. Is still there. Further, there are unsolved points in the baseband processing of data demodulation and the method of data demodulation.

It is an object of the present invention to provide a sliding correlator having a simplified circuit structure without separately providing an initial synchronizing circuit and a synchronizing holding circuit, and also to solve the above method.

[0008]

To achieve the above object, a sliding correlator according to the present invention comprises a clock generating means for generating a clock, and a sin component signal and a cos component signal of a received signal based on the clock. A / D conversion means for digital conversion and PN with variable phase
PN code generating means for generating a code, a plurality of correlating means for correlating the PN code with the outputs of the respective A / D converting means, and a synthesizing means for synthesizing the outputs of the correlating means to obtain a synthetic correlation signal. , Comparing the synthesized correlation signal of the synthesizing means and the prescribed correlation value with a predetermined value, and based on the comparison result, code synchronization timing detection, integration start timing detection for correct data demodulation, and selecting optimum demodulation data. And a control means for outputting three kinds of control signals for the purpose.

Further, the present invention is, as a spread spectrum communication device, means for differentially coding information data, means for spreading spectrum of differentially coded data by PN code, and modulating a carrier signal by spread spectrum signal. And a cos signal equal to the carrier frequency and a sin in the received signal from the transmitting unit.
Multiplying a signal by detecting a sin component signal and a cos component signal of the received signal and outputting the multiplication signal, a sliding correlator having the above configuration, and delay detection of the correlation output of each of the correlation means There is provided an SSC device including a receiving unit having a unit for selecting optimum demodulated data from a detection signal according to the control signal.

[0010]

In the sliding correlator of the present invention, the cos component and the sin component are obtained by multiplying the received signal and cos ωt and sin ωt which are equal to the modulation carrier frequency of the received signal, and the PN code chip is extracted from both components to extract the A / D signal.
After conversion, correlation is obtained to obtain a composite correlation signal, and the code synchronization, data demodulation, and detection of integration start timing are controlled by this signal. Further, in the SSC device of the present invention,
The transmitting unit differentially encodes the information data and then spreads the spectrum for transmission, and the receiving unit performs baseband processing using the sliding correlator to demodulate the data.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. As one embodiment of the present invention, FIG. 1 shows one of the configurations when a sliding correlator composed of a digital circuit is applied to an SSC system, in which two-phase shift keying (Bi- Phase Shift Keying
Hereinafter, the modulated SS signal is received and data demodulation is performed.

FIG. 1A shows a transmitter, 40 is a differential encoding circuit, and 40a is an exclusive OR circuit (EX-OR), 4
Reference numeral 0b is a delay element, and its input / output relationship is, for example, an ... 0110100011 bn ... 1011000010. 41 is an SS circuit, which is an EX-OR circuit 41a,
It is composed of a multiplier 41b.

FIG. 1 (b) shows a receiving unit, 20 and 21 are multipliers, 22 and 23 are low-pass filters (LPFs), and 24 is a correlation system as a sliding correlator. The correlation system 24 includes A / D converters 25 and 26 and a correlator 2
7, 28, a combination circuit 29, a control circuit 30, a reference PN code generator 31, a clock signal generator 32, differential decoding circuits 37, 38, and a selection circuit 39. Differential decoding circuit 3
Reference numerals 7 and 38 are composed of delay elements 37a and 38a and EX-OR circuits 37b and 38b, and their input / output relationships are opposite to the above.

The correlators 27 and 28 are constructed, for example, as shown in FIG. In the figure, 33 is an exclusive NOR circuit, 34 is an accumulator, and 3 is an accumulator.
Reference numeral 5 is a latch circuit, and 36 is a circuit for converting the output of the latch circuit 35 into a two's complement value and an absolute value. The exclusive NOR circuit 33 detects a match or mismatch between the A / D output and each chip of the PN code, and the accumulator 34 counts the number of matched chips. This operation is performed for one cycle of the PN code, and when the one cycle of the PN code is reached, the count output of the accumulator 34 is latched in the latch circuit 35 by the dump / clear signal (pulse generated at one cycle interval of the PN code). At the same time, the contents of the accumulator 34 are cleared.

Next, the asynchronous demodulation operation of the SS signal according to the embodiment of FIG. 1 will be described. The received SS signal S (t) can be expressed as shown in equation (1).

[0016]

[Equation 1]

In FIG. 1, cosω equal to the SS signal by the multipliers 20 and 21 and the modulation carrier frequency of the SS signal.
By multiplying t and sin ωt, the cos component and si
The n component is obtained, the PN code chip is extracted by the low-pass filters 22 and 23 having a cutoff frequency equal to the PN code clock frequency, and the A / D converters 25 and 26 perform A
Data demodulation is performed by performing baseband processing after D / D conversion.

That is, the correlation value between the digital data of the cos component and the sin component of the received PN code and the reference PN code in a state where the code patterns over one period are synchronized is the correlator 2.
7, 28, and data demodulation is performed based on this correlation value. In data demodulation, as shown in FIGS. 3A and 3B, the carrier co of the received SS signal s (t) is
A phase shift occurs between sω _o t and cos ωt and sin ωt on the receiving side, and, for example, a region (si
When the absolute values of the n component and the cos component are equal, that is, π /
4 <θ <3/4/4 and 5 / 4π <θ <7 / 4π), the maximum value can be obtained from the sin component, and conversely, when the sin component is in the region of zero, cos
It is possible to get the maximum from the components. For example, θ =
When it is π / 4, cos priority may be given.

The differentially encoded information data d
(T) is the normal information data d if the signal component is recovered even if the signal component disappears and an error occurs in the differentially decoded data.
It is possible to decrypt (t). Therefore, the data is demodulated by differential decoding based on the correlation values on the cos side and the sin side, respectively, and based on the result of comparing the correlation values on the cos side and the sin side with the comparator, the correlations of the selectors with high correlation are successively increased. If the demodulated data that shows the value is selected, the received S
Carrier cos ω _o t of S signal s (t) and co on the receiving side
Even if a phase shift occurs between sωt and sinωt, the information data d (t) can be demodulated without error.

FIG. 4 shows a flowchart of the overall operation of FIG. As shown in FIG. 4, in order to perform data demodulation from the SS signal, it is necessary to perform A / D conversion code synchronization and integration start timing determination. Therefore, in order to perform the above operation, FIG. 6 showing the basic configuration of FIG.
An example of the configuration shown in is proposed.

In the figure, reference numeral 40 is an A / D conversion block, which is composed of A / D converters 40-1 to 40-6. Reference numeral 41 is a correlation block, which includes correlators 41-7 to 41-12 and calculation (√ (x ² + y ² )) circuits 41-13 to 41-15. A control block 42 includes an initialization circuit 42-1, a comparison circuit 42-2, a code synchronization and integration start timing determination circuit 42-3, a demodulation data selection circuit 42-4, and a threshold setting circuit 42-5. A PNG block 43 is composed of a reference PN code generator 43-1 and a reference PN code control circuit 43-2. A clock generation block 44 is composed of a clock generation circuit 44-1.

The code synchronization and the integration start timing determination operation according to the embodiment of FIG. 6 having the above-mentioned configuration are performed as follows.

(1) A / D conversion The purpose of the A / D conversion is a reception P obtained by decomposing into a cos component and a sin component and passing through a low pass filter LPF.
The best level of N code chips is sampled and A / D converted. For example, FIG. 5A shows that the sampling is uncertain, and FIG. 5B shows that the sampling is confirmed.
When the reference PN code clock having a frequency equal to the received PN code clock is used as the sampling clock to confirm the sampling, for example, when the rising edge of the reference PN code clock captures the uncertain level of the received PN code chip, The falling edge has captured the defined level. This state is shown in FIG. From this timing relationship, it can be understood that normal A / D conversion can be performed by sampling with either the positive phase or the negative phase of the reference PN code clock. That is, as is clear from the sampling theorem "a band-limited signal having no spectral component of frequency fmHz or more can be uniquely determined by equally-spaced samples smaller than 1/2 fm", the reception PN code clock is used as the sampling clock. A clock having a frequency twice that of FIG. 7 shows a flowchart.
Although it depends on the response characteristics of the LPF, the deviation from the ideal sampling point is the loss Loss shown in equation (2).
Becomes 1.

[0024]

[Equation 2]

The loss Loss2 shown in the equation (3) is also added depending on the quantization level q of the A / D conversion.

[0026]

(Equation 3)

However, it is assumed that the offset error, gain error, non-linear error, etc. of the A / D converter 40 have been corrected.

In FIG. 7, step S1 is A /
The operation performed by the D block 40 and the clock generation block 44 is the operation performed by the correlation block 41 in step S2, and the correlators 41-4 to 41-6 each have an early, a center, and a rate ( Late)
Correlate with.

(2) Code synchronization The purpose of code synchronization is to match the phases of the received PN code contained in the received signal and the reference PN code generated on the receiving side. 9 and 10 show a flowchart and a timing chart. cos side and sin side correlators 41-7, 41-8, 41-9, 41-10, Early, C
With enter, 41-11, 41-12, and Late, the correlation value between the A / D-converted received PN code and the reference PN code is obtained, and the cos-side and sin-side correlation values Early, Center, L
The corresponding ate is synthesized by the synthesizer. The combined correlation value is compared by the comparison circuit 42-2 to determine the maximum correlation value. As shown in FIGS. 13 and 14, the code synchronization and integration start timing determination circuit 42-3
Is repeated until the correlation value reaches a predetermined threshold while changing the reference PN code phase at one chip intervals for all the code phases that the reference PN code can take over one cycle. When the correlation value reaches the predetermined threshold, the reference PN code Center becomes the reference based on the reference PN code phase that has reached the threshold (1/2)
The reference PN codes Early and Center are initialized before and after the chip.

(3) Determining the integration start timing The purpose of determining the integration start timing is the transmission P on the transmitting side.
This is to set the timing of the dump / clear pulse of the accumulator of the correlators Early, Center and Late to the code phase corresponding to the change point of the information data that modulates the N code. For example, as shown in FIG.
If the information data is modulated from one chip of N code, the reference P immediately after code synchronization as shown in FIG.
The timing of the dump / clear pulse of the accumulators of the early, center, and late correlators for the N code is incorrect. Therefore, as shown in FIG. 11C, in the integration start timing determination circuit 42-3, the code phase corresponding to the change point of the information data that modulates the known transmission PN code on the transmission side is detected in advance, and the data is demodulated correctly. Set the dump / clear pulse timings of the correlator Early, Center, and Late accumulators as much as possible.

The above operations (1) to (3) are performed, for example, during the code synchronization pattern period in the preamble period of the packet format as shown in FIG. As the code synchronization pattern, all "0" that does not cause a change point in the data resulting from the differential encoding is selected. Data demodulation is performed by the correlators Ea on the cos side and the sin side as shown in FIG.
Based on the correlation values obtained by rly, Center, and Late, it is performed based on the two's complement and the sign bit obtained by the absolute value conversion circuit 36 and the correlation value converted into an absolute value. cos side and si
The code bits obtained by the n-side correlators Early, Center, and Late are differentially decoded. The absolute-valued correlation values are compared by the comparison circuit 42-2, and a selection signal indicating which of the correlator Early, Center, and Late on the cos side and the sin side has the maximum correlation value is generated. . Correct demodulated data is selected and output by sending the selection signal from the circuit 42-6 to the selection circuit 39. Next, the demodulated data is collated with the frame pattern in the preamble period of the packet format as shown in FIG. 12, and if they match, a timing pulse indicating the start point of the significant data is generated. In the embodiment of FIG. 6, the level for initializing the reference PN code may be the maximum correlation value, in which case the code synchronization operation is slightly different as described below.

(4) Code synchronization The purpose of code synchronization is to match the phases of the received PN code contained in the received signal and the reference PN code generated on the receiving side. 13 and 14 show a flowchart and a timing chart. On the cos side and the sin side correlators Early, Center, and Late, the received P that has been A / D converted
The correlation value between the N code and the reference PN code is obtained, and the cos side and sin side correlation values Early, Center, and Late corresponding to each other are combined by the combiner 29. The combined correlation value is compared by the comparison circuit 42-2 to determine the maximum correlation value. As shown in FIG. 13 and FIG. 14, the code synchronization and integration start timing determination circuit 42-3 uses the reference P
Initialization of the maximum correlation value and the reference PN code by comparing the maximum correlation value up to the previous time with the current correlation value while changing the reference PN code phase at every one chip interval for all code phases that the N code can take over one cycle. Repeat the phase update. When the maximum correlation value is obtained, the initialization circuit 42-1 sets (1/2) so that the reference PN code Center becomes the reference based on the reference PN code phase for which the maximum correlation value is obtained.
The reference PN codes Early and Center are initialized before and after the chip. Alternatively, the code synchronization detection may be checked by combining FIG. 6 and FIG. 10 with FIG. 13 and FIG. 14 and then obtaining the maximum correlation value and comparing it with a predetermined threshold. That is, although the maximum correlation value can be determined to any one of E, C, and L, it may have been determined by unnecessary noise such as spurious. This may be checked by comparing with a predetermined threshold level to determine whether or not to shift to the subsequent processing. If synchronization is not held after code synchronization, the data length that can be demodulated is usually limited by the clock error between the transmission PN code clock and the reception PN code clock. However, when it is applied to a bucket transmission system, by selecting the performance of the crystal used for clock generation based on the transmission data length that does not degrade the system throughput, high cost performance is achieved without the synchronization holding function. Can be realized.

[0033]

As described above, according to the present invention, it is not necessary to separately provide the initial synchronization circuit and the synchronization holding circuit, so that the structure of the sliding correlator can be simplified. Further, the problems of baseband processing of data demodulation and data demodulation when the correlator is used in an SSC system are also solved.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of a correlator.

FIG. 3 is an explanatory diagram of a sin component region and a cos component region in data demodulation.

FIG. 4 is a flowchart showing the overall operation of the above embodiment.

FIG. 5 is a waveform diagram showing sampling indeterminate and confirmed states.

FIG. 6 is a block diagram showing an embodiment based on a specific configuration of the present invention.

7 is a flowchart showing the operation of A / D conversion in the embodiment of FIG.

8 is a waveform chart showing the relationship between the reference clock and the reception code chip in the embodiment of FIG.

FIG. 9 is a flowchart showing an operation of code synchronization.

FIG. 10 is a timing chart of a code synchronization operation.

FIG. 11 is a timing chart of the operation for determining the integration start timing.

FIG. 12 is an explanatory diagram of a packet format.

FIG. 13 is a flowchart showing an operation of code synchronization.

FIG. 14 is a timing chart of the code synchronization operation.

FIG. 15 is a block diagram showing a conventional SSC system.

FIG. 16 is a block diagram showing a conventional sliding correlator.

17 is a waveform diagram showing a correlation waveform in the sliding correlator of FIG.

[Explanation of symbols]

 20, 21 Multiplier 22, 23 Low-pass filter 24 Correlation system 25, 26 A / D converter 27, 28 Correlator 29 Synthesis circuit 30 Control circuit 31 Reference PN code generator 32 Clock signal generator

Claims (3)

[Claims] 1. A clock generation means for generating a clock, a plurality of A / D conversion means for digitally converting a sin component signal and a cos component signal of a received signal based on the clock, and a PN code having a variable phase. PN code generating means for generating, a plurality of correlating means for correlating the PN code with the output of each A / D converting means, a synthesizing means for synthesizing the outputs of the correlating means to obtain a synthesized correlation signal, For comparing the synthetic correlation signal of the synthesizing means and the synthetic correlation signal with a predetermined value, based on the comparison result, code synchronization timing detection, integration start timing detection for correctly performing data demodulation, and selecting optimum demodulation data A sliding correlator comprising: a control unit that outputs three types of control signals. 2. The sliding correlator according to claim 1, wherein the received signal is a spread spectrum signal by a PN code of differentially encoded information data. 3. A transmission unit having means for differentially coding information data, means for spreading spectrum of differentially coded data by PN code, and means for modulating and transmitting carrier signal by spread spectrum signal. And the received signal from the transmitter is multiplied by the cos signal and the sin signal, which are equal to the carrier frequency, to obtain the si of the received signal.
A multiplication means for detecting and outputting the n-component signal and the cos-component signal, a clock generation means for generating a clock, and a plurality of A / Ds for digitally converting the sin-component signal and the cos-component signal of the received signal based on the clock. Conversion means,
PN code generating means for generating a PN code having a variable phase,
A plurality of correlating means for correlating the PN code with the output of each A / D converting means, a combining means for combining the outputs of the correlating means to obtain a combined correlation signal, a combined correlation signal of the combining means, and the combined correlation. Control means for comparing a signal with a predetermined value, and based on the comparison result, code synchronization timing detection, integration start timing detection for correctly performing data demodulation, and outputting three types of control signals for selecting optimum demodulation data. And a receiving section having: a sliding correlating unit having: and a unit that delay-detects the correlation output of each of the correlating units and selects the optimum demodulated data from the obtained detection signal by the control signal. Spread spectrum communication device using a sliding correlator.