JP2744542B2 - Digital signal receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION This invention relates to a digital signal receiving apparatus for use in high-speed digital signal transmission of a wireless network of a cellular phone or a LAN, if specifically, the carrier frequency F _C, the modulated digital signal pair to the symbol rate F _B
To, | F _C -F _L | and ≧ (1/2) · F phase detection means for detecting a baseband signal from the received RF signal with the reference signal of frequency F _L with _B the relationship, by the phase detection means A / D at intervals of π / 2 with respect to the detected baseband signal whose phase rotates at the frequency F _C -F _L
A quadrature component deriving unit for converting, and a quadrature component data converted by the quadrature component deriving unit and a delay detection unit for calculating and deriving a modulated digital signal based on the following equation from the quadrature component data one time slot before : The present invention relates to a digital signal receiving device configured to include:

[0002]

2. Description of the Related Art Since a high-frequency signal received by the above-mentioned digital signal receiving apparatus is usually limited in band in order to use a frequency band efficiently, a baseband signal detected by the phase detecting means is: As shown in FIG.
The amplitude becomes small when the symbols are switched. The conventional delay detection means has not been configured with special consideration of this phenomenon.

[0003] Now, in the I-th symbol, the A / D
Let the converted baseband signal be Si (n), one symbol
If the number of samples per unit is M,

[0004]

(Equation 1)

[0005] a Si (n) = Acos (πΣ (j = 0, i) S (j) + (M · (i-1) + n) π / 2) ............... (1). However, 1 ≦ n ≦ M. From this, to obtain a modulated digital signal, I (i, n) = Si (n) .Si-1 (n) + Si (n-1) .Si-1 (n-1) (2) ) Q (i, n) = - Si (n) · Si-1 (n-1) + Si (n-1) · Si-1 (n) applying operation of ............... (3). I (i, n) = Si (n) · Si-1 (n) + Si (n-1) · Si-1 (n-1) = Acos (πΣ (j = 0, i) S (j) + ( M (i-1) + n) π / 2) Acos (πΣ (j = 0, i-1) S (j) + (M (i-1) + n) π / 2) + Acos (πΣ (j = 0 , i) S (j) + (M (i-1) + n-1) π / 2) Acos (πΣ (j = 0, i-1) S (j) + (M (i-1) + n-1 ) π / 2) = A ² ｛(cosπΣ (j = 0, i) S (j) cos (M (i-1) + n) π / 2 − sinπΣ (j = 0, i) S (j) sin ( M (i-1) + n) π / 2) × cosπΣ (j = 0, i-1) S (j) cos (M (i-1) + n) π / 2 − sinπΣ (j = 0, i-1 ) S (j) sin (M (i-1) + n) π / 2) + cosπΣ (j = 0, i) S (j) cos (M (i-1) + n-1) π / 2−sinπΣ ( j = 0, i) S (j) sin (M (i-1) + n-1) π / 2) × cosπΣ (j = 0, i-1) S (j) cos (M (i-1) + n -1) π / 2 − sinπΣ (j = 0, i-1) S (j) sin (M (i-1) + n-1) π / 2)｝ = A ² ｛(cosπΣ (j = 0, i ) S (j) cosπΣ (j = 0, i-1) S (j) cos (M (i-1) + n) π / 2 cos (M (i-1) + n) π / 2 − cosπΣ (j = 0, i) S (j) sinπΣ (j = 0, i-1) S (j) cos (M (i-1) + n) π / 2 sin (M (i-1) + n) π / 2 − sinπΣ (j = 0, i) S (j) cosπΣ (j = 0, i-1) S (j) sin (M (i-1) + n) π / 2 cos (M (i-1) + n) π / 2 + sinπΣ (j = 0, i) S (j) sinπΣ (j = 0, i-1) S (j) sin (M (i-1) + n) π / 2 sin (M (i-1) + n ) π / 2 + cosπΣ (j = 0, i) S (j) cosπΣ (j = 0, i-1) S (j) cos (M (i-1) + n-1) π / 2 cos (M ( i- 1) + n-1) π / 2 − cosπΣ (j = 0, i) S (j) sinπΣ (j = 0, i-1) S (j) cos (M (i-1) + n-1) π / 2 sin (M (i-1) + n-1) π / 2 − sinπΣ (j = 0, i) S (j) cosπΣ (j = 0, i-1) S (j) sin (M (i-1 ) + N-1) π / 2 cos (M (i-1) + n-1) π / 2 + sinπΣ (j = 0, i) S (j) sinπΣ (j = 0, i-1) S (j) sin (M (i-1) + n-1) π / 2 sin (M (i-1) + n-1) π / 2｝ = A ² ｛cosπΣ (j = 0, i) S (j) cosπΣ (j = 0, i-1) S (j) (cos (M (i-1) + n) π / 2 × cos (M (i-1) + n) π / 2 + cos (M (i-1) + n-1) π / 2cos (M (i-1) + n-1) π / 2) − cosπΣ (j = 0, i) S (j) sinπΣ (j = 0, i-1) S (j) (cos (M ( i-1) + n) π / 2 × sin (M (i-1) + n) π / 2 + cos (M (i-1) + n-1) π / 2sin (M (i-1) + n-1) π / 2) − sinπΣ (j = 0, i) S (j) cosπΣ (j = 0, i-1) S (j) (sin (M (i-1) + n) π / 2 × cos (M (i− 1) + n) π / 2 + sin (M (i-1) + n) π / 2cos (M (i-1) + n-1) π / 2) + sinπΣ (j = 0, i) S (j) sinπΣ (j = 0, i-1) S (j) (sin (M (i-1) + n) π / 2 × sin (M (i-1) + n) π / 2 + sin (M (i-1) + n-1) π / 2sin (M (i-1) + n-1) π / 2)｝ where cos (M (i-1) + n-1) π / 2 = cos ((M (i-1) + n) π / 2−π / 2) = sin (M (i-1) + n) π / 2, sin (M (i-1) + n-1) π / 2 = sin ((M (i-1) + n) π / 2−π / 2) = − cos (M (i−1) + n) π / 2, so I (i, n) = A ² ｛cosπΣ (j = 0, i) S (j) cosπΣ (j = 0, i-1) S (j) (cos (M (i-1) + n) π / 2 cos (M (i-1) + N) π / 2 + sin (M (i-1) + n) π / 2sin (M (i-1) + n) π / 2) − cosπΣ (j = 0, i) S (j) sinπΣ (j = 0 , i-1) S (j) cos (M (i-1) + n) π / 2 sin (M (i-1) + n) π / 2 −sin (M (i-1) + n) π / 2cos ( M (i-1) + n) π / 2 − sinπΣ (j = 0, i) S (j) cosπΣ (j = 0, i-1) S (j) sin (M (i-1) + n) π / 2 cos (M (i-1) + n) π / 2 −cos (M (i-1) + n) π / 2sin (M (i-1) + n) π / 2 + sinπΣ (j = 0, i) S (j) sinπΣ (j = 0, i-1) S (j) sin (M (i-1) + n) π / 2 sin (M (i-1) + n) π / 2 + cos (M (i-1 ) + n) π / 2cos ( M (i-1) + n) π / 2} = A 2 {cosπΣ (j = 0, i) S (j) cosπΣ (j = 0, i-1) S (j) + sinπΣ (j = 0, i) S (j) sinπΣ (j = 0, i-1) S (j)｝ = A ² cos (πΣ (j = 0, i) S (j) −πΣ (j = 0 , i-1) S (j))) = A ² cosπS (i) …………… (4) Q (i, n) = − Si (n) · Si-1 (n-1) + Si (n -1) · Si-1 (n) = -Acos (πΣ (j = 0, i) S (j) + (M (i-1) + n) π / 2) Acos (πΣ (j = 0, i- 1) S (j) + (M (i-1) + n-1) π / 2) + Acos (πΣ (j = 0, i) S (j) + (M (i-1) + n-1) π / 2) Acos (πΣ (j = 0, i-1) S (j) + (M (i-1) + n) π / 2) = A 2 {(-cosπΣ (j = 0, i) S (j ) cos (M (i-1) + n) π / 2 − sinπΣ (j = 0, i) S (j) sin (M (i-1) + n) π / 2) × cosπΣ (j = 0, i-1) S (j) cos (M (i-1) + n-1) π / 2 − sinπΣ (j = 0, i-1) S (j) sin (M (i-1) + n-1) π / 2) + cosπΣ (j = 0, i) S (j) cos (M (i-1) + n-1) π / 2 − sinπΣ (j = 0, i) S (j) sin (M (i-1) + n-1) π / 2) × cosπΣ (j = 0, i-1) S (j) cos (M ( i-1) + n) π / 2 − sinπΣ (j = 0, i-1) S (j) sin (M (i-1) + n) π / 2)｝ = A ² ｛(cosπΣ (j = 0, i) S (j) cosπΣ (j = 0, i-1) S (j) cos (M (i-1) + n) π / 2 cos (M (i-1) + n-1) π / 2 + cosπΣ (j = 0, i) S (j) sinπΣ (j = 0, i-1) S (j) cos (M (i-1) + n) π / 2 sin (M (i-1) + n-1) π / 2 + sinπΣ (j = 0, i) S (j) cosπΣ (j = 0, i-1) S (j) sin (M (i-1) + n) π / 2 cos (M (i-1 ) + N-1) π / 2 − sinπΣ (j = 0, i) S (j) sinπΣ (j = 0, i-1) S (j) sin (M (i-1) + n) π / 2 sin ( M (i-1) + n-1) π / 2 + cosπΣ (j = 0, i) S (j) cosπΣ (j = 0, i-1) S (j) cos (M (i-1) + n- 1) π / 2 cos (M (i-1) + n) π / 2 − cosπΣ (j = 0, i) S (j) sinπΣ (j = 0, i-1) S (j) cos (M (i -1) + n-1) π / 2 sin (M (i-1) + n) π / 2 − sinπΣ (j = 0, i) S (j) cosπΣ (j = 0, i-1) S (j) sin (M (i-1) + n-1) π / 2 cos (M (i-1) + n) π / 2 + sinπΣ (j = 0, i) S (j) sinπΣ (j = 0, i-1 ) S (j) sin (M (i-1) + n-1) π / 2 sin (M (i-1) + n) π / 2｝ = A ² ｛-cosπΣ (j = 0, i) S (j) cosπΣ (j = 0, i-1) S (j) (cos (M (i-1) + n) π / 2 × cos (M (i-1) + n-1) π / 2−cos ( M (i-1) + n-1) π / 2cos (M (i-1) + n) π / 2) + cosπΣ (j = 0, i) S (j) sinπΣ (j = 0, i-1) S (j) (cos (M (i-1) + n) π / 2 × sin (M (i-1) + n-1) π / 2-cos (M (i-1) + n-1) π / 2sin ( M (i-1) + n) π / 2) + sinπΣ (j = 0, i) S (j) cosπΣ (j = 0, i-1) S (j) (sin (M (i-1) + n) π / 2 × cos (M (i-1) + n-1) π / 2−sin (M (i-1) + n) π / 2cos (M (i-1) + n) π / 2) − sinπΣ (j = 0, i) S (j) sinπΣ (j = 0, i-1) S (j) (sin (M (i-1) + n) π / 2 × sin (M (i-1) + n-1) π / 2−sin (M (i-1) + n-1) π / 2sin (M (i-1) + n) π / 2)｝ = A ² ｛cos πΣ (j = 0, i) S (j) sinπΣ (j = 0, i-1) S (j) (cos (M (i-1) + n) π / 2 × sin (M (i-1) + n-1) π / 2−cos (M (i -1) + n-1) π / 2sin (M (i-1) + n) π / 2) + sinπΣ (j = 0, i) S (j) cosπΣ (j = 0, i-1) S (j) (sin (M (I-1) + n) π / 2 × cos (M (i-1) + n-1) π / 2− sin (M (i-1) + n-1) π / 2cos (M (i -1) + n) π / 2)｝ where cos (M (i-1) + n-1) π / 2 = cos ((M (i-1) + n) π / 2−π / 2) = sin (M (i-1) + n) π / 2, sin (M (i-1) + n-1) π / 2 = sin ((M (i-1) + n) π / 2−π / 2) = − cos (M (i-1) + n) π / 2, Q (i, n) = A ² ｛cosπΣ (j = 0, i) S (j) sin πΣ (j = 0, i-1) S (j) (− cos (M (i−1) + n) π / 2 × cos (M (i−1) + n) π / 2−sin (M (i− 1) + n) π / 2sin (M (i-1) + n) π / 2) + sinπΣ (j = 0, i) S (j) cosπΣ (j = 0, i-1) S (j) sin (M (i-1) + n) π / 2 × sin (M (i-1) + n) π / 2 + sin (M (i-1) + n) π / 2cos (M (i-1) + n) π / 2)｝ = A ² ｛−cosπΣ (j = 0, i) S (j) sinπΣ (j = 0, i-1) S (j) + sinπΣ (j = 0, i) S (j) cosπΣ (j = 0, i-1) S (j)｝ = A ² sin (πΣ (j = 0, i) S (j) -πΣ (j = 0, i-1) S (j))) = A ² sinπS (i) (5) As described above, the modulated digital signal is reproduced.

[0006]

However, according to the above-mentioned conventional digital signal receiving apparatus, if the amplitude is extremely small at the time of symbol switching, the phase information becomes ambiguous, so that a demodulation error occurs. There is a disadvantage that accurate derivation of digital signals may not be possible. An object of the present invention is to eliminate the above disadvantages.

[0007]

In order to achieve the above object, a digital signal receiving apparatus according to the present invention is characterized in that the differential detection means determines whether or not a calculated and derived modulated digital signal is significant. The difference is that a judgment means for judging based on the amplitude value of the band signal and outputting a signal judged to be significant is provided.

[0008]

The judging means grasps the amplitude value of the baseband signal over a plurality of symbols and judges that the amplitude value is not significant if the amplitude value at the timing when the modulated digital signal is calculated and derived is not significant. Discard the data,
Prepare for the next calculation derivation timing. If the amplitude value at the timing when the modulated digital signal is calculated and derived is greater than or equal to the set value, it is determined to be significant and the data is adopted as a new modulated digital signal. The set value may be arbitrarily set, for example, a value of 50% of the maximum amplitude value of the baseband signal over a plurality of symbols. As a result, data adopted for each time slot is output as a modulated digital signal.

[0009]

According to the present invention, it is possible to provide a digital signal receiving apparatus capable of accurately reproducing a modulated digital signal even when the amplitude becomes extremely small at the time of symbol switching.

[0010]

Embodiments will be described below. The digital signal receiving device adopts the double differential coded communication system.
As shown in FIG. 1, an amplifying means 5 for amplifying a received high-frequency signal, a phase detecting means 6 for detecting an orthogonal baseband signal from the amplified high-frequency signal, and a base detected by the phase detecting means 6 A quadrature component deriving unit 7 for A / D converting the band signal; and a delay detection unit 8 for calculating and deriving a modulated digital signal from the converted quadrature component data and the quadrature component data one slot before. The delay detection means 8 includes a first delay detection unit 8A for deriving a modulated digital signal, a second delay detection unit 8B for removing a frequency error from the modulated digital signal derived by the first delay detection unit 8A, and the like. It is.

[0011] More specifically, the phase detecting means 6, the output signal from the amplifying means 5, the frequency F _C of the carrier, the symbol rate F _B of the modulated digital _{signal, | F C -F L | ≧} ( an oscillator 61 for generating a reference signal of frequency F _L with 1/2) · F _B becomes relationship, a mixer circuit 62 for detecting a baseband signal at the reference signal, Yes constituted by an amplifier 63 and the like, the present embodiment In the example, F _C = 150 MHz, F _L = 146 MHz, F _B
= 1 MHz . The orthogonal component deriving means 7
Comprises a clock oscillator 71 having a frequency of 16 MHz, and an A / D converter 72 for converting the baseband signal into a digital signal in synchronization with a clock signal from the clock oscillator 71. The A / D conversion is performed on the baseband signal detected by the above and beat at the frequency F _C -F _L (= 4 MHz) at intervals of π / 2.

The delay detection means 8 is adapted to derive the quadrature component.
A / D converted by means of π / 2 phase by means 7
The most recently sampled version of the two orthogonal component data
An angle converter 8C for converting and outputting angle component data corresponding to the intersection component data; a delay detector 8A for calculating and deriving a modulated digital signal from the angle component data by the angle converter 8C and the angle component data one time slot before; 8B. More specifically, the angle converter 8C outputs an H of 00H to 0FFH corresponding to a phase angle of 0 ° to 360 °.
A ROM 81 in which EX data is stored; a shift register 82 for securing a digital signal previously converted by an A / D converter 72 having a phase different by π / 2;
An access circuit (not shown) for reading the angle component data of the baseband signal from the ROM 81 from the digital signal most recently converted in step 2 and the data of the shift register 82. The delay detectors 8A and 8B
Are composed of shift register groups T1 and T2 for delaying the angle component data by one time slot, and arithmetic units 83 and 84 for subtracting the latest angle component data from the value of the last stage shift register in the shift register group. It is.
The calculator 83 serves as a first delay detector for deriving a modulated digital signal, and the calculator 84 serves as a second delay detector for removing a frequency error from the modulated digital signal derived by the first delay detector. That is, the arithmetic units 83 and 84
Is 00H, that is, if the angle component data of one time slot before and this time are equal, the data of the previous time and this time are equal, and the outputs of the arithmetic units 83 and 84 are 80H, that is, the angle component data of one time slot before and this time. If the phase is inverted, it is determined that the previous and current data are different.

The double differential encoding communication system , which is the operation principle of the differential detection units 8A and 8B, will be described in detail below.
I do. Δφ is a phase angle initial value, and Δω is 1 due to a frequency error.
Assuming that the phase error per time slot and S1 and S2 are primary differential phase differences, the quadrature detection output two time slots before derived by the quadrature component deriving means 7 is (cos (Δφ), sin (Δφ)), 1 If the quadrature detection output before the time slot is (cos (Δφ + Δω + S2), sin (Δφ + Δω + S2)) and the current quadrature detection output is (cos (Δφ + 2Δω + S1 + S2), sin (Δφ + 2Δω + S1 + S2)), the delay detection two time slots before is obtained. The calculation is: I2 ′ = cos (Δφ) · cos (Δφ + Δω + S2) + sin (Δφ) · sin (Δφ + Δω + S2) = cos (Δω + S2) Q2 ′ = cos (Δφ) · sin (Δφ + Δω + S2) −sin (Δφ + cos (Δφ) · cos (Δφ) ) = Sin (Δω + S2) Similarly, the differential detection operation one time slot before is represented by I1 ′ cos (Δφ + Δω + S2) · cos (Δφ + 2Δω + S1 + S2) + sin (Δφ + Δω + S2) · sin (Δφ + 2Δω + S1 + S2) = cos (Δω + S1) Q1 '= cos (Δφ + Δω + S2) · sin (Δφ + 2Δω + S1 + S2) -sin (Δφ + Δω + S2) · cos (Δφ + 2Δω + S1 + S2) = sin (Δω + S1), and the term of Δφ is eliminated by the first-order differential detection. If these are further delayed detected, I1 = cos (Δω + S2) · cos (Δω + S1) + sin (Δω + S2) · sin (Δω + S1) = cos (S1-S2) Q1 = cos (Δω + S2) · sin (Δω + S1) −sin (Δω + S2) Cos (Δω + S1) = sin (S1−S2), and the term of Δω is eliminated in the second-order differential detection. That is, the phase error due to the frequency error is removed.

[0014] The constituting a part of said delay detection unit 8
The A / D is stored in the ROM 81 by the orthogonal component deriving means 7.
The amplitude data for evaluation corresponding to the converted baseband signal is input, and the access circuit (not shown) is
The π / 2 phase is changed by the orthogonal component deriving means 7 through
From the two orthogonal component data A / D converted
The amplitude data at the timing is output from the ROM 81.
It is. The amplitude data is input to the delay detection section 8A in the preceding stage.
Is, this time of the amplitude data and one time slot before the amplitude Day
Is input to the discriminating means 11, and further, a delay detection
The amplitude data two time slots before is determined through the wave portion 8B.
It is configured to be input to the separate means 11. The discrimination
The means 11 uses the differential detection means 8 to control the frequency F _C -F _L
For the modulated digital signal calculated and derived at intervals of π / 2 from the baseband signal beat at
If the amplitude data at the time is greater than 50% of the maximum value of the amplitude data of one time slot, the value of the modulated digital signal is adopted and the maximum value of the amplitude data of one cycle is 50%.
If the value is smaller than the value of% , the configuration is such that the value of the modulated digital signal is discarded . That is, as shown in FIG.
Data within a range of 50% or more of the maximum value of the amplitude within one time slot is valid data, and data within a range of 50% or less is invalid data. In particular, data derived at the time of symbol switching is likely to become invalid data.

As shown in FIG. 3, the transmitting apparatus adopting the above-mentioned double differential encoding communication system comprises a first differential means 1 for delaying and adding a digital signal to be transmitted by one time slot, The second differential means 2 adds the first modulated signal generated by the first differential means 1 after delaying it by one time slot again, and the second modulated signal generated by the second differential means 2 generates a carrier wave. It comprises a phase modulating means 3 such as a ring modulator for modulating the phase, and a transmitting means 4 for transmitting a signal generated by the phase modulating means 3.
The first differential means 1 and the second differential means 2 are a digital delay element such as a shift register for delaying a digital signal to be transmitted by one time slot, and the current signal and the delayed signal are mo
d. It is composed of an adder for adding by 2.

Another embodiment will be described below. In the above embodiment, the data transmission rate (symbol rate F _B ) is 1 Mbps.
A high-frequency signal with a frequency of 150 MHz that has been subjected to two-phase modulation (BPSK) with a modulated digital signal of
Has been described in the reference signal for the orthogonal detection circuit of the single mixer method of phase detection, data transmission speed, the carrier frequency is optional rather than limited to these values, the reference wave frequency, | F _C -F _L | ≧ (1/2) ・ N ・
Any frequency F _L that satisfies F _B is applicable. In the above embodiment, two-phase modulation [BPSK] has been described.
The present invention is not limited to this, and can be applied to any phase modulation. For example, quadrature phase modulation [QPSK] may be used.
In this case, the outputs of the arithmetic units 83 and 84 are 0, π / 2,
00B, 10B, 11B, 01 corresponding to π, 3π / 2
B binary data is obtained.

[0017] In the previous example, the differential detection circuit, the quadrature component data is converted to an angle component data, as calculates and derives a modulated digital signal from its angular component data and one time slot before the angular component data The discriminating means 11 is provided in the one adopting the configured double differential encoding communication system.
It has been described shall delay as the detection means, as shown in FIG. 4, the shift register SR to the quadrature component data derived by quadrature component deriving unit one time slot delayed
0,..., SR8 and an operation unit OP for performing the following operation, and the modulated digital signal derived as a result of the operation.
A determination means 11 for determining whether the signal is valid or invalid is provided.
It may be. I (n) = S _i (n) · S _i−1 (n) + S _i (n−1) · S _i−1 (n−1) Q (n) = − S _i (n) · S _{i− 1 (n-1) + S} i (n-1) · S i-1 (n) in addition, determination means of the present invention _{is, | F C -F L | ≧} (1 /
2) at the frequency F _L that satisfies F _B can also be employed in any circuit configuration of the method for detecting a baseband signal.

In the claims, reference numerals are provided for convenience of comparison with the drawings, but the present invention is not limited to the configuration shown in the attached drawings.

[Brief description of the drawings]

FIG. 1 is a block diagram of a digital signal receiving apparatus.

FIG. 2 is a timing chart.

FIG. 3 is a block diagram of a digital signal transmission device.

FIG. 4 is a block diagram showing a digital signal receiving apparatus according to another embodiment.

[Explanation of symbols]

 6 phase detecting means 7 orthogonal component deriving means 8 delay detecting means 11 discriminating means

Claims (1)

(57) [Claims] Frequency F _C of claim 1. A carrier for the symbol rate F _B of the modulated digital signal, | at ≧ (1/2) · F reference signal of a frequency F _L with _B the relationship | F _C -F _L Phase detection means (6) for detecting a baseband signal from a received high-frequency signal
When the is detected by the phase detection means (6) frequency F _C -F _L
Orthogonal component deriving means (7) for performing A / D conversion at an interval of π / 2 with respect to the baseband signal whose phase is rotated by the orthogonal component data and the orthogonal component data converted by the orthogonal component deriving means (7) one time slot before And a delay detection means (8) for calculating and deriving a modulated digital signal from the quadrature component data of the digital signal receiving apparatus. A digital signal receiving apparatus comprising: a determination unit (11) that determines whether a signal is significant based on the amplitude value of the baseband signal and outputs a signal determined to be significant.