JP6345980B2 - Receiver - Google Patents

Description

  Embodiments described herein relate generally to a receiving apparatus.

  The digital receiver converts the received analog signal into a digital signal using an analog / digital converter, and performs signal processing on the digital signal. The digital reception device acquires a desired signal from the received signal by performing signal processing on the digital signal. In recent years, an analog / digital converter capable of sampling at a frequency of 1 GHz or more has been developed. By using such a high-speed analog-to-digital converter for a digital receiver, it is possible to widen the band that is received by the digital receiver.

  As described above, when the reception target is widened, the amount of digital signals sequentially obtained by the analog / digital converter increases, and the processing load such as the amount of calculation in signal processing increases significantly. In applications where real-time performance is not required, a digital signal obtained sequentially is stored in a memory or the like, and then signal processing is sequentially performed on the digital signal to obtain a desired signal. On the other hand, in applications that require real-time performance, it is necessary to reduce the time required for signal processing in accordance with the increasing amount of computation. In order to shorten the time required for signal processing, it is conceivable to increase the operating frequency of a DSP (Digital Signal Processor) or CPU (Central Processing Unit) used for signal processing. However, the operating frequency of the DSP and CPU cannot be increased in accordance with the increase in the speed of the analog / digital converter, and the real-time property may be impaired.

JP 2007-208790 A

Kazumasa Onioi, Jin Sugawara, Masatoshi Hatano, “A Construction Method of Digital Quadrature Detector”, Hiroshima Institute of Technology Bulletin 45, 2011, pp. 11-27. 213-217

  The problem to be solved by the present invention is to provide a receiving apparatus that facilitates increasing the signal processing speed in accordance with the widening of the reception target.

The receiving apparatus according to the embodiment includes an analog / digital conversion unit, a first sorting switch, a first rearrangement unit, a first signal processing unit, and a second signal processing unit. The analog / digital converter sequentially outputs the sampling values obtained by sampling the received signal at a predetermined first period. The first distribution switch alternately outputs the sampling values output from the analog / digital conversion unit to the first sampling value series and the second sampling value series, and sequentially outputs them. The first rearrangement unit outputs the first sampling value in the first sampling value series and the first sampling value in the second sampling value series each time the sampling value in the first sampling value series is output. The second sampling value output from the distribution switch at the same timing and the third sampling value output next to the first sampling value in the first sampling value series are output at the same timing. The first signal processing unit sequentially outputs signal processing results obtained by signal processing based on the first sampling value and the second sampling value. The second signal processing unit sequentially outputs signal processing results obtained by signal processing based on the second sampling value and the third sampling value. The first rearrangement unit is a clock signal having a rising edge synchronized with the output of the sampling value of the first sampling value series, and is synchronized with the rising edge or the falling edge of the clock signal of the first period, First to seventh flip-flops for latching input sampling values are provided. The first flip-flop receives a sampling value of the first sampling value series and outputs the latched sampling value to the second flip-flop. The second flip-flop receives the sampling value output from the first flip-flop, and outputs the latched sampling value as the first sampling value to the first signal processing unit. The third flip-flop receives the sampling value of the second sampling value series and outputs the latched sampling value to the fourth flip-flop. The fourth flip-flop receives the sampling value output from the third flip-flop, and outputs the latched sampling value as the second sampling value to the first signal processing unit. The fifth flip-flop receives the sampling value of the second sampling value series and outputs the latched sampling value to the sixth flip-flop. The sixth flip-flop receives the sampling value output from the fifth flip-flop, and outputs the latched sampling value as the second sampling value to the second signal processing unit. The seventh flip-flop receives the sampling value of the first sampling value series, and outputs the latched sampling value as the third sampling value to the second signal processing unit.

The block diagram which shows the structural example of the receiver 1 of embodiment. The block diagram which shows the structural example of the rearrangement device 144 of embodiment. The timing chart which shows operation | movement of the digital signal processing part 14-1 of embodiment.

  Hereinafter, a receiver according to an embodiment will be described with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration example of the receiving device 1 according to the embodiment. As shown in FIG. 1, the receiving device 1 includes an antenna 10, a low noise amplifier 11, a filter circuit 12, an analog / digital converter 13, a digital signal processing unit 14-1, and a digital signal processing unit 14-2. .

  The low noise amplifier 11 amplifies the reception signal received by the antenna 10. The low noise amplifier 11 outputs the amplified received signal to the filter circuit 12. The filter circuit 12 attenuates signal components other than the desired frequency band in the reception signal amplified by the low noise amplifier 11, and outputs the signal component of the desired frequency band to the analog / digital converter 13. For example, a low-pass filter or a band-pass filter is used as the filter circuit 12.

  The analog / digital converter 13 samples the signal output from the filter circuit 12 at a predetermined sampling frequency and converts it into a digital signal. The analog / digital converter 13 alternately outputs a digital signal indicating the sampling value obtained by the conversion to the digital signal processing unit 14-1 and the digital signal processing unit 14-2 in time series order.

  When the analog / digital converter 13 outputs the sampling value obtained by sampling to the digital signal processing unit 14-1, the analog / digital converter 13 outputs the sampling value obtained by the next sampling to the digital signal processing unit 14-2. Further, the sampling value obtained by the next sampling is output to the digital signal processing unit 14-1. The analog / digital converter 13 outputs a clock signal synchronized with the output digital signal to the digital signal processing unit 14-1 and the digital signal processing unit 14-2.

  The digital signal output from the analog / digital converter 13 to the digital signal processing unit 14-1 and the digital signal processing unit 14-2 is synchronized with the rising edge and the falling edge of the clock signal. The digital signal processing unit 14-1 and the digital signal processing unit 14-2 operate in synchronization with the clock signal output from the analog / digital converter 13.

In FIG. 1, the digital signal output from the analog / digital converter 13 to the digital signal processing unit 14-1 is indicated as DATA _EVEN . A digital signal output from the analog / digital converter 13 to the digital signal processing unit 14-2 is indicated as DATA _ODD . The clock signal input to the digital signal processing unit 14-1 and the digital signal processing unit 14-2 is indicated as DCLK.

  The digital signal processing unit 14-1 and the digital signal processing unit 14-2 perform signal processing on the digital signal output from the analog / digital converter 13. Each of the digital signal processing unit 14-1 and the digital signal processing unit 14-2 outputs a result obtained by signal processing. In the receiving apparatus 1, the digital signal processing units 14-1 and 14-2 perform quadrature demodulation on the received signal, and the demodulation results are output from the digital signal processing units 14-1 and 14-2. In the receiving apparatus 1, the digital signal output from the analog / digital converter 13 to the digital signal processing unit 14-1 is handled as an in-phase component (I component). The digital signal output from the analog / digital converter 13 to the digital signal processing unit 14-2 is handled as an orthogonal component (Q component).

  The digital signal processing unit 14-1 and the digital signal processing unit 14-2 have the same configuration. In order to avoid duplication of description, the configuration of the digital signal processing unit 14-1 will be described, and the description of the configuration of the digital signal processing unit 14-2 will be omitted. The digital signal processing unit 14-1 includes a distribution switch 141, a multiplier 142, a multiplier 143, a rearranger 144, a signal processing circuit 145, and a signal processing circuit 146.

  The distribution switch 141 alternately distributes the sampling value input from the analog / digital converter 13 into the sampling value series A and the sampling value series B in synchronization with the clock signal. The distribution switch 141 outputs the sampling value series A to the multiplier 142 and outputs the sampling value series B to the multiplier 143. The distribution switch 141 outputs the sampling value output from the analog / digital converter 13 to the multiplier 142 in synchronization with the rising edge of the clock signal. The distribution switch 141 maintains the sampling value output to the multiplier 142 until the next rising edge of the clock signal. The distribution switch 141 outputs the sampling value output from the analog / digital converter 13 to the multiplier 142 in synchronization with the falling edge of the clock signal. The distribution switch 141 maintains the sampling value output to the multiplier 143 until the next falling edge of the clock signal.

  The multiplier 142 multiplies the sampling value output from the distribution switch 141 by “1”, and latches the multiplication result in synchronization with the rising edge of the clock signal. Multiplier 142 outputs the latched multiplication result to rearranger 144. The multiplier 143 multiplies the sampling value output from the distribution switch 141 by “−1”, and latches the multiplication result in synchronization with the rising edge of the clock signal. Multiplier 143 outputs the latched multiplication result to rearranger 144.

Every other sampling value obtained by the analog-digital converter 13 is input to the digital signal processing unit 14-1. The sampling value {X obtained by the analog-to-digital converter 13 is obtained by alternately multiplying “1” and “−1” by the sampling value series input to the digital signal processing unit 14-1. _i , X _{i + 1} , X _{i + 2} , X _{i + 3} ; i = 0, 1, 2, 3,...} are multiplied by “1”, “0”, “−1”, “0”. . On the other hand, in the digital signal processing unit 14-2, the sampling values {X _{i + 1} , X _{i + 2} , X _{i + 3} , X _{i + 4} ; i = 0, 1, 2, 3,. , “1”, “0”, “−1”, “0”. This means that one cycle is multiplied by a sine wave of 4 samples for the series of sampling values input to the digital signal processing unit 14-1. On the other hand, the sampling value series input to the digital signal processing unit 14-2 is multiplied by a sine wave whose phase is shifted by 90 degrees with respect to the sine wave in the digital signal processing unit 14-1. Become. That is, the digital signal processing unit 14-1 performs processing on the in-phase component of the received signal, and the digital signal processing unit 14-2 performs processing on the quadrature component of the received signal.

  The rearranger 144 receives the multiplication result output from the multiplier 142 and the multiplication result output from the multiplier 143. The rearranger 144 outputs two different sets of multiplication results based on the time series of sampling values corresponding to each multiplication result. The rearranger 144 outputs one set of multiplication results of the two sets of multiplication results to the signal processing circuit 145, and outputs the other set of multiplication results to the signal processing circuit 145. The rearranger 144 outputs two sets of multiplication results in synchronization with the rising edge of the clock signal.

  The signal processing circuit 145 and the signal processing circuit 146 sequentially perform digital signal processing on the multiplication results sequentially output from the rearranger 144. The signal processing circuit 145 and the signal processing circuit 146 sequentially output results obtained by the digital signal processing. The signal processing circuit 145 and the signal processing circuit 146 are configured as, for example, an FIR filter or an IIR filter.

  FIG. 2 is a block diagram illustrating a configuration example of the rearranger 144 in the present embodiment. As shown in FIG. 2, the rearranger 144 has seven flip-flops a to g that operate in synchronization with the rising edge of the clock signal. Each of the flip-flops a to g latches and outputs an input value in synchronization with the rising edge of the clock signal.

  The flip-flop a inputs the multiplication result output from the multiplier 142. The flip-flop a outputs the latched value to the flip-flop d. The flip-flop b and the flip-flop c receive the multiplication result output from the multiplier 143. The flip-flop b outputs the latched value to the flip-flop e. The flip-flop c outputs the latched value to the flip-flop f.

  The flip-flop d receives the value output from the flip-flop a. The flip-flop d outputs the latched value to the signal processing circuit 145. The value output from the flip-flop b is input to the flip-flop e. The flip-flop e outputs the latched value to the signal processing circuit 145. The value output from the flip-flop c is input to the flip-flop f. The flip-flop f outputs the latched value to the signal processing circuit 146. The flip-flop g receives the multiplication result output from the multiplier 142. The flip-flop g outputs the latched value to the signal processing circuit 146.

FIG. 3 is a timing chart showing the operation of the digital signal processing unit 14-1 of the present embodiment. In the timing chart shown in FIG. 3, the horizontal axis represents time. The timing chart also shows that the clock signal (DCLK) output from the analog / digital converter 13, the digital signal (DATA _EVEN ) indicating the sampling value output from the analog / digital converter 13, and the distribution switch 141 are multiplied. Output A to the multiplier 142, output B from the distribution switch 141 to the multiplier 143, output of the multiplier 142, output of the multiplier 143, flip-flops d to g (FFd to FFg of the rearranger 144) ) Each output is shown.

In the digital signal (DATA _EVEN ), every other subscript of X _i (i = 0, 2, 4,...) Indicating each sampling value is placed. This is because the analog / digital converter 13 alternately outputs sampling values to the digital signal processing unit 14-1 and the digital signal processing unit 14-2. The sampling value X _i (i = 1, 3, 5,...) Is input to the digital signal processing unit 14-2. Further, since the output of the multiplier 143 is multiplied by “−1”, it is different from the sampling value input to the digital signal processing unit 14-1. However, in FIG. 3, since the value output by each functional unit indicates which sampling value corresponds to the value, each output is indicated by a sampling value X _i .

  The distribution switch 141 distributes digital signals synchronized with both rising and falling edges of the clock signal DCLK to the two multipliers 142 and 143, respectively. The distribution switch 141 distributes to each of the multiplier 142 and the multiplier 143 and extends each sampling value to one cycle of the clock signal DCLK.

As described above, the multiplier 142 multiplies the sampling values (X ₀ , X ₄ , X ₈ ,...) Output from the distribution switch 141 by “1”, and synchronizes with the rising edge of the clock signal DCLK. Update the output value. The multiplier 143 multiplies the sampling values (X ₂ , X ₆ , X ₁₀ ,...) Output from the distribution switch 141 by “−1”, and outputs the output value in synchronization with the rising edge of the clock signal DCLK. Update.

  The value output from the flip-flop d has a delay of two cycles of the clock signal DCLK with respect to the multiplication result output from the multiplier 142. The values output from the flip-flop e and the flip-flop f have a delay corresponding to two cycles of the clock signal DCLK with respect to the multiplication result output from the multiplier 143. The value output from the flip-flop g has a delay of one cycle of the clock signal DCLK with respect to the multiplication result output from the multiplier 142.

  The values output from the flip-flops d and e are output to the signal processing circuit 145 as a set of multiplication results. The values output from the flip-flop f and the flip-flop g are output to the signal processing circuit 146 as a set of calculation results. As shown in FIG. 3, the value input to the signal processing circuit 145 and the value input to the signal processing circuit 146 are shifted by one sample. The period of the values input to the signal processing circuit 145 and the signal processing circuit 146 is twice the period of the sampling value output from the analog / digital converter 13.

Here, the outputs of the signal processing circuit 145 and the signal processing circuit 146 will be described. For example, it is assumed that the signal processing circuit 145 and the signal processing circuit 146 are FIR filters for values based on four sampling values that are continuous in time series. At time _{T A} in FIG. 3, the signal processing circuit 145 outputs the sampling value _{{X 0, X 2, X} 4, X 6} filter result OUT ₀ based on. The signal processing circuit 146 outputs the filter result OUT ₂ based on the sampling values {X ₂ , X ₄ , X ₆ , X ₈ }.

  That is, the digital signal processing unit 14-1 obtains a filter result based on four consecutive sampling values at a certain timing and a filter result based on four consecutive sampling values after one sampling with respect to the four sampling values. Are output at the same timing. In addition, although the case where the filter process based on four continuous sampling values was performed was demonstrated, it is the same also when the filter process based on two continuous sampling values or another continuous number of sampling values is performed.

Although the operation in the digital signal processing unit 14-1 has been described with reference to FIG. 3, the operation in the digital signal processing unit 14-2 is the same. In the timing chart shown in FIG. 3, the sampling values input to the digital signal processing unit 14-1 are {..., X ₀ , X ₂ , X ₄ , X ₆ , X ₈ ,. However, since the analog / digital converter 13 alternately outputs sampling values to the digital signal processing unit 14-1 and the digital signal processing unit 14-2, the sampling value input to the digital signal processing unit 14-2. Becomes {..., X ₁ , X ₃ , X ₅ , X ₇ , X ₉ ,.

  In the receiving apparatus 1 of the present embodiment, the analog / digital converter 13 alternately outputs the sampling values to the digital signal processing unit 14-1 and the digital signal processing unit 14-2, thereby parallelizing the digital signal processing. Yes. By parallelizing digital signal processing, the amount of calculation required for the digital signal processing unit 14-1 and the digital signal processing unit 14-2 can be halved (1/2). In addition, the switching cycle of the digital signals input to the digital signal processing unit 14-1 and the digital signal processing unit 14-2 is set to twice the sampling cycle.

  In the digital signal processing unit 14-1, the distribution switch 141 divides the digital signal of the sampling value input from the analog / digital converter 13 into two systems, and doubles the sampling value switching cycle of each digital signal. ing. That is, the sampling value switching period in the digital signals input to the multiplier 142 and the multiplier 143 is a quarter (1/4) period of the sampling period in the analog-digital converter 13. Yes.

Further, the rearranger 144 rearranges the outputs of the multipliers 142 and 143 and outputs the sampling values of the first group and the second group. The first set of sampling values is a set of multiplication results corresponding to two consecutive sampling values (X _i , X _{i + 2} ). The second set of sampling values is a set of multiplication results corresponding to two consecutive sampling values (X _{i + 2} , X _{i + 4} ) after one sampling with respect to the first set. The signal processing circuit 145 outputs a filter result based on the first set of multiplication results, and the signal processing circuit 146 outputs a filter result based on the second set of multiplication results. Two shifted filter results can be obtained every clock cycle. Similarly, the digital signal processing unit 14-2 can acquire two filter results shifted by one sampling in time series every clock cycle. That is, the receiving apparatus 1 can sequentially acquire four filter results that are continuous in time series every clock cycle.

  In the receiving apparatus 1, the operating frequency required in the signal processing subsequent to the distribution switch 141 is set to a quarter (1/4) of the sampling frequency in the analog / digital converter 13. However, since the digital signal processing unit 14-1 and the digital signal processing unit 14-2 output four filter results every four cycles of the sampling frequency, the receiving apparatus 1 uses the analog / digital converter 13 to output the sampling value. The filter result can be output at the same data rate as the output data rate. With the above-described configuration, the receiving apparatus 1 performs signal processing that maintains real-time characteristics while suppressing the operating frequency in the signal processing circuit 145 and the signal processing circuit 146 to a quarter of the sampling frequency. be able to.

  As described above, according to the receiving apparatus 1, even if the sampling frequency is increased in order to broaden the signal processing target in the received signal, the processing speed in the signal processing circuit 145 and the signal processing circuit 146 is set according to the sampling frequency. It becomes easy to increase the speed. The receiving apparatus 1 can suppress the operating frequency required for the signal processing circuit 145 and the signal processing circuit 146, and can easily maintain the real-time property of the signal processing for the received signal. For example, when the object of reception processing is set to 500 MHz, the sampling frequency in the analog / digital converter 13 is set to 1 GHz. However, the operating frequency required for the signal processing circuit 145 and the signal processing circuit 146 can be suppressed to 250 MHz, and the signal processing result for the reception bandwidth of 500 MHz can be sequentially output with a constant latency.

  By suppressing an increase in the operating frequency, the signal processing circuit 145 and the signal processing circuit 146 can be configured using a programmable logic device such as an FPGA without configuring the dedicated circuit. By using a programmable logic device or the like, it becomes easy to enhance versatility and suppress an increase in cost. Further, the receiving apparatus 1 can be easily applied even when high real-time performance is required in which signal processing is continuously performed on a broadband component included in the received signal and the signal processing result is continuously output.

  As described above, in the receiving apparatus 1, signal processing is performed even when the reception target is widened by making the quadrature demodulation process polyphase type, setting the number of decimation to 2, and performing signal processing using the rearranger 144. The real-time property can be easily maintained.

  In the receiving apparatus 1 in the above-described embodiment, a frequency converter that converts the frequency of the received signal to a low frequency may be provided between the filter circuit 12 and the analog / digital converter 13. Further, in the rearranger 144, signal processing is performed by adding a latency of 2 clock cycles to the multiplication result of the multiplier 143 by either one of the flip-flop b and the flip-flop e and the flip-flop c and the flip-flop f. The data may be output to the circuit 145 and the signal processing circuit 146. For example, when the flip-flop c and the flip-flop f are omitted from the rearranger 144, the flip-flop e outputs the multiplication result of the multiplier 143 to the signal processing circuit 145 and the signal processing circuit 146.

  The receiving device 1 includes two digital signal processing units 14 (14-1 and 14-2) in order to perform orthogonal demodulation processing in parallel, but does not necessarily include two digital signal processing units 14. . For example, the receiving device 1 may include one digital signal processing unit 14 or may include three or more digital signal processing units 14.

According to at least one embodiment described above, a distribution switch that alternately distributes the sampling value of the received signal to the sampling value series A and the sampling value series B, and continuous from the sampling value series A and the sampling value series B in time series. A sampling unit {X _i , X _{i + 2} , X _{i + 4} } that sequentially outputs each time the sampling value of the sampling value series A is output, and a signal based on the sampling value {X _i , X _{i + 2} } By having a signal processing circuit that performs processing and a signal processing circuit that performs signal processing based on the sampling values {X _{i + 2} , X _{i + 4} }, it is easy to increase the signal processing speed according to the wideband of the reception target can do.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 ... Receiver, 10 ... Antenna, 11 ... Low noise amplifier, 12 ... Filter circuit, 13 ... Analog-digital converter, 14, 14-1, 14-2 ... Digital signal processing part, 141 ... Distribution switch, 142 , 143 ... multiplier, 144 ... rearranger, 145, 146 ... signal processing circuit

Claims (2)

An analog-to-digital converter that sequentially outputs a sampling value obtained by sampling a received signal at a predetermined first period;
A first distribution switch that alternately distributes the sampling values output from the analog-digital conversion unit into a first sampling value series and a second sampling value series, and sequentially outputs them;
Each time a sampling value of the first sampling value series is output, the first sampling value of the first sampling value series and the same timing as the first sampling value in the second sampling value series are output. The second sampling value output from the first distribution switch and the third sampling value output next to the first sampling value in the first sampling value series are output at the same timing. A first rearrangement unit;
A first signal processing unit that sequentially outputs signal processing results obtained by signal processing based on the first sampling value and the second sampling value;
A second signal processing unit that sequentially outputs signal processing results obtained by signal processing based on the second sampling value and the third sampling value ;
The first rearrangement unit is:
A clock signal having a rising edge synchronized with an output of a sampling value of the first sampling value series, and an input sampling value in synchronization with a rising edge or a falling edge of the clock signal of the first period Having first to seventh flip-flops to latch;
The first flip-flop inputs a sampling value of the first sampling value series, and outputs a latched sampling value to the second flip-flop,
The second flip-flop receives the sampling value output from the first flip-flop, and outputs the latched sampling value as the first sampling value to the first signal processing unit,
The third flip-flop inputs a sampling value of the second sampling value series, and outputs a latched sampling value to the fourth flip-flop.
The fourth flip-flop receives the sampling value output from the third flip-flop, and outputs the latched sampling value as the second sampling value to the first signal processing unit,
The fifth flip-flop inputs a sampling value of the second sampling value series, and outputs a latched sampling value to the sixth flip-flop.
The sixth flip-flop receives the sampling value output from the fifth flip-flop, and outputs the latched sampling value as the second sampling value to the second signal processing unit,
The seventh flip-flop receives a sampling value of the first sampling value series, and outputs the latched sampling value to the second signal processing unit as the third sampling value;
Receiver device. The first sorting switch, a first multiplier that multiplies sampling values of the second sampling value series output from the first sorting switch by -1, and the first rearrangement. and parts, said first digital signal processing section configured between the first signal processing unit and a second signal processing unit,
A second sorting switch having the same configuration as the first sorting switch, and a second that multiplies the sampling values of the second sampling value series output from the second sorting switch by -1. A multiplier, a second rearrangement unit having the same configuration as the first rearrangement unit, a third signal processing unit having the same configuration as the first signal processing unit, and the second signal A second digital signal processing unit configured to include a fourth signal processing unit having the same configuration as the processing unit,
The analog / digital converter is
A sampling value obtained by sampling the received signal at the first period is alternately distributed to the first digital signal processing unit and the second digital signal processing unit, and output .
The first rearrangement unit outputs the output of the first multiplier as the second sampling value in the first rearrangement unit at the same timing as the first and third sampling values,
The second rearrangement unit outputs the output of the second multiplier at the same timing as the first and third sampling values as the second sampling value in the second rearrangement unit,
The receiving device according to claim 1.

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