JP6079825B2 - Transmission / reception apparatus and transmission / reception method - Google Patents

Description

  The present invention relates to a transmission / reception apparatus and method capable of simultaneously performing transmission and reception.

  Performing transmission and reception at the same time is called full duplex in the field of communication. The full duplex includes, for example, a time division duplex (TDD). In communication by TDD, transmission and reception are switched over time, so transmission and reception in the same frequency band are possible. Although TDD is a kind of full duplex, strictly speaking, transmission and reception are not performed simultaneously. If transmission and reception are performed simultaneously, the transmission signal interferes with the reception signal.

  Non-Patent Document 1 discloses a technique called antenna cancellation in order to cancel interference between a transmission signal and a reception signal. Antenna cancellation uses two transmit antennas and one receive antenna. One of the two transmitting antennas is arranged at a distance d from the receiving antenna, and the other transmitting antenna is arranged at a distance d + λ / 2 (λ is the wavelength of the radio signal) from the receiving antenna. Is done. Therefore, the signals transmitted from the two transmission antennas are in opposite phases at the position of the reception antenna, and the two transmission signals are canceled each other.

Jungll Choi and 4 others, “Achieving Single Channel, Full Duplex Wireless Communication”, [online], published on March 15, 2015, Internet <http: // domecrell. com / view / 88251 />

  For the antenna cancellation of Non-Patent Document 1, the receiving antenna needs to be precisely arranged. For this reason, antenna cancellation is not practical. That is, the receiving antenna needs to be accurately arranged at a position where the signals transmitted from the two transmitting antennas are in opposite phases. If the position of the receiving antenna is slightly shifted, the transmission signal cannot be canceled. From a practical point of view, it is not easy to accurately arrange the two transmission signals at positions where the phases are opposite to each other.

  Therefore, it is desirable to avoid interference of the transmission signal with the reception signal by other methods.

  From a certain viewpoint, the present invention includes a first processing unit that generates a digital signal having a component of an analog transmission signal, and a second processing unit that sets a no-data section in the digital signal in the transmission period of the analog transmission signal. And a third processing unit that samples an analog reception signal in the no-data section.

  From another viewpoint, the present invention generates a digital signal having a component of an analog transmission signal, sets a no-data section in the digital signal in the transmission period of the analog transmission signal, and in the no-data section, A transmission / reception method including sampling an analog reception signal.

  According to the present invention, it is possible to avoid the transmission signal from interfering with the reception signal.

It is a block diagram of a transmission / reception apparatus. It is a circuit diagram of the setting part of a no data section. It is a timing chart which shows a no-data area and sampling timing. It is explanatory drawing regarding emphasis of the harmonic component by the setting of a no-data area. It is explanatory drawing which shows the relationship between a no-data area and sampling timing. It is a block diagram of the transmission / reception apparatus which concerns on a modification. It is a power spectrum of a digital signal including two signal components.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

[1. Outline of Embodiment]
(1) A transmission / reception apparatus according to an embodiment sets a first processing unit that generates a digital signal having a component of an analog transmission signal, and sets a no-data section in the digital signal in a transmission period of the analog transmission signal. 2 processing units, and a third processing unit that samples an analog reception signal in the non-data section. By sampling the analog reception signal in the non-data section set in the transmission period of the analog transmission signal, the analog reception signal can be sampled when the digital signal serving as the transmission signal is not transmitted. Therefore, it is possible to avoid the transmission signal from interfering with the reception signal.

(2) It is preferable that the non-data section is partially set in each data section indicating 1-bit digital data in the digital signal. In this case, even if a no-data section is set in the digital signal, only the harmonic component of the analog transmission signal is emphasized, and the degradation of the analog transmission signal is small.

(3) The transmission / reception apparatus further includes an oscillator used for generating both the first clock signal and the second clock signal, and the first clock signal is used for generating the digital signal by the first processing unit, The second clock signal is preferably used for sampling the analog reception signal by the third processing unit. In this case, since the first clock signal and the second clock signal are generated using a common oscillator, timing fluctuation caused by the oscillator can be prevented from adversely affecting the sampling timing of the analog reception signal. it can.

(4) It is preferable that the second clock signal is obtained by passing a digital signal having a component of the second clock signal through a filter that passes the second clock signal. In this case, since the second clock signal is included as a signal component in the digital signal, the timing fluctuation of the second clock signal is small.

(5) The digital signal generated by the first processing unit further includes a component of the second clock signal, and the second clock signal is a filter that passes the second clock signal through the digital signal. It is preferably obtained by passing it through. In this case, since the second clock signal is included as a signal component in the digital signal having the component of the analog transmission signal, the timing fluctuation between the no-data interval and the sampling timing can be reduced.

(6) It is preferable that the transmission / reception apparatus is for wireless communication. In this case, full duplex in which transmission and reception are performed simultaneously becomes possible. In the present embodiment, unlike TDD, there is no need to switch between transmission and reception by time, so that time resources that can be used for communication increase.

(7) The transceiver may be for radar. In this case, the reflected radar wave can be received while transmitting the lator wave (radio signal for radar). The radar transmission / reception device according to the present embodiment detects a short-distance object because it does not need to stop the transmission of the radar wave and receive the radar wave returned from the reflected radar wave. It is suitable for doing.

  When receiving a radar wave that is reflected back from an object, the transmitted radar wave (transmission signal) must be transmitted to avoid interference with the reflected radar wave (reception signal). I need to stop. However, it takes a little time to stop the transmission of radar waves. For this reason, it is very difficult to stop transmission in a very short time until a reflected radar wave from an object at a short distance that is only a few meters away returns. On the other hand, in this embodiment, since it is not necessary to stop the transmission of radar waves, an object at a short distance can be easily detected.

(8) The transmission / reception method according to the embodiment includes generating a digital signal having a component of an analog transmission signal, setting a no-data section in the digital signal in the transmission period of the analog transmission signal, and the no-data section And sampling the analog received signal.

[2. Details of Embodiment]
FIG. 1 shows a transmission / reception device 10 according to the embodiment. The transmission / reception device 10 is used for radio communication or radar, for example. The wireless communication transceiver 10 transmits and receives communication wireless signals. Wireless communication includes, for example, wireless LAN communication and cellular communication. The radar transceiver 10 transmits and receives radar waves.

  In the transmission / reception apparatus 10 according to the embodiment, the frequency band of the transmission signal and the reception signal is the same, and a full-duplex method in which transmission / reception is performed simultaneously is employed. The transmission / reception apparatus 10 according to the embodiment can receive even in the transmission period, unlike the TDD system that does not receive in the transmission period.

  The transmission / reception device 10 includes a first processing unit 11, a second processing unit 12, and a third processing unit 13. The first processing unit 11 is configured as a digital signal processing unit. The first processing unit 11 performs digital signal processing for transmission / reception. The transmission / reception device 10 includes a transmission antenna 15 and a reception antenna 17. The transmission antenna 15 transmits a radio signal, and the reception antenna 17 receives a radio signal. The illustrated transmission / reception apparatus 10 has separate antennas 15 and 17 for transmission and reception, but may have antennas for both transmission and reception.

The first processing unit 11 generates and outputs a digital radio frequency (DRF) signal. The digital radio signal (DRF signal) is a digitized radio signal (analog transmission signal) to be transmitted from the transmission antenna 17. The DRF signal is a digital signal d _k configured as a 1-bit digital data string, but has a component of a radio signal (analog transmission signal). By using a filter (for example, a bandpass filter) including the frequency band of the radio signal as a pass band, only a desired radio signal can be extracted from the DRF signal.

The first processing unit 11 includes a quadrature modulation unit 11a and a secondary modulation unit 11b in order to generate a DRF signal. The quadrature modulation unit 11a performs quadrature modulation on baseband signals (I signal and Q signal). In FIG. 1, ω ₁ indicates the angular frequency of the carrier wave of the radio signal. The quadrature modulation signal output from the quadrature modulation unit 11a is given to the secondary modulation unit 11b. The secondary modulation unit 11b according to the embodiment is a delta-sigma modulator (Delta-Sigma Modulator). The delta-sigma modulator suppresses the quantization noise by oversampling, and shifts the quantization noise out of the band of the input signal (orthogonal modulation signal) by noise shaping. In an embodiment, the delta sigma modulator is a bandpass type. The delta sigma modulator 11b performs delta sigma modulation on the quadrature modulation signal and outputs a DRF signal. Processing in the quadrature modulation unit 11a and the secondary modulation unit 11b is processing for signal transmission, and is performed as digital signal processing.

  The first processing unit 11 includes a reception signal processing unit 11 c for a reception signal received by the reception antenna 17. The reception signal processing unit 11c performs processing on the digital reception signal obtained by converting the analog reception signal into a digital signal. The reception signal processing unit 11c performs processing such as orthogonal demodulation processing on the digital reception signal, and outputs baseband signals (I signal and Q signal). The received signal processing unit 11c may perform other signal processing such as down-conversion. The processing in the reception signal processing unit 11c is also performed as digital signal processing.

  The transmission / reception device 10 includes a clock generation circuit 19 for generating a clock used in the digital signal processing unit 11. The clock generation circuit 19 includes an oscillator 19a, and generates a necessary clock based on the output of the oscillator 19a.

The first processing unit 11 generates the first clock signal CLK1 _P having the frequency f _S1 and the negative signal CLK1 _N based on the clock output from the clock generation circuit 19. The first clock signal CLK1 _P is given to the secondary modulator 11b as a sampling clock signal for the secondary modulator 11b. The secondary modulator 11b on the basis of the first clock signal CLK1 _P, the sampling frequency of the frequency _{f S1,} oversampling the input signal (quadrature-modulated signal). Therefore, the data rate of the digital signal (ΔΣ modulation signal) output from the secondary modulator 11b is f _S1 [bps]. Note that the oversampling ratio is, for example, about 100 or more.

The first processing unit 11 generates and outputs a digital clock (Digital CLocK; DCLK) signal based on the clock output from the clock generation circuit 19. The digital clock signal (DCLK signal) is obtained by digitizing a second clock signal (sine wave) used as a sampling clock signal for sampling the analog reception signal received by the transmission / reception device 10. The DCLK signal is a digital signal d _k configured as a 1-bit digital data string, but has a sine wave component that is an analog signal. Therefore, by using a filter (for example, a band-pass filter) including the frequency (sampling frequency f _S2 ) of the second clock signal (sine wave) as a pass band, only a desired second clock signal (sine wave) from the DCLK signal. Can be taken out.

The first processing unit 11 includes a clock generation unit 11d and a modulation unit 11e in order to generate a DCLK signal. The clock generation unit 11d has the same configuration as that of the quadrature modulator 11b, and includes a mixer and an adder. An input signal generated based on the clock output from the clock generation circuit 19 is given to the clock generation unit 11d. Input signal supplied to the clock generating unit 11d is a _{cosθ, sinθ, cosω 2 t,} sinω 2 t. The clock generation unit 11d generates and outputs sin (ω ₂ t + θ) based on the input signal. ω ₂ is the angular frequency of the second clock signal (sine wave), and θ is the phase of the second clock signal (sine wave). Note that ω ₂ = 2πf _S2 and f _S2 is the frequency (sampling frequency) of the second clock signal (sine wave). Sin (ω ₂ t + θ) output from the clock generation unit 11d is provided to the modulation unit 11e. The modulation unit 11e according to the embodiment is a delta sigma modulator. In the embodiment, the delta-sigma modulator 11e is a bandpass type. The delta-sigma modulator 11e performs ΔΣ modulation on sin (ω ₂ t + θ) and outputs a DCLK signal. Processing in the clock generation unit 11d and the modulation unit 11e is also performed as digital signal processing.

  The second processing unit 12 performs processing on the DRF signal output from the first processing unit 11. The second processing unit 12 according to the embodiment includes a pulse generator 12a, a setting unit 12b, and a bandpass filter 12c. The output of the second processing unit 12 is given to the transmission antenna 15, and the transmission antenna 15 radiates a radio signal (analog transmission signal). The second processing unit 12 may include an amplifier.

The pulse generator 12a generates a rectangular wave signal waveform S _out corresponding to the DRF signal. When the DRF signal output from the first processing unit 11 has a rectangular waveform, the pulse generator 12a may be omitted.

Setting unit 12b sets the no-data period in the DRF signal _{S out.} Hereinafter, the DRF signal S _out before the no-data interval is set is referred to as a first DRF signal, and the DRF signal S ′ _out where the no-data interval is set is referred to as a second DRF signal. In the second DRF signal S ′ _out in which the no-data section is set, the harmonic component of the radio signal (analog transmission signal) is emphasized compared to the first DRF signal S _out , but the radio signal in the first DRF signal S _out The ingredients are basically kept. The setting unit 12b will be described later.

Bandpass filter 12c from the 2DRF signal S _'out of the no-data period is set is for obtaining a wireless signal includes a frequency band of the radio signal as a pass band. As described above, the DRF signal is a digital signal, but has a component of a radio signal. Therefore, when the second DRF signal S ′ _out passes through the band-pass filter 12c, an analog radio signal is obtained. When the transmission antenna 15 and other elements function as a bandpass filter, the bandpass filter 12c can be omitted. The radio signal output from the bandpass filter 12 c is output from the transmission antenna 15. That is, the transmission antenna 15 outputs the component of the radio signal (analog transmission signal) included in the second DRF signal (digital signal) S ′ _out in which the no-data section is set.

  The third processing unit 13 performs processing on the analog reception signal (radio signal) received by the reception antenna 17. The third processing unit 13 converts the analog reception signal into a digital signal so that it can be processed by the first processing unit 11 which is a digital signal processing unit. The third processing unit 13 according to the embodiment converts the analog reception signal into a digital signal by a direct RF undersampling method. The direct RF undersampling method is described in, for example, Daliso Banda et al. , "Direct RF Under Sampling Reception Method with Lower Sampling Frequency", 2013 Asia-Pacific Microwave Conference Processes, IEEE, 2013.

The third processing unit 13 includes a sample and hold circuit 13a, a low-pass filter 13b, and an AD converter 13c in order to perform direct RF undersampling. Sample-and-hold circuit 13a, a radio signal received is sampled at the sampling frequency f _S2, it maintains the signal value at the sampling until the next sampling. The output of the sample and hold circuit 13a is given to the AD converter 13c via the low pass filter 13b. The AD converter 13c samples the output of the sample and hold circuit 13a at the sampling frequency f _S2 and converts it into a digital signal.

In the direct RF undersampling method, the received radio signal can be sampled at a sampling frequency f _S2 lower than the carrier frequency fc (= ω ₁ / 2π) of the received radio signal. Therefore, the processing speed of the AD converter 13c and the like can be suppressed. If the processing speed of the AD converter 13c can be increased, the sample and hold circuit 13a may be omitted. That is, the third processing unit 13 may sample the analog reception signal and convert it into a digital reception signal by a general AD conversion method.

The third processing unit 13 also performs processing on the DCLK signal output from the first processing unit 11. The third processing unit 13 extracts the second clock signal CLK2 (sin (ω ₂ t + θ)) for sampling the received radio signal (analog reception signal) from the DCLK signal. Therefore, the third processing unit 13 includes a pulse generator 13d and a bandpass filter 13e. The pulse generator 13d generates a rectangular wave signal waveform corresponding to the DCLK signal. When the DCLK signal output from the first processing unit 11 has a rectangular waveform, the pulse generator 13d may be omitted. The band pass filter 13e is for obtaining the second clock signal sin (ω ₂ t + θ) that is a sine wave from the DCLK signal, and includes the frequency f _S2 of the second clock signal as a pass band.

As described above, the DCLK signal is a digital signal, but has a component of the second clock signal sin (ω ₂ t + θ). Therefore, when the DCLK signal passes through the bandpass filter 13e, the second clock signal sin (ω ₂ t + θ) that is a sine wave is obtained. The second clock signal sin (ω ₂ t + θ) output from the bandpass filter 13e is supplied to the sample and hold circuit 13a and the AD converter 13c as a sampling clock. Therefore, the sample and hold circuit 13a and the AD converter 13c perform sampling at the frequency f _s2 = ω ₂ / 2π of the second clock signal sin (ω ₂ t + θ).

FIG. 2 shows the setting unit 12b of the no-data section. The setting unit 12b according to the embodiment includes a three-input AND circuit 121. The 3-input AND circuit 121 is supplied with the first DRF signal S _out , the first clock signal CLK1 _P , and the negative signal (inverted signal) CLK1 _{N of} the first clock signal CLK1 _P as input signals. The length of the signal line L2 of the negative signal (inverted signal) CLK1 _N reaching the AND circuit 121 is such that the negative signal (inverted signal) CLK1 _N has a delay D with respect to the first clock signal CLK1 _P. It is larger than the length of the first clock signal CLK1 _P signal line L1.

3A to 3E show a first DRF signal S _out , a first clock signal CLK1 _P , a negative signal CLK1 _N , a negative signal CLK1 _N having a delay D (delayed CLK1 _N ), and a second DRF signal S, respectively. 'Indicates _out .

In FIG. 3A, d ₁ and d ₂ indicate digital signals in one data section (unit data section) indicating 1-bit digital data in the first DRF signal S _out which is a digital signal. The digital signal dk (k = 1, 2, 3,...) In each data section takes a value of High level or Low level. The time length T of each data section is 1 / f _s1 . Note that f _s1 is the frequency of the first clock signal CKL1 _p shown in FIG. 3B (sampling frequency in the secondary modulation unit 11b). In the first 1DRF signal _{S out,} the entire unit data interval shows 1bit digital data takes a value of High level or Low level.

As shown in FIG. 3C, the negative signal CLK1 _N is a signal obtained by inverting the first clock signal CKL1 _p . As shown in FIG. 3D, the negative signal CLK1 _N having a delay D (delayed CLK1 _N ) is a signal delayed by a delay amount D with respect to the negative signal CLK1 _N. Note that D <T.

FIG. 3E shows the second DRF signal S ′ _out obtained as the logical product of the three signals (S _out , CKL1 _p , and delayed CLK1 _N ) shown in FIGS. 3A, 3B, and 3D. Yes. The second DRF signal S ′ _out indicates 1-bit digital data in the first section in which the first clock CKL1 _p and the delayed negative signal CLK1 _N are both at a high level. In the present embodiment, since the time length of the first section is D and D <T, the section indicating 1-bit digital data is shorter in the second DRF signal S ′ _out than in the first DRF signal S _out .

Further, the second DRF signal S ′ _out is always at the low level in the second section in which at least one of the first clock CKL1 _p and the delayed negative signal CLK1 _N is at the low level. That is, the second section is a no-data section that does not represent 1-bit digital data. Thus, the no-data section is partially set in each data section. For this reason, the first section exists discretely in the time axis direction. In FIG. 3E, the second section (no data section) is provided on the rear side of each unit data section, but may be provided on the front side of each unit data section. It may be provided on both the rear side and the front side of the section.

The setting unit 12b illustrated in FIG. 2 includes a three-input AND circuit 121. When the second section is half the length of each unit data section, two signals (S _out , CKL1 _p ) May be input. As in the present embodiment, the setting unit 12b employs a three-input AND circuit 121, and includes the delayed CLK1 _N in the input to the AND circuit 121, thereby making the second section (no data section) a unit data section. It becomes easy to make it shorter than 1/2 of the length T.

FIG. 4 (A) shows a frequency spectrum of the 1DRF signal _{S out,} FIG. 4 (B) shows a frequency spectrum of the 2DRF signal S _'out.

The first DRF signal S _out has a main signal component at the carrier frequency fc of the quadrature modulation signal input to the secondary modulation unit 11b. This main signal component is a radio signal (analog transmission signal).

The first DRF signal S _out has not only a main signal component of the frequency fc but also a harmonic signal component by folding. The harmonic signal component appears at n × f _S1 + f _c (n is an integer having an absolute value of 1 or more). Harmonic signal components can be used as communication signals.

When the harmonic signal component (for example, frequency f _S1 + fc) is used as the transmission signal (frequency f _target ) output from the transmission / reception device 10, for example, if the frequency of the transmission signal is 3 GHz, the sampling frequency f _S is 3 GHz. It may be smaller than (data rate = 3 Gb / S), for example, 2 GHz. In this case, if the carrier frequency fc of the quadrature modulation signal input to the secondary modulator 11b is 1 GHz, the harmonic signal component (f _target = f _S1 + fc) can be 3 GHz. As described above, when the harmonic signal component is used, it is possible to suppress the operation speed of the first processing unit 11 and reduce the cost as compared with the desired communication frequency f _target .

However, as shown in FIG. 4A, the signal intensity of the harmonic signal component (for example, frequency f _S1 + fc) is greatly reduced compared to the main signal component (frequency fc). When the unit data section length T is 1 / f _{S1 as} in the first DRF signal S _out , the signal component and the noise component gradually decrease from 0 to f _S1 , and the component intensity becomes zero. A notch occurs at frequency f _S1 . Here, the frequency 0 to the frequency f _{S1 is referred} to as a first zone. When the frequency further increases beyond the first zone, the component intensity increases again, but a notch portion is generated where the component intensity becomes zero again at 2f _S1 . Here, the frequency f _S1 to the frequency 2f _{S1 are referred} to as the second zone.
The signal intensity of the harmonic signal component in the second zone is attenuated by about 13.5 dB with respect to the signal intensity of the main signal component in the first zone. In addition, the harmonic signal component generated in the frequency region of 2f _S1 or higher has a signal intensity that is further lowered than the harmonic signal component in the second zone.

Here, the frequency at which the notch portion is generated is determined by the data section length indicating 1-bit digital data, and when the data section length indicating 1-bit digital data is T = 1 / f _{S1 as shown} in FIG. The notch portion occurs at an integer multiple of the data rate (sampling frequency) f _S1 . On the other hand, as shown in FIG. 3E, when the data section length indicating 1-bit digital data is reduced, the frequency at which the notch portion is generated is increased. For example, when the data section length indicating 1-bit digital data is ½ of the unit data section length T, the position of the notch portion with the lowest frequency is 2f _S1 as shown in FIG. . That is, the first zone is extended from 0 to the frequency 2f _S1 .

As a result, the frequency (for example, f _S1 + fc) of the harmonic signal component generated in the frequency region higher than the frequency f _S1 is also included in the first zone. When n is an integer of 2 or more, the component intensity of the nth zone is significantly reduced compared to the component intensity of the first zone. However, by including the harmonic signal in the first zone, it is possible to suppress a decrease in signal strength of the harmonic signal component.

As can be seen from FIG. 4, setting the regular-free data section in each unit data section of the 1DRF signal S _out, only the harmonic components are emphasized, the presence of components of the radio signal is maintained Is done. Even when a no-data section is set without aiming at emphasizing harmonic components, if a no-data section is set sufficiently sparse in a DRF signal composed of a large number of pulses, a no-data section Even if is set, the signal waveform of the analog signal component only needs to be slightly distorted. That is, the individual pulses constituting the DRF signal determine the signal waveform of the analog signal component, but even if a small number of pulses are missing from the many pulses, the signal waveform of the analog signal component Only needs to be slightly distorted.

Returning to FIG. 3, as shown in FIG. 3E, the second DRF signal S ′ _out has a no-data section. When viewed as a digital signal, the no-data section does not transmit digital data. It becomes a transmission section. However, a radio signal (analog transmission signal) whose waveform is formed by a large number of pulses included in the second DRF signal signal S ′ _out is transmitted even in a non-data section (digital data non-transmission section) which is the second section. Will be. That is, the radio signal (analog transmission signal), while the second 1DRF signal S _out is output, regardless of the existence of the no-data period, is transmitted continuously. In other words, the no-data section is set in the transmission period of the radio signal (analog transmission signal).

  The third processing unit 13 according to the present embodiment avoids interference between the transmission signal and the reception signal when transmission and reception are performed simultaneously. In the no-data section in which digital data is not transmitted, the third processing unit 13 ). In the no data section, data that is viewed as a digital signal is not transmitted, so in the sampling section corresponding to the no data section, the received radio signal is sampled to avoid the transmission signal from interfering with the received signal. Can do.

For example, when the analog reception signal shown in FIG. 3F is given from the reception antenna 17 to the sampling and holding circuit 13a, the sampling and holding circuit 13a is determined by the second clock signal sin (ω ₂ t + θ). At the sampling timings T _S1 , T _S2 ..., The analog reception signal value is held and output. As shown in FIG. _3G , the sampling timings T _S1 and T _S2 occur within the sampling section corresponding to the non-data section.

The clock signal may fluctuate due to the oscillator 19a, and it is preferable to avoid the occurrence of the sampling timings T _S1 and T _{S2 in} the first period which is the digital data transmission period due to the fluctuation. In the present embodiment, the first clock signal CLK1 _P that determines the timing of the first interval and the second interval and the second clock signal sin (ω ₂ t + θ) that determines the sampling timings T _S1 and T _S2 are both common. It is generated using the oscillator 19a. Accordingly, fluctuation of timing oscillator 19a causes, in order to occur in the same manner to both the first clock signal CLK1 _P and the second clock signal _{sin (ω 2 t + θ)} , by fluctuation oscillator 19a causes, sampling timing T It is possible to reduce the possibility that _S1 and T _S2 occur in the first section which is the digital data transmission section.

Further, pump ring timing T _S1, T _S2 is to avoid occurring within the first section is a digital data transmission period, the sampling timing T _S1, T _S2 is preferably are as far as possible from the first section . It is preferable that the non-data section is as long as possible so that the sampling timings T _S1 and T _S2 can be greatly separated from the first section.

The positions of the sampling timings T _S1 and T _S2 in the sampling period corresponding to the non-data period can be adjusted by changing the phase θ in the second clock signal sin (ω ₂ t + θ). That is, the positions of the sampling timings T _S1 and T _S2 can be appropriately set by changing the frequencies of cos θ and sin θ input to the clock generation unit 11d in FIG.

In FIG. _3G , the sampling timings T _S1 and T _S2 are drawn so as to occur for each unit data section, but the occurrence frequency of the sampling timings T _S1 and T _S2 is the same as that of the unit data section. It may be less than the occurrence frequency. For example, if the frequency f _S1 of the first clock signal is 2 GHz and the frequency f _S2 of the second clock signal is 100 Hz, one sampling timing is generated in a section corresponding to 20 unit data sections. It's enough. Even when sampling is performed once in a section corresponding to a plurality of unit data sections, as shown in FIG. 5A, each unit data section d ₁ , d ₂ , d ₃ has no data section. Although N1, N2, and N3 are set, sampling is performed in the no-data section N2, but sampling may not be performed in the no-data sections N1 and N3. When sampling is performed once in a section corresponding to a plurality of unit data sections, as shown in FIG. 5B, a no-data section N4 is set only in the unit data section to be sampled. You may make it do.

  As described above, according to the transmission / reception device 10 of the present embodiment, it is possible to prevent the transmission signal from interfering with the reception signal, so that transmission / reception at the same frequency can be performed simultaneously.

  FIG. 6 shows a modification of the transmission / reception device 10 shown in FIG. The first processing unit 11 in FIG. 1 includes two delta sigma modulators 11b and 11e, whereas the first processing unit 11 in FIG. 6 includes a single delta sigma modulator 11f. It is configured. The transmission / reception apparatus 10 in FIG. 6 is the same as the transmission / reception apparatus 10 in FIG.

  The two delta sigma modulators 11b and 11e in FIG. 1 each have one input and one output, whereas the delta sigma modulator 11f in FIG. 6 has two inputs and one output (multiple inputs and one output). A multiple-input single-output delta-sigma modulator is disclosed in, for example, Japanese Patent Application Laid-Open No. 2014-165846. The multi-input single-output delta-sigma modulator can include components of a plurality of analog signals having different frequencies in a single digital signal (ΔΣ modulation signal) to be output.

The two-input one-output delta-sigma modulator 11f shown in FIG. 6 is supplied with the quadrature modulation signal output from the quadrature modulator 11a and sin (ω ₂ t + θ) output from the clock generation unit 11d as two input signals. It is done. The two-input one-output delta sigma modulator 11f outputs a digital signal generated by delta sigma modulation. A single digital signal output from the delta-sigma modulator 11f, the components of the radio signals (analog transmission signal) S _1, and, the second clock signal which is an analog signal (sinusoidal _{wave: sin (ω 2 t + θ} )) S _It has both _two components.

Figure 7 shows the power spectrum of the single digital signal S _out output from the delta-sigma modulator 11f. 7, the frequency of the radio signals _{S 1} is 1500 [MHz], the frequency of the second clock signal _{S 2} is 200 [MHz]. As apparent from FIG. 7, in 1500 [MHz] appears a component of the radio signal _{S 1,} which appears a component of the second clock signal at 200 [MHz].

  The digital signal output from the delta-sigma modulator 11f is given to the second processing unit 12 in FIG. The second processing unit 12 in FIG. 6 is the same as the second processing unit 12 in FIG. Therefore, a radio signal is output from the transmission antenna 15 connected to the second processing unit 12.

The third processing unit 13 in FIG. 6 extracts the second clock signal sin (ω ₂ t + θ) for sampling the received radio signal (analog reception signal) from the digital signal output from the delta-sigma modulator 11f. A band-pass filter 13e connected to the output of the pulse generator 12a of the second processing unit 12 is provided. The band pass filter 13e is for obtaining the second clock signal sin (ω ₂ t + θ) which is a sine wave from the digital signal output from the delta sigma modulator 11f, and the frequency f _S2 of the second clock signal is obtained. It is included as a passband.

Since the digital signal output from the delta-sigma modulator 11f also has a component of the second clock signal sin (ω ₂ t + θ), when passing through the band-pass filter 13e, the second clock signal sin ( ω ₂ t + θ). The second clock signal sin (ω ₂ t + θ) output from the bandpass filter 13e is supplied to the sample and hold circuit 13a and the AD converter 13c as a sampling clock.

In transceiver 10 in FIG. 6, the second clock signal sin (ω ₂ t + θ), since that is included as an analog signal component of the digital signal _{S out,} and a non-data interval that is set in the digital signal _{S out,} the second clock signal It is possible to eliminate almost all of the timing fluctuations occurring between the sampling timings T _S1 and T _S2 determined by sin (ω ₂ t + θ). Therefore, it becomes easy to prevent the sampling timings T _S1 and T _S2 from occurring in the first section which is the digital data transmission section due to the fluctuation caused by the oscillator 19a.

[3. Addendum]
The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the meanings described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

10 Transmission / Reception Device 11 First Processing Unit 11a Orthogonal Modulation Unit 11b Secondary Modulation Unit (Delta Sigma Modulator)
11c Received signal processor 11d Clock generator 11e Modulator (delta-sigma modulator)
11f delta-sigma modulator 12 second processing unit 12a pulse generator 12b setting unit 12c bandpass filter 13 third processing unit 13a sample and hold circuit 13b low-pass filter 13c AD converter 15 transmitting antenna 17 receiving antenna

Claims (8)

A first processing unit having a ΔΣ modulator that generates a digital signal having a component of an analog transmission signal and having a quantization signal shifted outside the frequency band of the analog transmission signal as a 1-bit digital data sequence ;
A second processing unit for setting a no-data section in a data section indicating 1-bit digital data in the 1-bit digital data string ;
A third processing unit that samples an analog reception signal in the no-data interval;
A transmission / reception device comprising: The transmission / reception apparatus according to claim 1, wherein the no-data section is partially set in each data section indicating 1-bit digital data in the digital signal. An oscillator used to generate both the first clock signal and the second clock signal;
The first clock signal is used for generating the digital signal by the first processing unit,
The transmission / reception apparatus according to claim 2, wherein the second clock signal is used for sampling the analog reception signal by the third processing unit. The transmission / reception apparatus according to claim 3, wherein the second clock signal is obtained by passing a digital signal having a component of the second clock signal through a filter that passes the second clock signal. The digital signal generated by the first processing unit further includes a component of the second clock signal,
The transmission / reception apparatus according to claim 3, wherein the second clock signal is obtained by passing the digital signal through a filter that allows the second clock signal to pass therethrough. The transmission / reception apparatus according to any one of claims 1 to 5, wherein the transmission / reception apparatus is for wireless communication. The transmission / reception device according to any one of claims 1 to 5, wherein the transmission / reception device is for radar. Generating a digital signal having a component of an analog transmission signal by ΔΣ modulation and having a quantization noise shifted outside the frequency band of the analog transmission signal as a 1-bit digital data sequence ;
Setting a no-data section in a data section indicating 1-bit digital data in the 1-bit digital data string ;
Sampling the analog received signal in the no-data interval;
A transmission / reception method including: