JP6452943B2 - Frequency comparator - Google Patents

Description

  The present invention relates to a frequency comparator.

  Patent Document 1 discloses a technique for comparing the frequencies of a reference clock signal and a measured clock signal.

JP-A-2-210911

  When comparing the frequencies of the reference clock signal and the clock signal under measurement, it is desirable that the frequency comparison resolution is high.

  On the other hand, when detecting a change in the frequency of the measured clock signal by comparing the frequencies of the reference clock signal and the measured clock signal, it is desirable that the change in the frequency of the measured clock signal can be detected immediately.

  Therefore, the present invention has been made in view of the above points, and immediately detects a change in the frequency of the clock signal to be measured while maintaining the frequency comparison resolution of the reference clock signal and the clock signal to be measured. It aims at providing the technology that can be.

In order to solve the above problems, one aspect of the frequency comparator according to the present invention is synchronized with a first counter that counts a reference clock signal, a second counter that counts a clock signal to be measured, and a sampling signal whose frequency is not changed. Sampling the output value of the first counter, outputting the sampled output value of the first counter, sampling the output value of the second counter in synchronization with the sampling signal, and sampling A second sampling unit that outputs the output value of the second counter, a first cumulative adder that cumulatively adds the output value of the first sampling unit, and a second that cumulatively adds the output value of the second sampling unit. Based on the output values of the cumulative adder, the first and second cumulative adders, and the frequency of the reference clock signal, And a frequency acquisition unit for obtaining the frequency of the constant clock signal, when said output value of said second cumulative adder is changed according to the change of the frequency of the measurement clock signal, the frequency acquisition unit, the output value Before convergence, a change in the frequency of the clock signal to be measured is detected based on the output value .

In the aspect of the frequency comparator according to the present invention, before Symbol second cumulative adder is I FIR type digital filter der, the FIR type digital filter comprises a plurality of latch circuits connected in series, the A plurality of first multipliers, adders, and second multipliers respectively corresponding to the plurality of latch circuits, wherein the first stage latch circuit of the plurality of latch circuits is synchronized with the sampling signal; The output value of the second sampling unit is held and outputted, and among the plurality of latch circuits, each latch circuit except the first stage latch circuit outputs the output value of the previous stage latch circuit in synchronization with the sampling signal. Each of the plurality of first multipliers multiplies the output value of the corresponding latch circuit by a coefficient and outputs the result, and the adder includes the plurality of first multipliers. Output value And, as a result outputs, the second multiplier coefficient multiplies the output value of the adder, and outputs the result as an output value of said second cumulative adder.

The second cumulative adder before Symbol In one embodiment of the frequency comparator according to the present invention I IIR type digital filter der, the IIR type digital filter comprises a first and a second multiplier, an adder, A latch circuit, wherein the first multiplier multiplies the output value of the second sampler by a coefficient and outputs the result, and the adder and the output value of the first multiplier , Adding the output value of the second multiplier and outputting the result, and the latch circuit holds the output value of the adder in synchronization with the sampling signal and outputs the output of the second cumulative adder The second multiplier multiplies the output value of the latch circuit by a coefficient and outputs the result .

  According to one aspect of the present invention, it is possible to immediately detect a change in the frequency of the clock signal to be measured while maintaining the resolution of the frequency comparison between the reference clock signal and the clock signal to be measured.

It is a figure which shows the structure of a frequency comparator. It is a figure which shows the structure of a counter. It is a figure which shows the structure of a sampling part. It is a figure which shows the structure of a cumulative adder. It is a timing chart which shows operation | movement of a frequency comparator. It is a timing chart which shows operation | movement of a comparison object apparatus. It is a figure which shows the structure of the modification of an accumulation adder. It is a timing chart which shows the operation | movement of the modification of a frequency comparator. It is a figure which shows the output characteristic of the accumulation adder comprised by the FIR type digital filter. It is a figure which shows the output characteristic of the accumulation adder comprised by the IIR type digital filter. It is a figure which shows an example of each coefficient of a FIR type digital filter. It is a figure which shows the structure of the frequency comparator which concerns on a modification.

  FIG. 1 is a diagram showing a configuration of a frequency comparator 1 according to the embodiment. The frequency comparator 1 according to the present embodiment compares the frequencies of the reference clock signal rclk and the measured clock signal mclk, and based on the comparison result and the frequency of the reference clock signal rclk, Find the frequency. The frequency comparator 1 is used in a semiconductor device such as a PLL (phase locked loop) circuit, a frequency synthesizer, or a CDR (Clock Data Recovery) circuit provided in the communication device.

  As shown in FIG. 1, the frequency comparator 1 includes counters 2m and 2r, sampling units 3m and 3r, cumulative adders 4m and 4r, and a frequency acquisition unit 5.

  The counter 2m counts the clock signal to be measured mclk, and the counter 2r counts the reference clock signal rclk. Specifically, the counter 2m counts rising edges of the clock signal to be measured mclk. That is, the counter 2m counts up the count value Cm in synchronization with the rising edge of the measured clock signal mclk. Thereby, the count value Cm of the counter 2m is counted up at a speed corresponding to the frequency of the clock signal to be measured mclk. The counter 2r counts rising edges of the reference clock signal rclk. That is, the counter 2r counts up the count value Cr in synchronization with the rising edge of the reference clock signal rclk. As a result, the count value Cr of the counter 2r is counted up at a speed corresponding to the frequency of the reference clock signal rclk.

  The counter 2m may count the falling edge of the measured clock signal mclk, and the counter 2r may count the falling edge of the reference clock signal rclk. Hereinafter, when it is not necessary to particularly distinguish the counters 2m and 2r, each is referred to as "counter 2".

  The sampling unit 3m samples the count value Cm that is the output of the counter 2m in synchronization with the sampling signal sclk that is a kind of clock signal (for example, at the rising edge of the sampling signal sclk). The sampling unit 3r samples the count value Cr that is the output value of the counter 2r in synchronization with the sampling signal sclk (for example, at the rising edge of the sampling signal sclk).

  Here, when the frequency of the sampling signal sclk is fs, the frequency of the clock signal to be measured mclk is fm, and the frequency of the reference clock signal rclk is fr, fs <fm and fs <fr. In the present embodiment, the frequency fs of the sampling signal sclk is, for example, 1/20 times the frequency fr of the reference clock signal rclk.

  Each time the sampling unit 3m samples the count value Cm, the sampling unit 3m obtains and outputs a difference value between the sampled count value Cm and the count value Cm sampled before. That is, the sampling unit 3m outputs an increment of the count value Cm between two consecutive rising edges in the sampling signal sclk. This increment is a value corresponding to the frequency fm of the clock signal to be measured mclk. Similarly, every time the sampling unit 3r samples the count value Cr, the sampling unit 3r obtains and outputs a difference value between the sampled count value Cr and the previously sampled count value Cr. That is, the sampling unit 3r outputs the increment of the count value Cr between two consecutive rising edges in the sampling signal sclk. This increment is a value corresponding to the frequency fr of the reference clock signal rclk. Hereinafter, when it is not necessary to distinguish between the sampling units 3m and 3r, each is referred to as a “sampling unit 3”.

  The cumulative adders 4m and 4r operate in synchronization with the sampling signal sclk. The cumulative adder 4m cumulatively adds the output value Sm of the sampling unit 3m, and outputs a cumulative added value Am obtained thereby. In the present embodiment, the cumulative adder 4m cumulatively adds the output value Sm from the sampling unit 3m a predetermined number of times, and outputs the cumulative added value Am obtained thereby. Since the output value Sm is a value corresponding to the frequency fm of the clock signal to be measured mclk, the cumulative addition value Am is also a value corresponding to the frequency fm. The cumulative adder 4r cumulatively adds the output value Sr of the sampling unit 3r and outputs a cumulative addition value Ar obtained thereby. In the present embodiment, the cumulative adder 4r, like the cumulative adder 4m, cumulatively adds the output value Sr from the sampling unit 3r a predetermined number of times and outputs the cumulative added value Ar obtained thereby. Since the output value Sr is a value corresponding to the frequency fr of the reference clock signal rclk, the cumulative addition value Ar is also a value corresponding to the frequency fr. Hereinafter, when it is not necessary to distinguish the cumulative adders 4m and 4r, each is referred to as "cumulative adder 4".

  The frequency acquisition unit 5 operates in synchronization with the sampling signal sclk. Each time the sampling signal sclk rises, the frequency acquisition unit 5 outputs the cumulative addition value Am output from the cumulative adder 4m, the cumulative addition value Ar output from the cumulative adder 4r, and the frequency fr of the reference clock signal rclk. Based on the above, the frequency fm of the clock signal mclk to be measured is obtained. Specifically, the frequency acquisition unit 5 obtains the frequency fm using the following formula (1).

  The cumulative addition value Am is a value corresponding to the frequency fm of the clock signal to be measured mclk, and the cumulative addition value Ar is a value corresponding to the frequency fr of the reference clock signal rclk. Therefore, the cumulative addition value Am and the cumulative addition value Am Comparing the values Ar is equivalent to comparing the frequencies of the clock signal under measurement mclk and the reference clock signal rclk. Therefore, from the equation (1), the frequency acquisition unit 5 compares the frequencies of the clock signal to be measured mclk and the reference clock signal rclk, and compares the comparison result (Am / Ar) with the frequency fr of the reference clock signal rclk. Based on this, it can be said that the frequency fm of the measured clock signal mclk is obtained. When the frequency comparator 1 obtains the frequency fm of the clock signal to be measured mclk, the frequency comparator 1 notifies the external device of the frequency fm.

  Further, the frequency acquisition unit 5 detects a change in the frequency fm of the clock signal to be measured mclk. Specifically, the frequency acquisition unit 5 determines that the frequency fm has changed when the cumulative addition value Am corresponding to the frequency fm of the clock signal to be measured mclk changes. And if the frequency acquisition part 5 detects the change of the frequency fm, it will notify that to an external device.

<Counter configuration example>
FIG. 2 is a diagram illustrating an example of the configuration of the counters 2m and 2r. Hereinafter, when it is not necessary to distinguish the clock signal to be measured mclk and the reference clock signal rclk, each is simply referred to as “clock signal”. When there is no need to distinguish between the count value Cm and the count value Cr, each is simply referred to as “count value C”.

  As shown in FIG. 2, the counter 2 includes an adder 20 and a latch circuit 21. The adder 20 adds “1” to the output of the latch circuit 21 and outputs the result. The latch circuit 21 holds and outputs the output of the adder 20 in synchronization with the rising edge of the clock signal. The output of the latch circuit 21 becomes the count value C. In such a counter 2, the count value C increases by one in synchronization with the rising edge of the input clock signal. The counter 2 outputs a count value C in synchronization with the rising edge of the clock signal.

<Configuration example of sampling unit>
FIG. 3 is a diagram illustrating an example of the configuration of the sampling units 3m and 3r. Hereinafter, when it is not necessary to distinguish between the output value Sm and the output value Sr, each is simply referred to as “output value S”.

  As shown in FIG. 3, the sampling unit 3 includes latch circuits 30 to 32 and a subtracter 33. The latch circuit 30 holds and outputs the count value C in synchronization with the rising edge of the sampling signal sclk. That is, the latch circuit 30 samples the count value C in synchronization with the sampling signal sclk and outputs it as sampling data CS (k). The sampling data CS (k) means the count value C sampled at the rising edge k of the sampling signal sclk.

  The latch circuit 31 holds and outputs the sampling data CS (k) output from the latch circuit 30 in synchronization with the rising edge of the sampling signal sclk. Since the latch circuit 30 samples the next count value C at the timing when the latch circuit 31 holds the sampling data CS (k), the output of the latch circuit 31 is higher than the count value C sampled by the latch circuit 30. This is the count value C sampled immediately before. Hereinafter, the output of the latch circuit 31 is referred to as “sampling data CS (k−1)”. k−x (x ≧ 1) indicates the rise of the sampling signal sclk x times before k. Further, k + x indicates the rising edge of the sampling signal sclk after x times with respect to k.

  The subtracter 33 subtracts the sampling data CS (k−1) from the latch circuit 31 from the sampling data CS (k) from the latch circuit 30 and outputs the result. The latch circuit 32 holds and outputs the output of the subtracter 33 in synchronization with the rising edge of the sampling signal sclk. The output of the latch circuit 32 becomes the output value S of the sampling unit 3.

  The sampling unit 3 having such a configuration includes a sampled count value C (sampling data CS (k)) and a count value C (sampling data CS (k−1)) sampled one before that. The difference value is obtained by the subtracter 33 and the difference value is output as the output value S. The sampling unit 3 outputs the output value S in synchronization with the rising edge of the sampling signal sclk.

  Sampling data CS (k) and CS (k-1) in the sampling unit 3m are set as sampling data CSm (k) and CSm (k-1), respectively. −1) are sampling data CSr (k) and CSr (k−1), respectively, the output values Sm and Sr are expressed by the following equations (2) and (3).

  Hereinafter, the sampling data CS (k) may be referred to as “count value C (k)”. Further, the sampling data CSm (k), CSm (k-1), CSr (k), CSr (k-1) are converted into "count value Cm (k)", "count value Cm (k-1)", " Sometimes called “count value Cr (k)” and “count value Cr (k−1)”.

<Configuration example of cumulative adder>
FIG. 4 is a diagram showing an example of the configuration of the cumulative adders 4m and 4r. Hereinafter, when it is not necessary to distinguish between the cumulative addition value Am and the cumulative addition value Ar, each is simply referred to as “cumulative addition value A”. In the present embodiment, the cumulative adder 4 is composed of a FIR (Finite Impulse Response) type digital filter. The cumulative adder 4 cumulatively adds the output value S from the sampling unit 3 M times (M is an integer of 2 or more).

  As shown in FIG. 4, the cumulative adder 4 includes M latch circuits 40-1 to 40 -M connected in series, M multipliers 41-1 to 41 -M, and an adder 42. And a multiplier 43. The M latch circuits 40-1 to 40-M constitute an M-stage shift register.

  The first-stage latch circuit 40-1 holds and outputs the output value S in synchronization with the rising edge of the sampling signal sclk. Of the M latch circuits 40-1 to 40-M, each latch circuit 40-j (2 ≦ j ≦ M) except for the first-stage latch circuit 40-1 is synchronized with the rising edge of the sampling signal sclk. The output of the latch circuit 40- (j-1) is held and output. Each multiplier 41-i (1 ≦ i ≦ M) multiplies the output of the latch circuit 40-i by a coefficient αi and outputs the result. The adder 42 adds the outputs of the M multipliers 41-1 to 41-M and outputs the result. The multiplier 43 multiplies the output of the adder 42 by a coefficient αall and outputs the result. The output of the multiplier 43 becomes the cumulative addition value A.

  Here, if the output value S output from the sampling unit 3 in synchronization with the rise k of the sampling signal sclk is S (k), the accumulation output from the accumulation adder 4 in synchronization with the rise k of the sampling signal sclk. The added value A (k) is expressed by the following equation (4).

  In the present embodiment, the following equation (5) is established for the coefficient αall and the coefficient αi.

  For example, when the coefficient αall and the coefficients α1 to αM are all “1”, M samples output from the sampling unit 3 in synchronization with the rising edge (k−M) to the rising edge (k−1) of the sampling signal sclk. The sum of the output values S (k−M) to S (k−1) is output from the cumulative adder 4 in synchronization with the rising k of the sampling signal sclk. Then, in synchronization with the next rising edge (k + 1) of the sampling signal sclk, the cumulative adder 4 calculates the sum of the M output values S (k + 1−M) to S (k) output from the sampling unit 3. Is output.

<Operation of frequency comparator>
FIG. 5 is a timing chart showing an example of the operation of the frequency comparator 1. The counter 2m operates in the same manner as the counter 2r, the sampling unit 3m operates in the same manner as the sampling unit 3r, and the cumulative adder 4m operates in the same manner as the cumulative adder 4r. Therefore, here, the counter 2m, the sampling unit 3m, and The operation of the cumulative adder 4m will be mainly described. Based on FIG. 5, the operation of the counter 2m and the like when the measured clock signal mclk is stopped and then restarted will be described.

  In the example of FIG. 5, the frequency fr of the reference clock signal rclk matches the frequency fm of the clock signal mclk to be measured. In the example of FIG. 5, M = 50. Therefore, the frequency fs of the sampling signal sclk is 1/20 of the frequencies fr and fm. The coefficient αall and the coefficients α1 to αM of the cumulative adder 4 are all “1”. In FIG. 5, in order to illustrate the reference clock signal rclk and the clock signal to be measured mclk, the frequencies fr and fm are smaller than the actual frequency, and the relationship between the frequencies fr and fm and the frequency fs is not correctly shown.

  First, the operation when the measured clock signal mclk is not stopped will be described. In this example, since the frequency fs is 1/20 of the frequency fm, the count value Cm of the counter 2m increases by “20” between two consecutive rising edges in the sampling signal sclk. Therefore, as shown in FIG. 5, the sampling data CS (k) and CS (k−1) in the sampling unit 3m increase by “20” every time the sampling signal sclk rises. Therefore, the output value Sm of the sampling unit 3m, which is the difference value between the sampling data CS (k) and the sampling data CS (k−1), is “20”. In this example, since the cumulative adder 4m cumulatively adds the output value S of the sampling unit 3m 50 times, the cumulative added value Am output from the cumulative adder 4m is “1000”.

  Since the counter 2r, the sampling unit 3r, and the cumulative adder 4r operate in the same manner as described above, in this example in which the frequency fr matches the frequency fm, the cumulative added value Ar output from the cumulative adder 4r is “1000. "

Here, when the cumulative addition value Am deviates even from “1000” by “1”, the frequency fm of the clock signal to be measured mclk changes as shown by the equation (1). Accordingly, in this example, it can be said that the frequency comparison resolution of the reference clock signal rclk and the clock signal to be measured mclk (hereinafter simply referred to as “frequency comparison resolution”) is 1000 ppm (10 ⁻³ ).

  As shown in FIG. 5, for example, when the measured clock signal mclk stops at timing t1 immediately after the rising edge of the sampling signal sclk, in other words, when the frequency fm changes to “0”, the next rising edge of the sampling signal sclk. Thus, the sampling data CS (k) and CS (k−1) have the same value, and the output value Sm of the sampling unit 3m becomes “0” at the next rising edge of the sampling signal sclk. When the output value Sm becomes “0”, the cumulative addition value Am decreases by “20” from the previous value to “980” at the next rising edge of the sampling signal sclk. Thereafter, each time the sampling signal sclk rises, the cumulative addition value Am decreases by “20”, and the cumulative addition value Am eventually becomes “0”.

  After the cumulative addition value Am becomes “0”, for example, when the measured clock signal mclk resumes at timing t2 immediately after the rising of the sampling signal sclk, in other words, when the frequency fm returns to the original value, the sampling signal sclk At the next rise, the sampling data CS (k) becomes larger than the sampling data CS (k−1) by “20”, and at the next rise of the sampling signal sclk, the output value Sm of the sampling unit 3m becomes “20”. . When the output value Sm becomes “20”, the cumulative added value Am increases by “20” from the previous value to “20” at the next rising edge of the sampling signal sclk. Thereafter, each time the sampling signal sclk rises, the cumulative addition value Am increases by “20”, and the cumulative addition value Am eventually becomes “1000”.

  As described above, in the present embodiment, since the output value Sm of the sampling unit 3m is cumulatively added, when the frequency fm of the measured clock signal mclk changes, the cumulative added value Am also changes immediately. To do. Therefore, the frequency acquisition unit 5 can immediately detect a change in the frequency fm of the clock signal to be measured mclk by monitoring the accumulated addition value Am.

  Here, as described above, the frequency fm changes because the measured clock signal mclk stops and the frequency fm becomes “0”, or the measured clock signal mclk resumes and the frequency fm is restored. To include. That is, the change in the frequency fm of the measured clock signal mclk is a concept including the stop and restart of the measured clock signal mclk.

  In the example of FIG. 5, for example, each time the cumulative adder 4m outputs the cumulative addition value Am, the frequency acquisition unit 5 determines whether the cumulative addition value Am has changed by “1” or more with respect to “1000”. If the cumulative addition value Am changes by “1” or more, it is determined that the frequency fm of the clock signal to be measured mclk has changed. That is, if the cumulative addition value Am is not “1000”, the frequency acquisition unit 5 determines that the frequency fm of the clock signal to be measured mclk has changed.

  Further, every time the cumulative adder 4m outputs the cumulative addition value Am Z (≧ 2) times, the frequency acquisition unit 5 calculates the total of the Z cumulative addition values Am, and the total is “1000 × Z It may be determined that the frequency fm of the clock signal to be measured mclk has changed when “Z” or more has changed with respect to “. That is, the frequency acquisition unit 5 may determine that the frequency fm of the clock signal mclk to be measured has changed when the sum is “1000 × Z−Z” or less and “1000 × Z + Z” or more. . In this case, for example, if Z = 2, the frequency acquisition unit 5 calculates the sum of the two cumulative addition values Am every time the cumulative adder 4m outputs the cumulative addition value Am twice, When the total changes by “2” or more with respect to “2000”, it is determined that the frequency fm of the clock signal to be measured mclk has changed. Thereby, even if the cumulative addition value Am changes due to malfunction of the sampling unit 3m or the like, it is possible to suppress erroneous determination that the frequency fm of the clock signal to be measured mclk has changed.

  When the frequency fm of the clock signal mclk to be measured is obtained for the frequency comparator 1 using the technique of the above-mentioned Patent Document 1, if the frequency comparison resolution is set to be the same as that of the present embodiment, A change in the frequency fm of the measurement clock signal mclk cannot be detected immediately. This point will be described below.

  FIG. 6 is a timing chart showing the operation of the apparatus shown in FIG. 1 of Patent Document 1 (hereinafter referred to as “comparison target apparatus”). In the following description, a “reference signal”, “measured signal”, “sampling signal”, The “reference signal frequency fclk” and the “measured signal frequency f” are replaced with the reference clock signal rclk, the measured clock signal mclk, the sampling signal sclk, the frequency fr, and the frequency fm, respectively. “N” and “X” in FIG. 6 indicate outputs of the D-type flip-flops 4 and 9 of the comparison target device, respectively.

  In the comparison target device, the binary counter 3 counts the measured clock signal mclk. The D-type flip-flop 4 samples the count value output from the binary counter 3 at the rising edge of the sampling signal sclk (specifically, the sampling signal sclk synchronized with the measured clock signal mclk) to obtain the wave number N. Output. In the comparison target device, the binary counter 8 counts the reference clock signal rclk. Then, the D-type flip-flop 9 samples the count value output from the binary counter 8 at the rising edge of the sampling signal sclk (specifically, the sampling signal sclk synchronized with the reference clock signal rclk) to obtain the count value X. Output. The arithmetic circuit 10 of the comparison target device obtains the frequency fm of the clock signal to be measured mclk using the following equation (6).

  Here, the wave number N (k) in the equation (6) indicates the count value of the binary counter 3 sampled at the rise k of the sampling signal sclk, and the wave number N (k + 1) is one more than k. The count value of the binary counter 3 sampled at the previous rising edge (k-1) of the sampling signal sclk is shown. The count value X (k) indicates the count value of the binary counter 8 sampled at the rising edge k of the sampling signal sclk, and the count value X (k + 1) is the sampling signal one before k. The count value of the binary counter 8 sampled at the rising edge of sclk (k-1) is shown.

  In such a comparison target device, in order to set the frequency comparison resolution to 1000 ppm as in the example of FIG. 5 described above, the frequency fr is the same between the comparison target device and the frequency comparator 1 according to the present embodiment. Assuming that, the count values of the binary counters 3 and 8 need to increase by “1000” between two consecutive rising edges in the sampling signal sclk. That is, it is necessary to set the frequency fs of the sampling signal sclk to 1/1000 of the frequency fr of the reference clock signal rclk and the frequency fm of the clock signal mclk to be measured. FIG. 6 shows an example of the operation of the comparison target apparatus when the frequency comparison resolution is 1000 ppm, that is, when the frequency fs is set to 1/1000 of the frequencies fr and fm. In FIG. 6, in order to illustrate the reference clock signal rclk and the clock signal to be measured mclk as in FIG. 5, the frequencies fr and fm are smaller than actual, and the relationship between the frequencies fr and rm and the frequency fs is It is not shown correctly.

  In the example shown in FIG. 6, the wave number N changes from “0” to “1000” and the count value X changes from “0” to “1000” in synchronization with the rising k−1 of the sampling signal sclk. Yes. At this time, the frequency fr obtained by the arithmetic circuit 10 is expressed by the following equation (7).

  When the measured clock signal mclk stops immediately after the rising edge k−1 of the sampling signal sclk, the wave number N corresponding to the stopped measured clock signal mclk does not change from “1000” at the next rising edge k of the sampling signal sclk. Thus, the count value X corresponding to the reference clock signal rclk changes from “1000” to “2000”. At this time, the frequency fr obtained by the arithmetic circuit 10 is expressed by the following equation (8).

  Thus, in the comparison target device, the sample value (wave number N) of the output of the binary counter 3 that measures the clock signal mclk to be measured and the sample value (count value X) of the output of the binary counter 8 that measures the reference clock signal rclk. ) Are used as they are, and the frequency fm is obtained. Therefore, when setting the frequency comparison resolution to 1000 ppm, it is necessary to set the frequency fs to 1/1000 of the frequencies fr and fm. Therefore, when the measured clock signal mclk stops immediately after the rising edge of the sampling signal sclk, it can be detected that the measured clock signal mclk has stopped until about 1000 rising edges of the reference clock signal rclk are counted from the rising edge. Can not. That is, if the frequency fm changes immediately after the rise of the sampling signal sclk, it cannot be detected that the frequency fm has changed until about 1000 rises of the reference clock signal rclk are counted from the rise. On the other hand, if the frequency fm is increased in order to immediately detect that the frequency fm has changed in the comparison target device, the frequency comparison resolution decreases.

  On the other hand, in the frequency comparator 1 according to the present embodiment, the frequency fm is obtained by using the cumulative addition value A obtained by cumulatively adding the output values S of the sampling unit 3, and therefore the sampling signal sclk. Even if the frequency fs is set larger than that of the comparison target device, the frequency comparison resolution equivalent to that of the comparison target device can be maintained. In the above example, M = 50, the frequency fs in the frequency comparator 1 is 50 times the frequency fs in the comparison target device, and the frequency comparison resolution in the frequency comparator 1 is the comparison target device. The same 1000ppm.

  Thus, in the frequency comparator 1 according to the present embodiment, even if the frequency fs of the sampling signal sclk is made larger than that of the comparison target device, the same frequency comparison resolution as that of the comparison target device can be obtained. A change in the frequency fm of the clock signal to be measured mclk can be detected immediately while maintaining the resolution.

  In the above example, M = 50 and the frequency fs of the sampling signal sclk is 1/20 of the frequency fr of the reference clock signal rclk. However, these values are merely examples, and the value of M and the frequency fs are What is necessary is just to determine suitably based on required frequency comparison resolution.

  In the above example, the change in the frequency fm is detected based on the cumulative addition value Am. However, the change in the frequency fm may be detected based on the frequency fm obtained by the frequency acquisition unit 5. In the above example, the frequency acquisition unit 5 detects a change in the frequency fm. However, an external device may detect a change in the frequency fm. In this case, the external device may detect a change in the frequency fm based on the frequency fm obtained by the frequency acquisition unit 5 and output from the frequency comparator 1, or may be output from the frequency comparator 1. A change in the frequency fm may be detected based on the cumulative addition value Am.

  Also in the frequency comparator 1 according to the present embodiment, the sampling signal sclk is synchronized with the clock signal to be measured mclk and input to the sampling unit 3m, and the sampling signal sclk is input to the reference clock signal rclk as in the comparison target device. And may be input to the sampling unit 3r in synchronization.

<Various modifications>
<First Modification>
In the above example, the cumulative adder 4 is an FIR type digital filter, but may be an IIR (Infinite Impulse Response) type digital filter. FIG. 7 is a diagram showing an example of the configuration of the cumulative adder 4 of the frequency comparator 1 according to this modification. The frequency comparator 1 according to this modification is obtained by changing the configuration of the cumulative adder 4 in the frequency comparator 1 described above.

  As shown in FIG. 7, the cumulative adder 4 according to this modification is an IIR digital filter, and includes multipliers 45 and 48, an adder 46, and a latch circuit 47. The multiplier 45 multiplies the output value S by a coefficient α and outputs the result. The adder 46 adds the output of the multiplier 45 and the output of the multiplier 48 and outputs the result as an output value Ai. The latch circuit 47 holds and outputs the output value Ai from the adder 46 at the rising edge of the sampling signal sclk. The multiplier 48 multiplies the output of the latch circuit 47 by a coefficient (1-α / M) and outputs the result. The output of the latch circuit 47 becomes the cumulative addition value A.

  With respect to the cumulative adder 4m according to the present modification having such a configuration, when the input output value Sm is constant, the following equation (9) is established.

  The following formula (10) is obtained from the formula (9).

  Similarly, for the cumulative adder 4r according to this modification, the following equation (11) is established when the input output value Sr is constant.

  As can be understood from the equation (10), when the output value Sm is constant, that is, when the frequency fm of the clock signal mclk to be measured is constant, the cumulative addition value Am is M times the output value Sm. . As can be understood from the equation (11), when the output value Sr is constant, that is, when the frequency fr of the reference clock signal rclk is constant, the cumulative addition value Ar is M times the output value Sr. Become.

  FIG. 8 is a timing chart showing an example of the operation of the frequency comparator 1 according to this modification. Based on FIG. 8, the operations of the counter 2m, the sampling unit 3m, and the cumulative adder 4m when the measured clock signal mclk is stopped and then restarted will be mainly described.

  In the example of FIG. 8, the frequency fr of the reference clock signal rclk and the frequency fm of the clock signal to be measured mclk coincide with each other as in the example of FIG. 5 described above, and the frequency fs of the sampling signal sclk is the frequency fr. , Fm and 1/20. The coefficient α of the cumulative adder 4m is “1”, and M = 50. In FIG. 8, in order to illustrate the reference clock signal rclk and the clock signal to be measured mclk, the frequencies fr and fm are smaller than the actual frequency, and the relationship between the frequencies fr and rm and the frequency fs is not correctly shown. Hereinafter, the output value Ai generated inside the cumulative adder 4m according to the present modification is referred to as “output value Ami”.

  As described above, when the measured clock signal mclk does not stop and the frequency fm is constant, the cumulative addition value Am is M times the output value Sm. Therefore, as shown in FIG. 8, the cumulative addition value Am is “1000”. Similarly, the cumulative addition value Ar is “1000”.

  As shown in FIG. 8, when the measured clock signal mclk stops at timing t11 immediately after the rising edge of the sampling signal sclk, the sampling data CS (k) and CS (k−1) are the same at the next rising edge of the sampling signal sclk. The output value Sm of the sampling unit 3m becomes “0” at the next rising edge of the sampling signal sclk. When the output value Sm becomes “0”, the output value Ami generated inside the cumulative adder 4m decreases by “20” from “1000” to “980”. When the output value Ami becomes “980”, the cumulative addition value Am becomes “980” at the next rising edge of the sampling signal sclk. When the cumulative addition value Am becomes “980”, the output value Ami becomes “960.4”. When the output value Ami becomes “960.4”, the cumulative addition value Am becomes “960.4” at the next rising edge of the sampling signal sclk. Thereafter, the cumulative addition value Am becomes “941.192”, and thereafter becomes “932.368”. Thereafter, each time the sampling signal sclk rises, the cumulative addition value Am decreases, and the cumulative addition value Am eventually becomes “0”.

  When the measured clock signal mclk resumes at timing t12 immediately after the rising of the sampling signal sclk after the cumulative addition value Am becomes “0”, the sampling data CS (k) becomes the sampling data CS at the next rising of the sampling signal sclk. It becomes larger than (k−1) by “20”, and the output value Sm of the sampling unit 3m becomes “20” at the next rising edge of the sampling signal sclk. When the output value Sm becomes “20”, the output value Ami changes from “0” to “20”. When the output value Ami becomes “20”, the cumulative addition value Am changes from “0” to “20” at the next rising edge of the sampling signal sclk. When the cumulative addition value Am becomes “20”, the output value Ami becomes “39.6”. When the output value Ami becomes “39.6”, the cumulative addition value Am becomes “58.808” at the next rising edge of the sampling signal sclk. Thereafter, each time the sampling signal sclk rises, the cumulative addition value Am increases, and the cumulative addition value Am eventually becomes “1000”.

  By configuring the cumulative adder 4 with an IIR digital filter as in this modification, the circuit scale of the cumulative adder 4 can be made smaller than when the cumulative adder 4 is configured with an FIR digital filter. be able to.

<Second Modification>
In the above example, when the cumulative adder 4 is configured by an FIR type digital filter, the values of the coefficient αall and the coefficients α1 to αM are all “1”, but the values of the coefficient αall and the coefficients α1 to αM are Other than that.

  In the above example, when the cumulative adder 4 is configured by an IIR digital filter, the value of the coefficient α is “1”, but the value of the coefficient α may be other than this.

  FIG. 9 is a diagram illustrating a change in the output of the cumulative adder 4m configured by the FIR digital filter when the clock signal under measurement mclk is stopped. FIG. 10 is a diagram illustrating a change in the output of the cumulative adder 4m configured with an IIR digital filter when the measured clock signal mclk is stopped. 9 and 10, the horizontal axis indicates the number of rising of the reference clock signal rclk after the measured clock signal mclk stops, and the vertical axis indicates the cumulative addition value Am.

  The graph 100 shown in FIG. 9 shows the cumulative addition value Am when M = 50 and the values of the coefficient αall and the coefficients α1 to α50 are all set to “1”. A graph 101 shown in FIG. 9 shows the cumulative addition value Am when M = 50 and the values of the coefficient αall and the coefficients α1 to α50 are set as shown in FIG. A graph 102 shown in FIG. 9 shows how the wavenumber N changes when the measured clock signal mclk stops in the comparison target device.

  A graph 110 shown in FIG. 10 shows the cumulative addition value Am when the coefficient α is “1”. A graph 111 in FIG. 10 shows the cumulative addition value Am when the coefficient α is “5”. A graph 112 shown in FIG. 10 shows how the wave number N changes when the measured clock signal mclk stops in the comparison target device.

  As shown in FIG. 9, when the values of the coefficient αall and the coefficients α1 to α50 are all set to “1” (graph 100), the values of the coefficient αall and the coefficients α1 to α50 are as shown in FIG. The accumulated addition value Am becomes smaller than “1000” immediately after the measured clock signal mclk is stopped, compared to the case where it is set (graph 101). Therefore, when the values of the coefficients αall and α1 to α50 are all set to “1” (graph 100), the values of the coefficients αall and the coefficients α1 to α50 are set as shown in FIG. 11 (graph). 101), the frequency acquisition unit 5 can immediately detect that the frequency fm of the clock signal to be measured mclk has changed.

  On the other hand, when the values of the coefficient αall and the coefficients α1 to α50 are set as shown in FIG. 11 (graph 101), the values of the coefficient αall and the coefficients α1 to α50 are all set to “1” ( From the graph 100), the cumulative addition value Am becomes zero immediately after the measured clock signal mclk stops. Therefore, when the values of the coefficient αall and the coefficients α1 to α50 are set as shown in FIG. 11 (graph 101), the values of the coefficients αall and the coefficients α1 to α50 are all set to “1” (graph). 100), the frequency acquisition unit 5 can immediately obtain the current frequency fm of the clock signal to be measured mclk.

  Further, as shown in FIG. 10, when the coefficient α is set to “5” (graph 111), the measured clock is larger than the case where the coefficient α is set to “1” (graph 110). As soon as the signal mclk stops, the cumulative addition value Am becomes zero. Therefore, when the coefficient α is set to “5” (graph 111), convergence is faster than when the coefficient α is set to “1” (graph 110), and the frequency acquisition unit 5 The current frequency fm of the clock signal mclk can be determined immediately.

  As described above, since the coefficient αall and the coefficients α1 to αM and the coefficient α are changed, the change in the cumulative addition value AM when the frequency fm of the clock signal mclk to be measured is changed. By appropriately setting the coefficients α1 to αM and the coefficient α, it is possible to obtain a characteristic according to the purpose with respect to the change characteristic of the cumulative added value Am when the frequency fm of the clock signal to be measured mclk changes. For example, when the cumulative adder 4m is composed of an FIR type digital filter, when it is desired to immediately detect that the frequency fm has changed, the values of the coefficient αall and the coefficients α1 to α50 are all set to “1”. When it is desired to obtain the frequency fm immediately, the values of the coefficient αall and the coefficients α1 to α50 are set as shown in FIG. Further, for example, when the cumulative adder 4m is formed of an IIR digital filter, the coefficient α is set to “5” when it is desired to immediately obtain the current frequency fm.

<Third Modification>
FIG. 12 is a block diagram showing the configuration of the frequency comparator 1 according to this modification. In the above example, the sampling unit 3 outputs the difference value between the sampled count value C (k) and the count value C (k−1) sampled before that. The counted value C (k) is output as it is. The output values output from the sampling units 3m and 3r according to this modification are referred to as “output value S′m” and “output value S′r”, respectively. Further, when it is not necessary to distinguish the output values S′m and S′r, each is referred to as “output value S ′”.

  The cumulative adder 4 according to the present modification cumulatively adds the output value S ′ output from the sampling unit 3 as described above. Therefore, the cumulative adder 4 outputs a cumulative added value of the sampled count value C (k). The cumulative addition values output from the cumulative adders 4m and 4r according to this modification are referred to as “cumulative addition value A′m” and “cumulative addition value A′r”, respectively. Further, when it is not necessary to distinguish the cumulative addition values A′m and A′r, each is referred to as “cumulative addition value A ′”.

  The frequency acquisition unit 5 according to the present modification obtains the frequency fm of the clock signal to be measured mclk based on the cumulative addition values A′m, A′r and the frequency fr of the reference clock signal rclk. Hereinafter, an example of how to obtain the frequency fm in this modification will be described.

  In the following description, it is assumed that the cumulative adder 4 is composed of the FIR type digital filter shown in FIG. However, the cumulative adder 4 in this modification example has one more latch circuit. That is, the cumulative adder 4 according to this modification includes (M + 1) latch circuits 40-1 to 40- (M + 1) connected in series and (M + 1) multipliers 41-1 to 41- ( M + 1). The latch circuit 40- (M + 1) holds and outputs the output of the preceding latch circuit 40-M in synchronization with the rising edge of the sampling signal sclk, and the multiplier 41- (M + 1) outputs the latch circuit 40-M. The output of (M + 1) is multiplied by a coefficient α (M + 1), and the result is output. The adder 42 adds the outputs of (M + 1) multipliers 41-1 to 41- (M + 1) and outputs the result. The multiplier 43 multiplies the output of the adder 42 by a coefficient αall and outputs the result. The output of the multiplier 43 becomes the cumulative addition value A ′. In the following description, it is assumed that the coefficients α1 to α (M + 1) and the coefficient αall are all set to “1”.

  The frequency acquisition unit 5 according to the present modification obtains a value Wm (k) represented by the following expression (12) and a value Wr (k) represented by the following expression (13).

  Here, the value Wm (k) matches the cumulative addition value Am (k) in the above example, and the value Wr (k) matches the cumulative addition value Ar (k) in the above example.

  For example, M = 5, and the count value Cm sampled at six consecutive rising edges U-6 to U-1 of the sampling signal sclk in the sampling unit 3m is “20”, “40”, “60”. , “80”, “100”, and “120”. That is, the output values S′m (U-6), S′m (U-5), S′m (U-4), S′m (U-3), S′m (U-2), S It is assumed that 'm (U−1) is “20”, “40”, “60”, “80”, “100”, and “120”, respectively.

  In such a case, the difference values between the sampled count value Cm (k) and the previously sampled count value Cm (k−1) are all “20”. The added value Am is “100”. Then, the value Wm (k) represented by the equation (12) is “100”, which is consistent with the cumulative addition value Am.

  In this modification, as shown in FIG. 12, the output values S′m and S′r output from the sampling units 3 m and 3 r are input to the frequency acquisition unit 5. The frequency acquisition unit 5 calculates the value Wm (k) using Expression (12), and calculates the value Wr (k) using Expression (13). Then, the frequency acquisition unit 5 substitutes the obtained two values Wm (k) and Wr (k) into the following equation (14) to obtain the frequency fm of the measured clock signal mclk.

  As in the above example, the sampling unit 3 outputs the difference value between the sampled count value C (k) and the count value C (k−1) sampled before that. Compared with the case where the count value C (k) sampled by the sampling unit 3 is output as it is as in the modification, the calculation processing in the frequency acquisition unit 5 is simplified.

  As mentioned above, although the frequency comparator 1 was demonstrated in detail, above-described description is an illustration in all the phases, Comprising: This invention is not limited to it. The various modifications described above can be applied in combination as long as they do not contradict each other. And it is understood that the countless modification which is not illustrated can be assumed without deviating from the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 Frequency comparator 2,2m, 2r Counter 3,3m, 3r Sampling part 4,4m, 4r Cumulative adder 5 Frequency acquisition part

Claims (3)

A first counter for counting a reference clock signal;
A second counter for counting the clock signal under measurement;
A first sampling unit that samples the output value of the first counter in synchronization with a sampling signal whose frequency is not changed, and outputs the sampled output value of the first counter;
A second sampling unit that samples the output value of the second counter in synchronization with the sampling signal, and outputs the sampled output value of the second counter;
A first cumulative adder for cumulatively adding the output values of the first sampling unit;
A second cumulative adder for cumulatively adding the output values of the second sampling unit;
A frequency acquisition unit that obtains the frequency of the clock signal under measurement based on the output values of the first and second cumulative addition units and the frequency of the reference clock signal ;
When the output value of the second cumulative adder changes in response to a change in the frequency of the clock signal to be measured, the frequency acquisition unit performs the measurement based on the output value before the output value converges. A frequency comparator that detects changes in the frequency of the measurement clock signal . The frequency comparator according to claim 1, comprising:
Before Stories second accumulation adder I FIR type digital filter der,
The FIR type digital filter is
A plurality of latch circuits connected in series;
A plurality of first multipliers respectively corresponding to the plurality of latch circuits;
An adder;
With a second multiplier
Have
The first stage latch circuit among the plurality of latch circuits holds and outputs the output value of the second sampling unit in synchronization with the sampling signal,
Among the plurality of latch circuits, each latch circuit except the first-stage latch circuit holds and outputs the output value of the previous-stage latch circuit in synchronization with the sampling signal,
Each of the plurality of first multipliers multiplies the output value of the corresponding latch circuit by a coefficient, and outputs the result,
The adder adds the output values of the plurality of first multipliers, and outputs the result,
The second multiplier is a frequency comparator that multiplies the output value of the adder by a coefficient and outputs the result as an output value of the second cumulative adder . The frequency comparator according to claim 1, comprising:
Before Stories second accumulation adder IIR type digital filter der,
The IIR type digital filter is:
First and second multipliers;
An adder;
Latch circuit and
Have
The first multiplier multiplies the output value of the second sampler unit by a coefficient and outputs the result.
The adder adds the output value of the first multiplier and the output value of the second multiplier, and outputs the result,
The latch circuit holds the output value of the adder in synchronization with the sampling signal and outputs it as the output value of the second cumulative adder,
The second multiplier is a frequency comparator that multiplies the output value of the latch circuit by a coefficient and outputs the result .

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