JP3128828B2 - MSK demodulation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MSK demodulation circuit used in a modulation / demodulation system of a digital satellite communication system.
In particular, the present invention relates to an MSK demodulation circuit capable of removing the phase uncertainty of the MSK demodulation circuit and facilitating an interface with an error correction device (FEC) connected to an output.

[0002]

2. Description of the Related Art In general, modulation and demodulation methods in satellite communication are as follows.
Although the QPSK method is widely used, it is well known that the MSK method shows better characteristics in a nonlinear region.

Conventionally, in this type of MSK modulation / demodulation system, as shown in FIG. 3, an MSK modulation unit is composed of a differential converter 51, a serial / parallel converter 52, and an MSK modulator 53, and the MSK demodulation unit is MSK demodulation. , A parallel / serial converter 55, and a differential converter 56.

First, an MSK modulator 53 and a demodulator 54 in the MSK modulation / demodulation system will be described with reference to the configuration diagrams of FIGS. 4 and 5, respectively. In FIG. 4, I-channel baseband signal I1A and 1 / 4f _s frequency Ich clock and (ICLK) are multiplied by the multiplier 101 to generate an output signal I1B. Here, ICLK is further divided into two by a frequency divider 103 at a frequency f _S / 2 to obtain 1/4 f _S. This divided signal is subjected to LPF 104 to remove harmonics and
/ 4f _S clock is supplied. This output signal I1B
And carrier signal (assuming amplitude 1) of angular frequency w _O cos
W _O t is multiplied by the multiplier 106 to obtain an output signal I1C. On the other hand, in the side of the Q channel, 1 / 4f Qch clock QCLK and Q-channel baseband signals Q1A and a multiplied by the multiplier 102 output signal shifted 90 degrees by the clock 90 degree phase shifter 105 frequency _S Q
1B has been obtained. The carrier signal si by a carrier signal cosW _O t a 90 degree shift to 90-degree phase shifter 108
nWOt is generated. The multiplier 107 is a multiplier 107
In the output signal Q1C is obtained by multiplying the Q1B and sinW _O t. The combiner 109 combines the output signals I1C and Q1C to obtain an MSK modulated signal S (t). This MSK modulated signal S (t) is represented by the following equation (1).

[0005] will be described with reference to FIG. 5 the structure and operation of the _{S (t) = IcosW S /} 4 · cosW O t + QsinW S / 4 · sinW O t ... (1) Next MSK demodulator 54. The MSK modulated signal S (t) input to the MSK demodulator 54 is split into two by the divider 201, and one output is set to I2A and the other output signal Q2A.
Both I2A and Q2A are S (t) shown by equation (1). Then I2A in multiplier 202 reproduced carrier circuit (not shown) by the reproducing carrier signal cos (W _O t + φ)
Detected by This detection signal is subjected to LPF 205 to remove harmonics, sampled by a clock input RCLK by an A / D converter 207, A / D converted, and converted into a digital signal I2B. Similarly, the output signal Q2A represented by S (t) in the equation (1) is detected by the multiplier 203 by the 90-degree phase shifter 204 by sin (W _O t + φ) in which the phase of the RCAR is delayed by 90 degrees, and LP
Harmonics are removed by F206. This output signal is sampled by the A / D converter 208 using the clock whose clock RCLK is delayed by 90 degrees by the 90-degree phase shifter 209, A / D converted, and the digital signal Q2
B. Here, the cos of the reproduced carrier signal
(W _O t + φ) and sin (W _O t + φ) in the phase φ
Is the phase difference with respect to the carrier on the sending side, which is generated when the carrier is reproduced. On the receiving side, φ is 0, + π / 2, −
It is not known which of π / 2 and π, which causes phase uncertainty.

On the other hand, the digital signals I2B, Q2B
Is multiplied by the clock of the frequency f _S / 4 divided by the 分 frequency divider 210 by the multipliers 211 and 212, respectively.
Ich digital signals I2 whose phases are different from each other by 90 degrees
The C and Qch digital signals Q2C are output. This I2
C and Q2C are RCL by flip-flops 214 and 215
By sampling the timing in phase with K, the Ich digital signals I2D, Qch
A digital signal Q2D is obtained. This I2D, Q2D
The signal format of φ = 0, φ = + π / 2, -π /
2, four types of demodulated signals are generated for each case of φ = 0, which is shown in FIG. That is, when φ = 0, I2D501 and Q2D502 are obtained, and φ = π / 2
, I2D 503 and Q2D 504 if φ = π, I2D 505 and I2D 506 if φ = π, and I2D 507 and Q2D 508 if φ = −π / 2. As shown in FIG. 6, the signal format of Q2D 504 is
11 has a 1-bit phase lag with respect to 11, and Q2
Similarly, in the signal format of D508, the bar I11 is delayed by one bit in phase with respect to the bar Q11 indicating the inverted signal of the I2D507. Where φ = 0, φ = π / 2, φ =
Demodulated signal sequences corresponding to phases of π, φ = −π / 2 are shown in FIG. 6 as (I1, Q1), (Q1D, I1),
(Bar I1, Bar Q1) and (Bar Q1D, Bar I1).

Next, the conventional method for removing the phase uncertainty is, as shown in FIG. 3, described above, before and after the MSK modulator 53 and the MSK demodulator 54, the differential converters 51 and 56 and the serial / By providing the parallel converter 52 and the parallel / serial converter 55, phase uncertainty is removed. That is, (I1, Q1) (Q1
D, I1), if it is determined by the P / S converter 55 that the data received by the Ich at the time of the P / S conversion is past data, the converted signal d3 becomes one type of 601 in FIG. (Bar I1, Bar Q1) (Bar Q1D, Bar I
Since 1) is one type of 602 in FIG. 7, there are only two types of d3.

Next, the differential converters 51 and 56 are respectively shown in FIG.
As shown in the block diagrams of FIGS.
1, 703 and 1-bit delay circuits 702 and 704. In the differential converter 51, when an input signal is represented by xn and an output signal is represented by Xn, Xn = xn + X
The conversion of (n-1) is performed, and when the input / output signals are represented by Xa and xa, xa = Xa + X
The conversion (a-1) is performed. As described above, if there is no signal error during transmission from the output of the differential converter 51 to the input of the differential converter 56, Xa = Xn or Xa =
Since it is the bar Xn (see FIG. 9), the input signal xn and the output signal xa are equal, only one d2 in FIG. 3 exists, and there is no phase uncertainty.

As described above, in the case of the conventional MSK method, the receiving end finally becomes one series of data and the phase uncertainty can be removed.

[0010]

The conventional MSK described above.
In the demodulation circuit, since a differential converter is used to eliminate the phase uncertainty generated on the receiving side, there is a disadvantage that a 1-bit error is spread to a 2-bit error. Further, in this method, the phase uncertainty is removed from the output signal after the differential conversion. Therefore, when interfacing with a forward error correction device (FEC) having a coding rate R = 1/2, the FEC of the FEC is not used. Since the decoder input is a two-sequence input, there is a disadvantage that it is necessary to further perform S / P conversion, and two types of phase uncertainty are generated again.

[0011]

In the MSK demodulation circuit of the present invention, two series of demodulated signals of an I channel signal and a Q channel signal are converted into four phase uncertain carrier signals of a reproduced carrier signal for each of an I channel and a Q channel. Four kinds of baseband signals of baseband signals "I, Q" or "QD, I" or "bar I, bar Q" or "bar QD, bar I" (QD signal is a signal delayed by one bit from Q signal) In the MSK demodulation circuit having an MSK demodulator that outputs any one of the baseband signals, any one of the four baseband signals is input and the “I,
Q ”,“ QD, I ”,“ bar I, bar Q ”,“ bar I,
A phase having a signal generator for generating four kinds of signals of bar QD "and a selector having an I-channel and Q-channel output locked by selecting one of the four kinds of signals by a selection signal from outside. A forward error correction circuit for inputting an output signal of the phase converter and performing error correction; and inputting a signal of an error correction result of the forward error correction circuit and an output signal of the phase converter to input a phase. And a control circuit for determining whether the error is correct or not, and outputting a selection signal when the determination value is better than a predetermined threshold value of the error correction result to lock the operation of the phase converter.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a circuit diagram of a phase converter 1 as a main part of the present embodiment. In the embodiment shown in FIG. 1, the MSK demodulator 1 which receives the MSK modulated signal S (t) output from the MSK modulator 53 described in the conventional example and performs the same operation as the MSK demodulator 54, and the MSK demodulator 1 Input signals I1 and Q1 of the
1 and Q1, a phase converter 2 having a selector for generating four digital signals, which will be described later, and sequentially selecting the four digital signals to output digital signals I2 and Q2. , Q2 and a decoded signal EC indicating the error correction result of the forward error correction (FEC) device 4, and correct digital signals I2, Q2 with reduced errors are determined from the four digital signals I2, Q2 to perform phase conversion. And a control circuit 3 for locking the selector of the device 2.

Next, the operation of this embodiment will be described. As described in the conventional example, the MSK demodulator 1 outputs the reproduced carrier signal RC
Due to the uncertainty of AR phase φ, φ = 0, + π / 2, -π
Under the four conditions of / 2 and π, in addition to the same (I1, Q1) as the baseband signal input from the transmission shown in FIG. 6, (Q1D, I1), (I1, Q1), (Q1D) , Bar I1).

As shown in FIG. 2, the phase converter 2 generates two I1's for directly outputting the baseband signal I1 and two inverted signals I1 'by the inverters 7 and 10. The baseband signal Q1 is directly output Q1 ', a baseband signal QD' delayed by one bit through a one-bit delay circuit 6, and the baseband signal QD 'is inverted via an inverter 8 to an inverted signal Q2'. And an inverted signal Q 'is generated via the inverter 9. Here, four baseband signals (I1, IQ) shown in FIG.
(Q1D, I1), (bar I1, bar Q1), (bar Q
1D, bar I1) is generated in a pseudo manner and output from the selector 5.

Next, an FEC4, which is an error correction circuit having a coding rate R = 1/2 shown in FIG. 1, is a series of decoded signals obtained as a result of performing error correction on each of the above four baseband signals. Output EC. If the value of the phase φ is not the correct phase, an error correction decode signal that is considerably worse than the error correction decode signal in the case of the correct phase is output.

Next, the control circuit 3 converts the decoded signal EC into an encoded signal by an encoder, compares it with a baseband signal before error correction, and compares the error correction effect. Therefore, the phases of I1 and Q1 of the MSK demodulator 1 are detected from the signals from both of them, and if it is determined to be correct, a command is issued to the phase converter 2 to keep the phase as it is. Issue a command to select another phase. By continuing until the phase is determined to be correct,
The correct phase is selected at most for the fourth time. For determining the error correction effect of the control circuit 3, a synchronization determiner is built in, and the signal before FEC4 and the signal after FEC4 are R = 1/2.
By comparing the signals re-encoded in the above and giving the result to the synchronization determiner, the synchronization determiner instructs the phase converter 2 to select another phase when the number of errors exceeds a certain threshold. If you do not exceed the threshold,
Keep the phase as it is.

As described above, the selector 5 of the phase converter 2 holds the signal determined to have the correct phase φ among the four signals whose phases are undefined.

[0019]

As described above, the present invention includes a phase converter having two input / output terminals connected to the output of the MSK demodulator, an FEC, and a control circuit, thereby providing a conventional device. Since the differential converter is not used, there is an effect that the phase uncertainty in the MSK method can be removed without deteriorating the bit error rate. In addition, since it has a two-output phase converter, the interface with the FEC becomes easy.

[Brief description of the drawings]

FIG. 1 is a block diagram of an MSK demodulation circuit showing one embodiment of the present invention.

FIG. 2 is a circuit diagram of a phase converter showing a main part of the present embodiment.

FIG. 3 is a configuration diagram of a conventional MSK modulation / demodulation method.

FIG. 4 is a configuration diagram of an MSK modulator according to the related art and the present embodiment.

FIG. 5 is a configuration diagram of an MSK demodulator according to the related art and the present embodiment.

FIG. 6 shows a signal format common to the related art and the present embodiment.

FIG. 7 is a signal format illustrating a conventional example.

FIG. 8 is a circuit diagram of a conventional differential converter.

[Explanation of symbols]

 Reference Signs List 1 MSK demodulator 2 Phase converter 3 Control circuit 4 Error correction circuit (FEC) 5 Selector 6 1-bit delay circuit 7 to 9 Inverter

Claims (2)

(57) [Claims] 1. A baseband signal “I, Q” or “QD” for each of I-channel and Q-channel, wherein two-phase demodulated signals of an I-channel signal and a Q-channel signal are formed by four types of phase-indetermined carrier signals of a reproduced carrier signal. , I "or" bar I, bar Q "or" bar QD, bar I "(QD signal is a signal delayed by one bit from Q signal) and outputs any one of four baseband signals. An MSK demodulator circuit having an MSK demodulator that performs one of the above four types of baseband signals and inputs “I, Q”, “QD, I”, “I, Q”,
A signal generator for generating four types of signals "bar I, bar QD", and a selector having I channel and Q channel outputs locked by selecting one of the four types of signals by a selection signal from the outside; And a forward error correction circuit for inputting an output signal of the phase converter and performing error correction, and a signal of an error correction result of the forward error correction circuit and an output signal of the phase converter. A control circuit that determines whether the phase is correct by inputting or incorrect, outputs a selection signal in the case of a determination value that is better than a predetermined error correction result threshold value, and locks the operation of the phase converter. An MSK demodulation circuit, comprising: 2. An inverter in which a signal generator of the phase converter receives baseband signals of I channel and Q channel and generates two inverted signals of I channel and one inverted signal of Q channel, respectively. And a 1-bit delay circuit for generating a signal for delaying the baseband signal of the Q channel by 1 bit, and an inverter for generating an inverted signal from an output signal of the 1-bit delay circuit. MSK demodulation circuit.