JPH0326133A - Bpsk demodulating system - Google Patents

Abstract

PURPOSE:To demodulate a BPSK intermediate frequency modulated wave input signal with a digital processing by obtaining a synchronizing with the clock pulse signal of the period of 1/2 of the period of an intermediate frequency modulated wave and comparing it with the phase of the signal bisecting the frequency of the clock pulse signal. CONSTITUTION:A pulse generating circuit 4 generates the clock pulse signal Sc of the period of 1/2 of a frequency fc of an IF modulated wave signal Sa to be inputted and gives it to the input terminal of a D flip-flop circuit 3. A frequency dividing circuit 5 bisects the frequency of the clock pulse signal Sc and outputs a pulse signal Sf. A phase comparator 6 compares the phases of both signal Sd and Sf to be inputted and outputs a digital signal Sg to go to a low level when the phase difference is 0 and to go to a high level when the phase difference is pi, respectively. The BPSK IF modulated wave input signal Sa to be IF-modulated in such a manner is digitally processed, demodulated and outputted as the digital signal Sg.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention provides input B P S K (Binary
PhaseShift Keying: relates to a BPSK demodulation method that digitally processes an intermediate frequency modulated wave and outputs it as a digital signal.

(Conventional technology and issues to be solved) In the field of wireless communications, digital systems are being adopted in order to be economical and provide a variety of communication services, and one of these digital wireless systems is digital modulation technology. be. And, as a digital modulation technology, 2
There are digital phase modulation (PSK) techniques such as phase and four-phase.

As a BPSK demodulation method for demodulating this BPSK modulated signal, there is a carrier wave recovery method using multiplication, etc. as a general method.

Conventionally, however, such a carrier wave regeneration method is performed using an analog circuit, which requires adjustment of the circuit. Further, there are problems such as not only the circuit configuration being complicated but also the shape of the circuit becoming relatively large.

The present invention has been made in view of the above-mentioned points.
To provide a BPSK demodulation method that can digitize a PSK intermediate frequency modulated wave (referred to as an IF modulated wave) and obtain data output by latching it with a digital carrier wave, thereby making it possible to use an IC in a demodulation circuit and eliminate adjustment. With the goal.

(Means for Solving the Problems) In order to achieve the above object, according to the present invention, a BPSK intermediate frequency modulated wave is digitized, and a clock having a period of 1/2 of the intermediate frequency period of the intermediate frequency modulated wave is digitized. The digitized signal is synchronized by a pulse signal, and the phase of the digitized and synchronized signal is compared with the phase of a signal formed by dividing the frequency of the clock pulse signal by two to obtain data output. be.

(Function) After digitizing the input BPSK intermediate frequency modulated wave, the digitized signal is synchronized by a clock pulse signal with a period of 1/2 of the period of the BPSK intermediate frequency modulated wave, and the synchronized digital signal is Data output is obtained by comparing the phase of the signal with the phase of a signal obtained by dividing the frequency of the clock pulse signal by two. In this way, the BPS that can be input
The K intermediate frequency modulated wave is digitally processed and demodulated to obtain data output.

(Example) An embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 shows a BPSK intermediate frequency demodulation circuit 1 for implementing the present invention, and a slicer 2 of the demodulation circuit 1 digitizes an input intermediate frequency modulated wave (hereinafter referred to as rTF modulated wave) Sa and converts it into a pulse signal. sb, and the output pulse signal sb is input to the input terminal D of a latch circuit, for example, a D flip-flop circuit 3. The signal Sd output from the output terminal Q of this D flip-flop 3 is input to the phase comparator 6. Note that the frequency of the IF modulated wave signal Sa is f1.

The pulse generator 4 circuit 4 receives the frequency 16 of the IF modulated wave signal Sa.
For period T = 1/2f. It generates and outputs a clock pulse signal Sc. This clock pulse signal Sc is a pulse signal s obtained by digitizing the IF modulated wave Sa.
This is a carrier wave for synchronizing the D flip-flop circuit 3 and is input to the input terminal CK of the D flip-flop circuit 3.

On the other hand, the pulse signal Sc output from the pulse generation circuit 4
is input to the frequency dividing circuit 5. This frequency dividing circuit 5 divides the frequency of the clock pulse signal Sc into 1/2 and outputs a pulse signal Sf, which is applied to a phase comparator 6. The phase comparator 6 compares the phase of the input signal Sd and the phase of the signal Sf,
When the phase difference is 0, a low level data signal Sg is output, and when the phase difference is π, a high level data signal Sg is output.

The operation will be explained below with reference to the timing chart shown in FIG.

For example, the BPSK IF modulated signal Sa has a phase difference of 01π, 010, π, etc. as shown in FIG. 2(a).
・Assume that the input is changed as follows. The slicer 2 receives and digitizes the IF modulated signal Sa (FIG. 2(a)), and, for example, a pulse signal Sb (
It is converted into the image shown in FIG. 2(b)) and output. Furthermore, Fig. 2(a)
, (0) corresponds to a low level, and (1) corresponds to a high level.

On the other hand, the pulse generation circuit 4 generates an IF modulated wave signal S
The frequency f of a. A clock pulse signal Sc (FIG. 2(C)) with a period of 1/2 (T=1/2f.) is generated and D
It is applied to the input terminal CK of the flip-flop circuit 3. This D flip-flop circuit 3 latches the input clock pulse signal sb every time the pulse signal Sc is input and outputs it as a signal Sd (FIG. 2(d)). Thereby, the pulse signal sb digitized and outputted by the slicer 2 is made into a signal Sd synchronized with the clock pulse signal Sc.

The frequency dividing circuit 5 divides the frequency of the clock pulse signal SC by 1/2.
The pulse signal Sf (FIG. 2(e)) is output. Therefore, this pulse signal Sf becomes a signal that is synchronized with the signal Sd that is synchronized with the clock pulse signal Sc. The phase comparator 6 receives both input signals Sd and S.
It compares the phase with f and outputs a digital signal Sg (FIG. 2(f)) which is at a low level when the phase difference is 0, and at a high level ε when the phase difference is π.

The BPSK IF modulated wave input signal Sa (FIG. 2(a)) subjected to IF modulation in this manner is digitally processed and demodulated, and is output as a digital signal Sg (FIG. 24(f)).

(Effects of the Invention) As explained above, according to the present invention, a BPSK intermediate frequency varying wave is digitized, and the digitization is performed using a clock pulse signal having a period of 1/2 of the period of the intermediate frequency of the intermediate frequency modulated wave. The data output is obtained by synchronizing the digitalized and synchronized signal and comparing the phase of the digitalized and synchronized signal with the phase of the signal formed by dividing the clock pulse signal by two. The BPSK intermediate frequency modulated wave input signal can be demodulated by digital processing, and as a result, the demodulation circuit can be implemented as a digital IC, which makes it possible to downsize the demodulation circuit and eliminate adjustment. Become. This has excellent effects such as making it possible to reduce the cost of a demodulation circuit for a BPSK intermediate frequency modulated wave signal.

[Brief explanation of drawings]

Figure 1 shows a BP to which the BPSK demodulation method according to the present invention is applied.
FIG. 2 is a block diagram showing an embodiment of a demodulation circuit for an SK modulated wave signal, and FIG. 2 is a timing chart showing an embodiment of the signal waveform of the demodulation circuit of FIG. ■...BPSK demodulation circuit, 2...Slicer, 3...
・D flip-flop, 4... pulse generation circuit, 5.
... Frequency divider circuit, 6... Phase comparator.

Claims (1)

[Claims] A BPSK intermediate frequency modulated wave is digitized, the digitized signal is synchronized with a clock pulse signal having a period of 1/2 of the intermediate frequency period of the intermediate frequency modulated wave, and the digitized and synchronized signal is A BPSK demodulation system characterized in that data output is obtained by comparing the phase with the phase of a signal formed by dividing the frequency of the clock pulse signal by two.