JPS588240U - phase synchronized circuit - Google Patents

phase synchronized circuit

Info

Publication number
JPS588240U
JPS588240U JP10156081U JP10156081U JPS588240U JP S588240 U JPS588240 U JP S588240U JP 10156081 U JP10156081 U JP 10156081U JP 10156081 U JP10156081 U JP 10156081U JP S588240 U JPS588240 U JP S588240U
Authority
JP
Japan
Prior art keywords
voltage
sample
output
waveform
hold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10156081U
Other languages
Japanese (ja)
Other versions
JPH028444Y2 (en
Inventor
俊 伊藤
健 大西
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP10156081U priority Critical patent/JPS588240U/en
Publication of JPS588240U publication Critical patent/JPS588240U/en
Application granted granted Critical
Publication of JPH028444Y2 publication Critical patent/JPH028444Y2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の位相同期回路のブロック図を示す。第2
図〜第4図は同期信号の周波数変化による第1図の位相
同期回路の各回路部の出力波形図を示す。ポ5図はこの
考案の一実施例の位相同期  、回路のブロック図を示
す。 図において、1は電圧制御発振回路、2は波形発生器、
3はサンプルホールド回路、4は低域フィルタ、6はサ
ンプル制御回路を示す。 補正 昭56. 9.19 実用新案登録請求の範囲を次のように補正する。 O実用新案登録請求の範囲 位相同期回路において、 制御電圧に応じた周波数で発振動作する電圧制御発振手
段、 前記電圧制御発振手段の出力周波数に同期して三角波を
発生する波形発生手段、 前記波形発生手段出力をサンプルホールドしまたはサン
プルするサンプルホールド手段、同期信号が与えられる
毎に前記サンプルホールド手段に前記波形発生手段の出
力電圧をサンプルホールドさせ、かつ前記同期信号が所
定時間入力されない状態に基づシ)て同期信号の入力さ
れない期間中前記サンプル手段に前記波形発生手段の出
力電圧をサンプルさせるサンプル制御手段、および 前記サンプルホールド手段の出力電圧を平滑化しかつ平
滑した電圧を前記制御電圧として前記電圧制御発振手段
に4是る平滑手段を備えた、位相同期回路。
FIG. 1 shows a block diagram of a conventional phase locked circuit. Second
4 to 4 show output waveform diagrams of each circuit section of the phase-locked circuit shown in FIG. 1 due to changes in the frequency of the synchronizing signal. Figure 5 shows a block diagram of a phase synchronization circuit according to an embodiment of this invention. In the figure, 1 is a voltage controlled oscillation circuit, 2 is a waveform generator,
3 is a sample hold circuit, 4 is a low-pass filter, and 6 is a sample control circuit. Correction 1984. 9.19 The scope of claims for utility model registration is amended as follows. O Utility Model Registration Claims In a phase-locked circuit, voltage-controlled oscillation means operates in oscillation at a frequency according to a control voltage, waveform generation means generates a triangular wave in synchronization with the output frequency of the voltage-controlled oscillation means, and the waveform generation sample and hold means for sampling and holding the output of the means; and sample and hold means for sampling and holding the output voltage of the waveform generating means each time a synchronization signal is applied, and based on a state in which the synchronization signal is not input for a predetermined period of time. c) sample control means for causing the sample means to sample the output voltage of the waveform generation means during a period in which a synchronization signal is not input; and a sample control means for smoothing the output voltage of the sample hold means and using the smoothed voltage as the control voltage. A phase synchronized circuit equipped with four smoothing means in the controlled oscillation means.

Claims (1)

【実用新案登録請求の範囲】 位相同期回路において、 制御電圧に応じた周波数で発振動作する電圧制御発振手
段、 前記電圧制御発振手段の出力周波数に同期して三角波を
発生する波形発生手段、 前記波形発生手段出力をサンプルホールドしまたはサン
プルするサンプルホールド手段、前記同期信号が与えら
れる毎に前記サンプルホールド手段に前記波形発生手段
の出力電圧をサンプルホールドさせ、かつ同期信号が所
定時間入力されない状態に基づいて同期信号の入力され
ない期間中前記サンプルホールド手段に前記波形発生−
手段の出力電圧をサンプルさせるサンプル制御手段、お
よび、 前記サンプルホールド手段の出力電圧を平滑化しかつ平
滑した電圧を前記制御電圧として前記電圧制御発振手段
に与える平滑手段を備えた、位相同期回路。
[Claims for Utility Model Registration] In a phase-locked circuit, voltage-controlled oscillation means operates in oscillation at a frequency according to a control voltage, waveform generation means generates a triangular wave in synchronization with the output frequency of the voltage-controlled oscillation means, and the waveform sample-and-hold means for sampling and holding the output of the generating means; each time the synchronization signal is applied, the sample-and-hold means samples and holds the output voltage of the waveform generation means; and based on a state in which the synchronization signal is not input for a predetermined period of time; During the period when no synchronization signal is input, the sample and hold means generates the waveform.
A phase synchronized circuit comprising: sample control means for sampling the output voltage of the means; and smoothing means for smoothing the output voltage of the sample and hold means and applying the smoothed voltage to the voltage controlled oscillation means as the control voltage.
JP10156081U 1981-07-07 1981-07-07 phase synchronized circuit Granted JPS588240U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10156081U JPS588240U (en) 1981-07-07 1981-07-07 phase synchronized circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10156081U JPS588240U (en) 1981-07-07 1981-07-07 phase synchronized circuit

Publications (2)

Publication Number Publication Date
JPS588240U true JPS588240U (en) 1983-01-19
JPH028444Y2 JPH028444Y2 (en) 1990-02-28

Family

ID=29896221

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10156081U Granted JPS588240U (en) 1981-07-07 1981-07-07 phase synchronized circuit

Country Status (1)

Country Link
JP (1) JPS588240U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6315992U (en) * 1986-07-17 1988-02-02

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5310415A (en) * 1976-07-15 1978-01-30 Olympus Optical Co Ltd Winding of tape on hub of magnetic tape cassette

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5310415A (en) * 1976-07-15 1978-01-30 Olympus Optical Co Ltd Winding of tape on hub of magnetic tape cassette

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6315992U (en) * 1986-07-17 1988-02-02

Also Published As

Publication number Publication date
JPH028444Y2 (en) 1990-02-28

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