JPS58184932U

JPS58184932U - phase synchronized oscillator

Info

Publication number: JPS58184932U
Application number: JP8110782U
Authority: JP
Inventors: 一条　幸吉
Original assignee: 日本電気株式会社
Priority date: 1982-06-01
Filing date: 1982-06-01
Publication date: 1983-12-08

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は従来の位相同期発振器を示すブロック−図、第
２図は第１図の動作を示す波形図、第３図は本考案の実
施例を示すブロック図、第４図は第３図の動作を示す波
形図である。１・・・・・・常用人力クロック信号入力端子、２・・
曲予備入カクロック信号入力端子、３・・曲信号断検出
部、４・・・・・・入力切替え部、５・・・・・・分周
器、６・・・・・・位相比較器、７・・・・・・分周器
、８・・・・・・低域沖波器、９・・・・・・周波数可
変発振器、１０・・・・・・出力端子、１１・・・・・
・時限パルス発生部、１２・・・・・・周波数逓倍回路
。Fig. 1 is a block diagram showing a conventional phase synchronized oscillator, Fig. 2 is a waveform diagram showing the operation of Fig. 1, Fig. 3 is a block diagram showing an embodiment of the present invention, and Fig. 4 is a block diagram showing the operation of Fig. 1. FIG. 2 is a waveform chart showing the operation of FIG. 1... Regular human input clock signal input terminal, 2...
Song pre-input clock signal input terminal, 3... Song signal disconnection detection unit, 4... Input switching unit, 5... Frequency divider, 6... Phase comparator, 7... Frequency divider, 8... Low frequency wave generator, 9... Frequency variable oscillator, 10... Output terminal, 11...
- Timed pulse generator, 12... Frequency multiplier circuit.

Claims

[Scope of utility model registration request]

A phase comparator with two manual inputs and one output, a detection unit that detects disconnection of the regular manual clock signal, and a l/n of the regular clock signal.
A frequency-divided (n is an integer of 2 or more) clock signal is input to one side of the phase comparator, and when the detection section detects disconnection of the regular clock signal, the frequency-divided clock signal is divided by l/n of the standby manual clock signal. an oscillator that changes the frequency of the output clock signal according to the output of the phase comparator; In a phase synchronized oscillator having a frequency divider serving as the other input of a phase comparator, the input means is driven by the output of the signal loss detection section, and the signal loss detection section operates for a time approximately equal to the operation time thereof. a timed pulse generator for generating a timed pulse with a width of 1/2, and a timed pulse generator which is driven by this timed pulse and which outputs a timed pulse of the preparatory input clock signal while the timed pulse is applied;
A phase synchronized oscillator comprising means for inputting an n-frequency divided clock signal to one input of the phase comparator.