JPS6181243U - - Google Patents
Info
- Publication number
- JPS6181243U JPS6181243U JP16562684U JP16562684U JPS6181243U JP S6181243 U JPS6181243 U JP S6181243U JP 16562684 U JP16562684 U JP 16562684U JP 16562684 U JP16562684 U JP 16562684U JP S6181243 U JPS6181243 U JP S6181243U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- input digital
- digital signal
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001934 delay Effects 0.000 claims 1
- 230000000630 rising effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Description
第１図は本考案の一実施例の構成を示すブロツ
ク図。第２図は本考案の一実施例の作用の説明に
供す波形図。第３図は本考案の一実施例の変形例
を示すための付加回路図。
２…遅延回路、３…Ｄ型フリツプフロツプ、４
…位相比較器、５…ローパスフイルタ、６…電圧
制御発振器。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a waveform diagram for explaining the operation of an embodiment of the present invention. FIG. 3 is an additional circuit diagram showing a modification of one embodiment of the present invention. 2...Delay circuit, 3...D flip-flop, 4
...Phase comparator, 5...Low pass filter, 6...Voltage controlled oscillator.
Claims (1)
したクロツク信号を抽出するビツト同期回路にお
いて、位相比較器、ローパスフイルタおよび電圧
制御発振器を有するＰＬＬ回路と、前記入力デジ
タル信号を遅延させる遅延回路と、前記電圧制御
発振器と位相比較器との間に挿入され、前記電圧
制御発振器の出力をクロツク信号としかつ前記入
力デジタル信号を入力するＤ型フリツプフロツプ
とを備え、前記遅延回路の出力と前記Ｄ型フリツ
プフロツプの出力の立上りまたは立下りとを前記
位相比較器で位相比較することを特徴とするビツ
ト同期回路。 A bit-synchronized circuit extracting a clock signal phase-synchronized with a bit rate in an input digital signal includes a PLL circuit having a phase comparator, a low-pass filter, and a voltage-controlled oscillator, a delay circuit that delays the input digital signal, and the voltage control circuit. A D-type flip-flop is inserted between the oscillator and the phase comparator, and uses the output of the voltage-controlled oscillator as a clock signal and receives the input digital signal, and the output of the delay circuit and the output of the D-type flip-flop are connected to each other. A bit synchronization circuit characterized in that the phase of a rising edge or a falling edge is compared by the phase comparator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16562684U JPH0247653Y2 (en) | 1984-11-02 | 1984-11-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16562684U JPH0247653Y2 (en) | 1984-11-02 | 1984-11-02 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6181243U true JPS6181243U (en) | 1986-05-29 |
| JPH0247653Y2 JPH0247653Y2 (en) | 1990-12-14 |
Family
ID=30723466
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16562684U Expired JPH0247653Y2 (en) | 1984-11-02 | 1984-11-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0247653Y2 (en) |
-
1984
- 1984-11-02 JP JP16562684U patent/JPH0247653Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0247653Y2 (en) | 1990-12-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6181243U (en) | ||
| JPS61191657U (en) | ||
| JPS62164651U (en) | ||
| JPS5848140U (en) | Trigger synchronization control circuit | |
| JPS58119243U (en) | phase synchronized oscillator | |
| JPS6286740U (en) | ||
| JPS588240U (en) | phase synchronized circuit | |
| JPS60108045U (en) | pulse shaping circuit | |
| JPS59104636U (en) | frequency synthesizer | |
| JPS61103936U (en) | ||
| JPS5849285U (en) | timer clock circuit | |
| JPS6150346U (en) | ||
| JPS5948143U (en) | phase synchronized oscillator | |
| JPH0275846U (en) | ||
| JPS583643U (en) | Pulse transmitter | |
| JPS6085442U (en) | phase synchronized circuit | |
| JPS6040149U (en) | Phase comparator for bit-synchronized PLL | |
| JPS6068742U (en) | automatic frequency control circuit | |
| JPS62129854U (en) | ||
| JPS58169735U (en) | phase lock droop circuit | |
| JPS6370715U (en) | ||
| JPS6123785U (en) | Time axis correction device | |
| JPS60132666U (en) | Dropout compensation circuit for PLL circuit | |
| JPS6019238U (en) | FM signal generator | |
| JPS60145738U (en) | Synchronous circuit for asynchronous signals and pulse signals |