JPS58169735U - phase lock droop circuit - Google Patents

phase lock droop circuit

Info

Publication number
JPS58169735U
JPS58169735U JP6396682U JP6396682U JPS58169735U JP S58169735 U JPS58169735 U JP S58169735U JP 6396682 U JP6396682 U JP 6396682U JP 6396682 U JP6396682 U JP 6396682U JP S58169735 U JPS58169735 U JP S58169735U
Authority
JP
Japan
Prior art keywords
circuit
phase
loop filter
differential
phase lock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6396682U
Other languages
Japanese (ja)
Other versions
JPH0339948Y2 (en
Inventor
文彦 横川
Original Assignee
パイオニア株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パイオニア株式会社 filed Critical パイオニア株式会社
Priority to JP6396682U priority Critical patent/JPS58169735U/en
Publication of JPS58169735U publication Critical patent/JPS58169735U/en
Application granted granted Critical
Publication of JPH0339948Y2 publication Critical patent/JPH0339948Y2/ja
Granted legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のＰＬＬ回路のブロック図、第２図及び第
３図は本考案の実施例を夫々示す回路図である。 主要部分の符号の説明、１・・・位相比較器、２・・・
ｖｃｏ、、３・・・ループフィルタ、４・・・差動スイ
ッチ回路、５．６・・・カレントミラー回路。FIG. 1 is a block diagram of a conventional PLL circuit, and FIGS. 2 and 3 are circuit diagrams showing embodiments of the present invention. Explanation of symbols of main parts, 1... Phase comparator, 2...
vco, 3... Loop filter, 4... Differential switch circuit, 5.6... Current mirror circuit.

Claims (1)

【実用新案登録請求の範囲】 二重平衡型差動アンプ構成の乗算器からなる位相比較器
と、前記位相比較器による比較出力を入力とするループ
フィルタと、前記ループフィルタの出力により制御され
る電圧制御型発振器とを有するフェイズロッドループ回
路であって、前記二重平衡型差動アンプの中力電流を電
流源とする差動スイッチ回路を有し、２前記差動スイッ
チ回路の１対の差動出力を前記ループフィルタの時定数
を決定するインピーダンス素子へ夫々接続し、前記差動
スイッチ回路を制御信号により制御して回路の動作帯域
特性を切換るようにしたフェイズロックドループ回路。 　　　゛[Claims for Utility Model Registration] A phase comparator consisting of a multiplier configured as a double-balanced differential amplifier, a loop filter that receives the comparison output from the phase comparator as input, and is controlled by the output of the loop filter. 2. A phase rod loop circuit having a voltage controlled oscillator and a differential switch circuit using the middle current of the double balanced differential amplifier as a current source; A phase-locked loop circuit in which differential outputs are connected to impedance elements that determine a time constant of the loop filter, and the differential switch circuit is controlled by a control signal to switch the operating band characteristics of the circuit.゛
JP6396682U 1982-04-30 1982-04-30 phase lock droop circuit Granted JPS58169735U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6396682U JPS58169735U (en) 1982-04-30 1982-04-30 phase lock droop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6396682U JPS58169735U (en) 1982-04-30 1982-04-30 phase lock droop circuit

Publications (2)

Publication Number Publication Date
JPS58169735U true JPS58169735U (en) 1983-11-12
JPH0339948Y2 JPH0339948Y2 (en) 1991-08-22

Family

ID=30074041

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6396682U Granted JPS58169735U (en) 1982-04-30 1982-04-30 phase lock droop circuit

Country Status (1)

Country Link
JP (1) JPS58169735U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5164857A (en) * 1974-12-03 1976-06-04 Fujitsu Ltd

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5164857A (en) * 1974-12-03 1976-06-04 Fujitsu Ltd

Also Published As

Publication number Publication date
JPH0339948Y2 (en) 1991-08-22

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