JPS6085413U

JPS6085413U - PLL synchronous detection circuit

Info

Publication number: JPS6085413U
Application number: JP17607783U
Authority: JP
Inventors: 智賢中川原
Original assignee: 株式会社東芝
Priority date: 1983-11-16
Filing date: 1983-11-16
Publication date: 1985-06-12

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は、従来の疑似同期検波方式の概略構成図：第２
図は従来のＰＬＬ同期検波回路の概略構成図、第３図は
本考案の一実施例に係るＰＬＬ同期検波回路の構成図、
第４図、第５図は本考案の他の実施例に係るＰＬＬ同期
検波回路の構成図である。１・・・増幅器、２・・・映像検波回路、３・・・ＡＦ
Ｔ回路、４・・・リミッタ、５・・・位相検波回路、６
・・・低域通過フィルタ、７・・・電圧制御発振器、８
・・・９０°位相器、９・・・ロック検出回路、１０・
・・信号源、１１・・・切替回路。Figure 1 is a schematic configuration diagram of the conventional pseudo-synchronous detection method.
The figure is a schematic configuration diagram of a conventional PLL synchronous detection circuit, and FIG. 3 is a configuration diagram of a PLL synchronous detection circuit according to an embodiment of the present invention.
4 and 5 are configuration diagrams of a PLL synchronous detection circuit according to another embodiment of the present invention. 1...Amplifier, 2...Video detection circuit, 3...AF
T circuit, 4... Limiter, 5... Phase detection circuit, 6
...Low pass filter, 7...Voltage controlled oscillator, 8
...90° phase shifter, 9...lock detection circuit, 10.
...Signal source, 11...Switching circuit.

Claims

[Scope of utility model registration request]

a video detection circuit that receives a video intermediate frequency signal and a video detection signal as input and demodulates the video intermediate frequency signal; a phase detection circuit that receives the video intermediate frequency signal and the phase detection signal as input and outputs a phase error signal; a low-pass filter to which a phase error signal is supplied; a voltage-controlled oscillator to which the output of the low-pass filter is supplied and outputs the video detection signal; A 90° phase shifter that shifts the phase by 90° and outputs it as the phase detection signal, and an AFT that receives either the video detection signal or the phase detection signal as input, performs FM detection on it, and outputs it as an AFT signal for automatic frequency adjustment. A PLL synchronous detection circuit comprising a circuit.