JPH01114231A - Digital interface circuit - Google Patents

Abstract

PURPOSE:To reduce jitter, and to improve a high fidelity characteristic by providing a second PLL circuit to perform the correction processing of the jitter of a signal demodulated by a first PLL circuit, and obtaining a synchronizing signal by frequency-dividing the oscillation output of a high fidelity oscillator. CONSTITUTION:The first phase-locked loop circuit(PLL circuit) A is constituted of a phase comparator 4 and a voltage controlled oscillator 5, and outputs the synchronizing signal of a wide band including the sampling frequencies of more than two kinds, for the digital interface signals of more than two kinds to be received by a receiving part 1. Further, this circuit is provided with a control circuit 6 to receive the output of the receiving part 1, the phase comparator 7, a frequency divider 8 and the high stability oscillator 9, and those constitute the second PLL circuit B. Here, when sampling frequency information is obtained, the output signal of the high stability oscillator 9 is divided by the frequency divider 8 according to the instruction of the control circuit 6, and the synchronizing signal of the frequency very close to the frequency of the digital interface signal is outputted. Thus, the data with less jitter is obtained.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention is used to separate and demodulate a desired signal from a digital interface signal processed inside a DAT (digital audio tape recorder) or the like. Related to digital interface circuits.

(Prior art) For example, digital audio tape recorder (DA)
In the reproducing circuit of T), a digital interface circuit is provided in order to process the output signal (digital signal) of the magnetic head with a predetermined digital circuit.

The output signal of the magnetic head includes audio data, channel status signals, user's bits, and the like. The digital ink face circuit separates and demodulates audio data and other data from such signals, and the audio data is then converted to analog and supplied to the main amplifier, etc., and the other data is used for control purposes. . In order to reliably separate and demodulate control signals, etc. from input signals, digital interface circuits have conventionally used a phase-locked loop circuit (P).
LL circuit) was provided.

FIG. 2 shows a block diagram of such a conventional digital interface circuit.

In the figure, a receiving section 1 is a circuit that receives a digital interface signal from a terminal 2. A signal processing circuit 3 is connected to this, and the signal processing circuit 3 performs separation and demodulation of the digital interface signal.

Here, this circuit is provided with a phase comparator 4 that takes in the output signal of the receiver 1 and a voltage controlled oscillator (VCO) 5. This phase comparator 4 and voltage controlled oscillator 5 are:
It constitutes a known PLL circuit. That is, in order to synchronize with the input signal input to the receiver 1, the voltage controlled oscillator 5
The output signal of
The phase difference is detected and the synchronization signal output from the voltage controlled oscillator 5 is corrected so that the phase difference becomes O. When synchronized with the input signal,
The so-called PLL is in a locked state, and the synchronization signal output from the voltage controlled oscillator 5 at this time is transmitted to the signal processing circuit 3.
It is used as a system clock for control.

(Problems to be Solved by the Invention) By the way, in a digital audio tape recorder, the signal input to this digital interface circuit is, for example, 32KHz, 44.1KHz, or 48KH.
There are several frequency ranges such as z. Therefore, the synchronization signal output from the voltage controlled oscillator 5 is also required to have wideband characteristics including at least these three types of sampling frequencies.

However, generally speaking, when the oscillation frequency range of an oscillator is widened, its stability deteriorates. Therefore, if the synchronization signal is used as the system clock, the signal processing circuit 3
When processing audio data in a digital camera, so-called jitter increases and its high-fidelity characteristics deteriorate. Therefore, even though the synchronization signal used as the system clock of the signal processing circuit 3 is required to have high stability and low jitter characteristics, considering the cost,
There was a problem in that it was not easy to realize this.

(Means for Solving the Problems) The present invention has been made with attention to the above points, and includes two types of devices for accepting a digital interface signal and separating and demodulating a predetermined signal included in this digital interface signal. a first PL"L circuit i that generates a wideband synchronization signal including two or more types of sampling frequencies for demodulating the above digital interface signal;
a second PL that generates synchronization signals corresponding to the two or more types of sampling frequencies within a predetermined required accuracy range and performs jitter correction processing on the signal demodulated by the first PLL circuit;
The second P'LL circuit includes a high stability oscillator that oscillates within a predetermined required accuracy range, and the first P'LL circuit.
A digital interface circuit comprising: a frequency divider that divides the oscillation output of the high stability oscillator to obtain the synchronization signal based on frequency information included in the digital interface signal demodulated in the LL circuit. The purpose is to provide the following. (Embodiment of the Invention) FIG. 1 is a block diagram showing an embodiment of a digital interface circuit of the present invention.

In the figure, a receiver 1 receives a digital interface signal input from a terminal 2, and sends it to a signal processing circuit 3.
The processing is performed by a block similar to that shown in FIG. 2.

Here, a phase comparator 4 receives the output signal of the receiver 1.
A first PLL circuit A is constituted by a broadband oscillator such as a voltage controlled oscillator 5 connected thereto. This first PLL circuit A has exactly the same configuration as the PLL circuit shown in FIG. Therefore, the voltage controlled oscillator 5 is configured to output a broadband synchronization signal including two or more sampling frequencies in response to two or more types of digital interface signals received by the receiving section l.

Furthermore, this circuit is provided with a control circuit 6 for receiving the output of the receiving section 1, a phase comparator 7, a frequency divider 8, and a high stability oscillator 9, which constitute a second PLL circuit circuit.

Here, this high stability oscillator 9 is generated from, for example, a crystal oscillator, which generates synchronization signals corresponding to two or more sampling frequencies to be used for the signal received by the receiver 1 within a predetermined required accuracy range. It consists of an oscillation circuit.

Further, the frequency divider 8 divides the frequency of the output signal of the high stability oscillator 9 and sends a predetermined synchronization signal to the phase comparator 7 and the signal processing circuit 3.
This is a circuit that supplies Further, the frequency divider 8 is of a variable type that switches the frequency division ratio according to a control signal output from the control circuit 6.

The phase comparator 7 compares the digital interface signal received by the receiver 1 with the synchronization signal output from the frequency divider 8, detects the phase difference, and corrects the output signal of the high stability oscillator 9. This is a circuit installed in

In the present invention, in this second PL, L circuit B, the frequency divider 8 divides the output signal of the high stability oscillator 9 according to the selection by the control circuit 6 to generate a predetermined high precision synchronization signal. create.

Next, detailed operation of the digital interface circuit shown in FIG. 1 will be explained.

First, when a digital interface signal is input to the receiver 1 from the terminal 2, the first PLL circuit is activated, and when this locks, the digital interface signal can be demodulated.

The control circuit 6 decodes the channel status signal contained in the digital interface signal and reads therein frequency information indicating the sampling frequency.

As explained in FIG. 2, the broadband voltage controlled oscillator 5 to the first PLL circuit has some degree of stability due to its band characteristics, but it is necessary to demodulate this channel status signal from the digital interface signal. There is no problem with the decoding function. Therefore, the control circuit 6 can easily perform its operations.

When the sampling frequency information is obtained here, the control circuit 6 instructs the frequency divider 8 to a predetermined frequency division ratio. Thereby, the output signal of the high stability oscillator 9 is frequency-divided by the frequency division ratio. In this way, a synchronizing signal having a frequency very close to the frequency of the digital interface signal is output from the frequency divider 8, and the operation of the phase comparator 7 locks the second PLL circuit circuit. When the PLL is locked, the synchronization signal output from the frequency divider 8 is used in the signal processing circuit 3 as a synchronization signal with a required frequency of sufficiently high precision.

The signal processing circuit 3 receives this system clock and sequentially reads the digital interface signals temporarily stored in the buffer 10. As a result, the digital interface signal becomes data with less jitter, and distortion of audio data can be prevented.

In addition, in the above digital interface circuit,
First, it is only necessary to satisfy the so-called broadband characteristics of the first PLL circuit. In addition, the second PLL circuit only needs to satisfy high stability, and since it oscillates based on frequency information that specifies the frequency of the digital interface signal, it does not necessarily require characteristics that allow the oscillation frequency to be continuously varied over a wide band. It's not something you can do.

Therefore, the broadband voltage controlled oscillator 4 has a conventional PL.
Using the same oscillator as that used in the L circuit,
A variable crystal oscillator or the like with highly accurate oscillation output characteristics is suitable for the high stability oscillator.

In addition, with the above configuration, when the first PLL circuit is connected, the control circuit 6 reads the channel status information to determine, for example, whether the input signal is a signal that is permitted to be recorded. It is also possible to perform judgments, etc.

(Effects of the Invention) The digital interface circuit of the present invention described above supplies a synchronization signal with extremely low jitter to the signal processing circuit, so that high-fidelity characteristics can be maintained at high quality when audio data is converted to analog. be able to. Furthermore, since its configuration is relatively simple, it can also satisfy so-called economical efficiency.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a digital interface circuit of the present invention, and FIG. 2 is a block diagram showing an embodiment of a conventional digital interface circuit. DESCRIPTION OF SYMBOLS 1... Receiving section, 2... Input terminal, 3... Signal processing circuit, 5... Wideband oscillator, 8... Frequency divider, 9...
・High stability oscillator, A...first PL'L circuit, B.
...Second PLL circuit.

Claims (1)

[Claims] A device that accepts a digital interface signal and separates and demodulates a predetermined signal included in the digital interface signal, including two or more types of sampling frequencies for demodulating two or more types of digital interface signals. a first phase-locked loop circuit that generates a broadband synchronization signal; and a first phase-locked loop circuit that generates synchronization signals corresponding to the two or more sampling frequencies within a predetermined required accuracy range;
and a second phase-locked loop circuit that corrects jitter of the signal demodulated by the locked-loop circuit, and the second phase-locked loop circuit oscillates within a predetermined required accuracy range. The oscillation output of the high stability oscillator is divided based on frequency information included in the digital interface signal demodulated by the high stability oscillator and the first phase-locked loop circuit to obtain the synchronization signal. A digital interface circuit comprising a frequency divider.