JPS6241474Y2 - - Google Patents

Description

[Detailed explanation of the invention] This invention uses FM-MPX using a phase-locked loop.
The present invention relates to an integrated circuit for a demodulator, and particularly to an improvement of a frequency division stage section interposed therein.

Recently, with the progress of integrated circuit (IC) technology, phase-locked loops (PLLs) have come to be used in various circuit fields. In the field of audio equipment, conventional devices were configured as shown in Figure 1.
A typical example is an FM-MPX (multiplex) demodulator. In other words, the part surrounded by the dotted line in the figure is the IC.
The FM input (composite) signal applied to the input terminal _P1 is connected to the amplifier 1 and the terminal P1.
Phase correction capacitor C ₂ externally connected to P ₂ and P ₃
The signal is supplied to the first and second phase comparators 2 and 9 via. Here, the phase-locked loop includes a DC amplifier 3 and a voltage-controlled oscillator (VCO) that oscillates a free-running frequency signal of 76 KHz for the first phase comparator 2.
first and second frequency dividers 5 for frequency division by 4 and 2;
6 are connected in a loop, and the entire loop consists of 19K in the FM input (composite) signal.
Although it is synchronized with the Hz pilot signal, the 38KHz switching signal for demodulation, which will be described later, is sent to the first frequency divider 5.
I'm getting it from Note that capacitors C ₃ , externally connected from the first phase comparator 2 via terminals P ₄ , P ₅ ,
C ₄ and resistor R ₁ constitute a low-pass filter of the phase-locked loop. Further, the capacitor C ₅ and the resistors R ₂ and R ₃ which are externally connected to the terminal P ₆ are an integrating circuit that is combined with the Schmitt circuit included in the voltage controlled oscillator 4.

On the other hand, the lighting circuit has the following for the phase comparator 9:
A third frequency divider 7 that divides the frequency of 38KHz from the first frequency divider 5 by two, and a trigger circuit 10 including a DC amplifier and a Schmitt circuit are connected in a loop. For monitoring stereo signals by directly synchronizing to the 19KHz pilot signal in the input (composite) signal. In other words, depending on the presence or absence of the 19KHz pilot signal, the external stereo indicator PL is made to blink via terminal _P7 , and the stereo switch circuit 11 is controlled to transmit or not transmit the 38KHz switching signal to the decoder circuit 8 (monaural). By switching the FM input (composite) signal, demodulated outputs separated into left and right channels can be obtained from terminals _P8 and _P9 . Note that the terminal from the second phase comparator 9
A capacitor C ₆ externally connected via P ₁₀ and P ₁₁ serves as a low-pass filter for the lighting circuit.

In addition, a terminal derived from the second frequency divider 6
P ₁₂ is provided as a test point.

By the way, in the above, it is necessary that the 38 KHz switching signal (reproduction subcarrier) for demodulation and the 19 KHz pilot signal are in phase with each other.

However, the conventional FM-MPX as described above
In the demodulator, all of the first to third frequency dividers 5, 6, and 7 included in the IC part are saturated flip-flop circuits each composed of transistors _Q1 to _Q4 as shown in FIG. As a result, a phase shift occurs between the above-mentioned pilot signal and the reproduced subcarrier due to the time delay caused by the frequency dividing stage, resulting in a shift in the relationship between the set value of the free-running frequency of the voltage controlled oscillator 4 and the separation. will occur.

For this reason, conventionally, the output section of the amplifier 1 has several
By attaching a 100PF capacitor _C1 externally or by incorporating the required capacitor into the preamplifier 1, it is possible to It was necessary to perform phase alignment.

This idea was made in view of the above points, and the main part of the internal frequency division stage is composed of an unsaturated (high-speed) flip-flop circuit using, for example, a master-slave type low-level ECL frequency divider. Thus, the present invention aims to provide an integrated circuit for an FM-MPX demodulator using an extremely good phase-locked loop that can eliminate the need for complicated phase alignment using capacitors or the like.

An embodiment of this invention will be described in detail below with reference to the drawings.

That is, in Fig. 3, 5' is the second
The first frequency divider is a saturation type flip-flop circuit composed of transistors Q ₁ ′ to Q ₄ ′ and Q ₃ ′, Q ₆ ′, similar to the first frequency divider 5 in the figure. A 38KHz signal is output by dividing the frequency of the 76KHz signal from the voltage controlled oscillator 4 shown in the figure by two. The 38KHz signal from the first frequency divider 5' is connected to a so-called low-level ECL, which is configured like a double-balanced amplifier with transistors Q ₁₁ to _{Q 17} and Q ₂₁ to _{Q 27} , respectively.
The signal is supplied to second and third frequency dividers 6' and 7' which are unsaturated master-slave flip-flop circuits based on Emitter Coupled Logic (Emitter Coupled Logic). Here, since the master-slave type flip-flop circuit operates with a phase difference of exactly 90 degrees, the second and third frequency dividers 6' and 7' each output a 19KHz signal obtained by dividing the 38KHz signal by 2. One is 0 phase (in-phase) (0°) and the other is 90° phase (90°)
It will be output with a difference.

Thus, the first to third frequency dividers 5'. 6' and 7' are shown in Fig. 1 above.
If you replace it with frequency dividers 5, 6, and 7, the IC
The main frequency dividing stage among the frequency dividing stages interposed in the converter section is composed of unsaturated high-speed flip-flop circuits, which poses a problem when all the stages are composed of only saturated flip-flop circuits as in the past. As a result, it is possible to realize an FM-MPX demodulator with excellent separation characteristics without the need for complicated phase matching such as adding a capacitor.

That is, the 76KHz output signal from the voltage controlled oscillator 4 in FIG.
The phase is fixed by comparing the phase with the 19KHz pilot signal in the FM input signal, and at least the second frequency divider 6' and the third frequency divider 6' for deriving the switching signal are used. Since the frequency divider 7' is of an unsaturated type and is designed to have no time delay, the switching signal of the decoder circuit 8 is equivalently changed based on the time delay as in the conventional case.
The phase does not lead to the 19KHz pilot signal, and in other words, the phase shift between the pilot signal and the switching signal can be eliminated, and separation of the demodulated output can be maintained well.

As mentioned above, even if the unsaturated second and third frequency dividers 6' and 7' are made of master-slave flip-flop circuits using low-level ECL, the number of elements used will hardly increase. Therefore, add a capacitor as before.
This method is more reasonable and can provide higher performance than the method that provides a phase delay to the 19KHz pilot signal in the FM input (composite) signal.

Therefore, as described in detail above, according to this invention, the main part of the internal frequency division stage is composed of an unsaturated (high-speed) flip-flop circuit using a master-slave type low-level ECL frequency divider. It is possible to provide an integrated circuit for an FM-MPX demodulator that uses an extremely good phase-locked loop that can improve separation characteristics without the need for complicated phase alignment.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing the FM-MPX demodulator.
Figure 2 is a circuit connection diagram showing the conventional frequency dividing stage used in the frequency dividing stage of Figure 1, and Figure 3 is the FM according to this invention.
- FIG. 3 is a circuit connection diagram showing a frequency division stage section used in an embodiment of the integrated circuit for an MPX demodulator; 5', 6', 7'... Frequency divider, 8... Decoder circuit, 1... Preamplifier, 2, 9... Phase comparator,
3...DC amplifier, 4...Voltage controlled oscillator, 10
...Trigger circuit, 11...Stereo switch circuit.

Claims (1)

[Scope of utility model registration request] This consists of a preamplifier into which the demodulated FM signal including the 19KHz pilot signal is input, and a phase-locked loop that is phase-locked to the 19KHz pilot signal in the demodulated FM signal. a voltage-controlled oscillator that oscillates a free-running frequency signal of 76KHz, a first frequency divider that divides the 76KHz signal from this voltage-controlled oscillator by two and outputs a 38KHz signal, and a The frequency of the 38KHz signal is divided by 2 to obtain the 19KHz of the demodulated FM signal.
It has a master section and a slave section that output first and second 19KHz signals that are in phase with the pilot signal and have a 90° phase difference. The outputs from the preamplifier and the second and third frequency dividers are respectively supplied via external capacitors, and the 19KHz pilot signal in the demodulated FM signal and the second and third the first and second from the divider of
first and second phase comparators that individually compare the phases of the 19KHz signal and output the DC component via an external low-pass filter, and amplify the DC output from the first phase comparator. a DC amplifier that supplies a voltage control signal to the voltage controlled oscillator; a trigger circuit that detects the presence or absence of an output signal from the second phase comparator; 38KHz from frequency generator
A stereo switch circuit that enables signal derivation,
38KHz derived from this stereo switch circuit
The integrated circuit includes a decoder circuit that can switch the demodulated FM signal according to a signal and derive demodulated outputs separated into left and right channels, and a phase compensation capacitor is provided at the output section of the preamplifier. An integrated circuit for an FM-MPX demodulator, characterized in that it does not require any additional components.