JPS59161715U

JPS59161715U - Integrated circuit for FM-MPX demodulator

Info

Publication number: JPS59161715U
Application number: JP2955284U
Authority: JP
Inventors: 日下部　博己
Original assignee: 株式会社東芝
Priority date: 1984-03-01
Filing date: 1984-03-01
Publication date: 1984-10-30
Also published as: JPS6241474Y2

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図はＦＭ−ＭＰＸ復調器を示す回路構成図、第２図
は第１図の分周段に用いる従来の分周段部を示す回路結
線図、第３図はこの考案に係るＦＭ−ＭＰＸ復調器用集
積回路の一実施例に用いる分周段部を示す回路結線図で
ある。　　　　　　　　　−６′、６′、７′・・・分
周器、８・・・デコーダ回路、１・・・前置増幅器、２
．９・・・位相比較器、３・・・直流増幅器、４・・・
電圧制御発振器、１０・・・トリガ回路、１１・・・ス
テレオスイッチ回路。Fig. 1 is a circuit configuration diagram showing an FM-MPX demodulator, Fig. 2 is a circuit connection diagram showing a conventional frequency division stage section used in the frequency division stage of Fig. 1, and Fig. 3 is an FM-MPX demodulator according to this invention. FIG. 2 is a circuit wiring diagram showing a frequency division stage section used in an embodiment of an integrated circuit for an MPX demodulator. -6', 6', 7'... Frequency divider, 8... Decoder circuit, 1... Preamplifier, 2
．． 9... Phase comparator, 3... DC amplifier, 4...
Voltage controlled oscillator, 10... trigger circuit, 11... stereo switch circuit.

Claims

[Scope of utility model registration request]

It uses a phase-locked loop that is phase-locked to the l9KHz pilot signal in the FM input signal to be demodulated, and the 75
a voltage controlled oscillator that oscillates a KHz free-running frequency signal;
A first frequency divider that divides the 75KHz signal from this voltage controlled oscillator by two and outputs a 33KHz signal, and divides the 33KHz signal from this first frequency divider by two and outputs the 33KHz signal to be demodulated. A first and a second one with in-phase and 90° phase difference with the 19KHz pilot signal in the FM input signal.
second and third frequency dividers that output a 9KHz signal; a 19KHz pilot signal in the demodulated FM input signal; and first and second l9KHz signals from the second and third frequency dividers; a trigger circuit that detects the presence or absence of an output signal from the second phase comparator; and a trigger circuit that detects the presence or absence of an output signal from the second phase comparator; 33KHz from 1 frequency divider
The stereo switch circuit includes a stereo switch circuit capable of deriving a signal, and a decoder circuit capable of deriving demodulated outputs separated into left and right channels by switching the FM input signal to be demodulated using a 38 KHz signal derived from the stereo switch circuit. The integrated circuit for an FM-MPX demodulator is configured such that the voltage controlled oscillator can be controlled by an output signal from the first phase comparator.
An integrated circuit for an FM-MPX demodulator, characterized in that the third frequency divider is constituted by an unsaturated flip-flop circuit using a master-slave type low-level ECL.