JPH0438617Y2 - - Google Patents

Description

[Detailed explanation of the invention] (a) Industrial application field This invention allows 19K
The present invention relates to a stereo display circuit that performs stereo display in response to the presence of a Hz stereo pilot signal, and particularly to a stereo display circuit that prevents display elements from erroneously lighting up when forced monaural reception is canceled. (b) Prior Art Japanese Patent Publication No. 55-41582 describes a stereo demodulation circuit as shown in FIG. In Fig. 2, a 19KHz signal obtained by dividing the output signal of a 76KHz VCO (voltage controlled oscillator) 1 by first and second frequency divider circuits 2 and 3 is converted into a 19KHz signal in a stereo composite signal by a phase comparator circuit 4. The phase is compared with the stereo pilot signal. An error signal corresponding to the phase difference obtained from the phase comparator circuit 4 passes through a low-pass filter 5, is amplified by a DC amplifier circuit 6, and is applied to the VCO 1. Therefore, the above
The VCO oscillates in synchronization with the 19KHz stereo pilot signal. Further, the 19 KHz stereo pilot signal in the stereo composite signal is detected by a detection circuit 7 and applied to a trigger circuit 9 via a low pass filter 8. Therefore, when receiving a stereo broadcast in which the 19 KHz stereo pilot signal is present, an output signal from the detection circuit 7 is generated, the trigger circuit 9 is operated, and the stereo display element 10 is turned on. Furthermore, when receiving a stereo broadcast, the switch circuit 11 is controlled to be conductive by the output signal of the trigger circuit 9, so the 38KHz output signal of the first frequency divider circuit 2 is applied as a switching signal to the stereo demodulator 12, and the stereo Demodulation is performed. On the other hand, when receiving monaural broadcasts, there are
Since the 19KHz stereo pilot signal is not included, the detection circuit 7 does not generate an output signal, and the trigger circuit 9 also does not generate an output signal. Therefore, the stereo display element 10 does not light up, and the switch circuit 11
is in a cut-off state. By the way, when the stereo demodulation operation is stopped, such as when receiving a weak electric field stereo broadcast, a forced monaural signal is applied to the control terminal 13. When the forced monaural signal is applied, a control signal is generated from the control circuit 14, the oscillation of the VCO 1 is stopped, the operation of the trigger circuit 9 is stopped, the stereo display element 10 is turned off, and the switch circuit 11 is turned off.
A cutoff is performed. Therefore, by using a stereo demodulation circuit as shown in FIG. 2, normal reception of stereo broadcasts and monaural broadcasts and forced monaural reception can be achieved. As the detection circuit 7 for detecting the stereo pilot signal shown in FIG. 2, for example, a synchronization detection circuit as shown in FIG. 3 is used. In the case of Figure 3, input terminal 15
The 19KHz stereo pilot signal applied to
At the connection point A between the first and second resistors 16 and 17 and the connection point B between the third and fourth resistors 18 and 19,
is multiplied by the signal from At the bases of the first and second chopper transistors 20 and 21,
First and second 19KHz switching signals having phases different by 180 degrees from each other are applied from a frequency divider circuit 22 constituted by a flip-flop circuit, so that they are alternately conductive. At this time, since the oscillation output signal of the VCO 23 is synchronized with the 19KHz stereo pilot signal in the stereo composite signal, the frequency-divided output signal of the frequency divider circuit 22 is also synchronized with the stereo pilot signal. Synchronous detection is achieved. The synchronous detection output signal charges the capacitor 24 to the polarity shown. Therefore, when the 19 KHz stereo pilot signal is present, the first transistor 26 constituting the differential amplifier circuit 25 is turned on, the second transistor 28 is turned off, and an output signal is generated at the output terminal 28. Therefore, by applying the output signal obtained at the output terminal 28 to the stereo display element 10, stereo display can be achieved. Furthermore, if the oscillation of the VCO 23 is stopped using a forced monaural signal, the output signal of the frequency dividing circuit 22 is stopped in a predetermined state, and one of the first and second chopper transistors 20 and 21 is turned on, and the other is turned on. turns off and the synchronous detection operation stops. (c) Problems to be solved by the invention In that case, if the first chopper transistor 20 is turned on and the second chopper transistor 21 is turned off, then the first transistor 27 of the differential amplifier circuit 25 is turned on. It never turns on, and the stereo display element never lights up. However, when the first chopper transistor 20 is turned off and the second chopper transistor 21 is turned on, charges of the illustrated polarity remain in the capacitor 24, and the first transistor 26 of the differential amplifier circuit 25 is turned on. The stereo display element lights up and malfunctions. In order to prevent this malfunction, a forced monaural signal can also be applied to the trigger circuit 9 as shown in Fig. 2, but even if such a measure is taken, the stereo display element will not function properly when the forced monaural mode is released. The problem of erroneous lighting still remains. In other words, if monaural reception or weak electric field stereo reception is being performed when forced monaural is canceled, the stereo display element should normally be turned off, but the capacitor 24
If a charge remains in the differential amplifier circuit,
Since the 25 first transistors 26 continue to be on,
The stereo display element lit up when forced monaural was canceled, which was a problem. (d) Means for solving the problem The present invention was created in view of the above points, and uses a forced monaural signal to stop the oscillation of the VCO and at the same time stop the operation of the frequency dividing circuit. It is characterized by points. (E) Effect According to the present invention, since the operation of the frequency dividing circuit is stopped together with the VCO, the first and second chopper transistors of the detection circuit for detecting the 19KHz stereo pilot signal can be turned on or off simultaneously. The voltage across the capacitor can be set to the same value. Therefore, when the forced monaural operation state is entered, the accumulated charge in the capacitor can be reduced to zero, and erroneous lighting of the stereo display element when forced monaural operation is canceled can be prevented. (F) Embodiment Figure 1 is a circuit diagram showing an embodiment of the present invention.
29 consists of third and fourth transistors 30 and 31, a current source 32, and resistors 33 and 34, and VCO
23 and a power supply circuit 3 that serves as an operating power source for the FF (flip-flop) circuit 22 that operates as a frequency dividing circuit.
5 is a control transistor that is turned on in response to a forced monaural signal applied to a control terminal 36 and bypasses the output power of the current source 32; 37 is a differentially connected fifth and sixth transistor 38 and 39; , a buffer amplifier circuit that inverts mutual output signals obtained from the FF circuit 22 and applies them to the bases of the first and second chopper transistors 20 and 21, and 40 is a drive transistor that drives the display element 10. be. In FIG. 1, circuit elements that are the same as those in FIGS. 2 and 3 are denoted by the same reference numerals, and explanations thereof will be omitted. In normal operating conditions, the control transistor 3
6 is off, the power supply circuit 29 operates according to the output current of the current source 32, and a current voltage is applied to the VCO 23 and the FF circuit 22. Therefore, VCO2
3 and the FF circuit 22 operate normally, and the FF circuit 22
Output signals (19 KHz switching signals) having mutually opposite phases are applied to the buffer amplifier circuit 37 . FF circuit 22 inverted by the buffer amplifier circuit 37
The output signals of
If the stereo pilot signal is present, the stereo display element 10 lights up and stereo display is performed. To perform forced monaural operation, when a forced monaural signal is applied to the control terminal 35, the control transistor 3
6 is turned on, bypassing the output current of current source 32. Therefore, the current circuit 29 becomes inoperative,
At the same time as the oscillation of VCO23 stops, the FF circuit 2
2 operation stops. When the FF circuit 22 stops operating, both outputs become "L", so the fifth and sixth transistors 38 and 39 constituting the buffer amplifier circuit 37 are also turned off, and the fifth and sixth transistors 38 and 39 collector voltages both become "H". Therefore, since the "H" collector voltage is applied to the bases of the first and second chopper transistors 20 and 21, respectively, the first and second chopper transistors 20 and 21 are both turned on. , capacitor 24
The voltages across are equal. Therefore, no charge is accumulated in the capacitor 24, and the collector currents of the first and second transistors 26 and 27 have the same value, so the output transistor 41 and the drive transistor 40 are not turned on, and the stereo display element 10 is achieved. When forced monaural is canceled, power supply circuit 29
returns to normal operation, and the VCO 23 and FF circuit 22 also operate normally, so the synchronous detection circuit is in a normal operating state. At that time, since there is no residual charge in the capacitor 24, erroneous lighting of the stereo display element 10 due to the residual charge does not occur. In a stereo reception state in which a 19KHz stereo pilot signal is applied to the input terminal 15, the stereo display element 10 is turned on in accordance with the detection output, and in a monaural reception state, the stereo display element 10 is turned off. In the embodiment shown in FIG. 1, the buffer amplifier circuit 37 for signal inversion is used to invert the output signal of the FF circuit 22, so that both ends of the capacitor 24 are equally at the "H" level during forced monaural mode. ing. Therefore, the base biases of the first and second transistors 26 and 27 do not change when forced monaural is canceled, and the time required for the synchronous detection circuit to reach a normal operating state is significantly shortened. However, without using the buffer amplification circuit 37 ,
The output signal of the FF circuit 22 may be directly applied to the bases of the first and second chopper transistors 20 and 21. In that case, in forced monaural mode, both the outputs of the FF circuit 22 become "L" and the first
Since the second chopper transistors 20 and 21 are both turned off, both ends of the capacitor 24 are equally at the "L" level. In this case, it takes time for the voltage across the capacitor 24 to reach a predetermined value when the forced monaural mode is canceled, but at least the accumulated charge in the capacitor 24 can be reduced to zero, so that erroneous lighting of the stereo display element 10 can be prevented. (G) Effects of the invention As described above, according to the invention, it is possible to prevent the stereo display element from erroneously lighting up when the forced monaural mode is activated or when the forced monaural mode is canceled. Furthermore, since the present invention stops the operation of the FF circuit as well as the VCO, the current consumption during forced monaural mode can be significantly reduced. Furthermore, as in the embodiment, if the output signal of the FF circuit is inverted using a buffer amplifier circuit,
The time required for the detection circuit of the 19KHz stereo pilot signal to reach normal operation from the time of forced monaural cancellation can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional stereo demodulation circuit, and FIG. 3 is a circuit diagram showing an example of the display circuit. 22...FF circuit, 23...VCO, 29 ...power supply circuit, 36...control transistor, 37 ...buffer amplifier circuit.

Claims (1)

[Scope of utility model registration request] Oscillates in synchronization with the stereo pilot signal
A VCO, a frequency divider circuit that divides the output signal of the VCO, a synchronous detection circuit that synchronously detects a stereo pilot signal in a stereo composite signal according to the output signal of the frequency divider circuit, and In a stereo display circuit comprising a drive circuit that drives a stereo display element according to an output signal, the VCO is
A stereo display circuit which stops oscillation of the frequency divider circuit and stops the operation of the frequency dividing circuit to prevent the stereo display element from being erroneously lit.