JPH04602Y2 - - Google Patents

Description

[Detailed description of the invention] (a) Industrial application field This invention relates to an improvement of the stereo multiplex circuit of an FM stereo receiver, and in particular,
The present invention relates to a stereo multiplex circuit that accelerates the start of stereo operation when the oscillation stop of a VCO (voltage controlled oscillator) is released. (b) Prior art The 38KHz switching signal required for demodulating FM stereo signals is a PLL (phase locked loop).
Created by using circuits. Said PLL
As shown in Fig. 1, the circuit includes a phase comparator 1, a low-pass filter 2, a DC amplifier 3, and a VCO 4.
and first and second frequency dividers 5 and 6. The VCO 4 generates an oscillation signal having a frequency of 76KHz, and the oscillation signal is divided into a 38KHz signal by a first frequency divider 5, and a second
The frequency is divided by frequency divider 6 into a 19KHz signal. and,
The 19KHz signal is converted to FM in phase comparator 1.
The phase is compared with the 19KHz stereo pilot signal included in the stereo signal, and a signal corresponding to the phase difference is applied to the VCO 4 via the low-pass filter 2 and DC amplifier 3, so the oscillation frequency of the VCO 4 is the 19KHz stereo pilot signal. It will be synchronized with. The 38KHz output signal of the first frequency divider 5 is applied to the stereo decoder 7 as a switching signal. Therefore, the stereo composite signal containing the stereo sum signal (L+R) and the stereo difference signal (L-R) applied to the input terminal 8 is
The signal is demodulated by the stereo decoder 7, and left and right stereo signals L and R are generated at left and right output terminals 9 and 10, respectively. However, when a stereo multiplex circuit including the PLL circuit shown in Fig. 1 is used in an AM/FM receiver, there is a drawback that a beat occurs due to the oscillation frequency of the VCO 4 during AM reception, which interferes with AM reception. Ta. Therefore, conventionally,
As shown in Japanese Patent Publication No. 55-41582, the oscillation of the VCO 4 is forcibly stopped during AM reception to prevent the above-mentioned interference. By the way, a VCO in which the oscillation frequency is set by a solid-state resonator such as a crystal and positive and negative variable reactance circuits has been proposed by the applicant of the present application and filed as Japanese Patent Application No. 169338/1982. FIG. 2 shows such a VCO and a DC amplifier that applies a control signal to the VCO, where 11 is a VCO equipped with a constant current transistor 12, and 13 is a VCO with a constant current transistor 12.
A solid-state resonator such as a crystal that determines the oscillation frequency of 14
acts as a parallel capacitance of the solid-state resonator 13,
A positive variable capacitance reactance circuit for making the oscillation frequency of VCO11 lower than the free run frequency,
15 is a negative variable capacitor reactance circuit which acts as a parallel capacitor for the solid-state resonator 13 and makes the oscillation frequency of the VCO 11 higher than the free run frequency; 16 is a differentially connected first and second transistor 17 and 18; and the first and second current inversion circuits 1
9 and 20, which is a DC amplifier that generates control signals for the positive and negative variable reactance circuits 14 and 15. When receiving FM stereo broadcasting, the 19KHz signal obtained by dividing the oscillation output signal of VCO 11,
A signal corresponding to the phase difference between the FM stereo composite signal and the 19KHz stereo pilot signal is applied as a differential component to the first and second input terminals 21 and 22 of the DC amplifier 16 via a low-pass filter. It is amplified by a DC amplifier 16.
At that time, if the oscillation frequency of the VCO 11 is higher than a predetermined value, the signal level applied to the second input terminal 22 becomes higher than the signal level applied to the first input terminal 21, and the collector current of the second transistor 18 increases. becomes large, and the control signal applied from the second current inversion circuit 20 to the positive variable reactance circuit 14 becomes large, so that the oscillation frequency of the VCO 11 becomes low. Moreover, when the oscillation frequency of the VCO 11 is lower than a predetermined value, the collector current of the first transistor 17 becomes large, and the control signal applied from the first current inversion circuit 19 to the negative variable reactance circuit 15 becomes large. Therefore, the VCO1
The oscillation frequency of 1 becomes higher. Therefore, by using the circuit shown in Figure 2, the oscillation frequency of VCO 11 can be reduced to 19KHz.
It can be synchronized with the stereo pilot signal. When receiving AM broadcasting, the control terminal 23 is grounded, the constant current transistor 12 is turned off, and the oscillation of the VCO 11 is stopped in order to prevent interference with AM reception. When the oscillation of the VCO 11 stops, the first
The operation of the PLL circuit shown in the figure also stops, but the VCO1
Depending on the timing of the oscillation stop of 1, the DC amplifier 1
An offset voltage is generated between the bases of the first and second transistors 17 and 18 of 6. For example, the first
When the voltage at the input terminal 21 decreases by more than a predetermined value than the voltage at the second input terminal 22, the first transistor 1
7 is off, the second transistor 18 is on,
While the control signal is applied from the second current inversion circuit 20 to the positive variable reactance circuit 14, the operation of the DC amplifier 16 is stopped. In this state, when the control terminal 23 is opened again to receive FM broadcasting, the VCO 11 starts oscillating at a frequency determined by the solid-state oscillator 13 and the equivalent capacity of the positive variable reactance circuit 14. Therefore, when the positive variable reactance circuit 14 works,
Because the parallel resonant impedance is lower, the above
The voltage level of the oscillation signal of the VCO 11 becomes small.
This state is equivalent to a decrease in the loop gain of the PLL circuit, and the response of the PLL circuit becomes slow. As a result, it takes a long time for the receiver to start stereo operation after the VCO 11 is stopped, giving the listener a sense of discomfort. (c) Purpose of the invention This invention was created in view of the above points.
When the VCO is stopped, a forced offset voltage is applied to the DC amplifier, and when the VCO stops, the negative variable reactance circuit is activated first, and the receiver is
This is intended to shorten the time it takes to start stereo operation after the VCO is released. (d) Structure of the invention The stereo multiplex circuit according to the invention includes a VCO whose oscillation frequency is set by a solid-state resonator and positive and negative variable reactance circuits;
The PLL circuit includes a DC amplifier that supplies a control signal to the positive and negative variable reactance circuits, and means for applying a predetermined offset voltage to the DC amplifier when oscillation of the VCO is stopped. (e) Embodiment Figure 3 is a circuit diagram showing an embodiment of the present invention.
24 is a VCO whose oscillation frequency is set by a solid-state resonator 25 and positive and negative variable reactance circuits 26 and 27; 28 is a VCO that divides the 76KHz oscillation signal of the VCO 24 to generate a 38KHz switching signal; 1 frequency divider 29 divides the output signal of the first frequency divider 28 and outputs 19K to Q and terminals with opposite phases to each other.
A second frequency divider 30 that generates an Hz signal divides the output signal of the first frequency divider 28 and outputs a signal from the output signal of the second frequency divider 29 to Q and terminals in opposite phases to each other.
a third frequency divider that generates a 19KHz signal phase-shifted by 90 degrees; 31 is an input terminal to which an FM stereo composite signal is applied; 32 is an input terminal to which an FM stereo composite signal is applied; 19KHz
A synchronous detector 33 that synchronously detects the stereo pilot signal is a first synchronous detector that amplifies the output signal of the synchronous detector 32 and drives a stereo display (not shown).
a DC amplifier; 34 a phase comparator for comparing the phase of the output signal of the second frequency divider 29 and the 19KHz stereo pilot signal; 35 a phase comparator 34;
a low pass filter that passes the output signal of 36 ;
37 is a decoder that demodulates the left and right stereo signals using the 38KHz switching signal obtained from the first frequency divider 28; 38 is a VCO 24 that is turned on when receiving AM; oscillation stop switch, 3
9 is a detection transistor that detects that the switch 38 is turned on; 40 is the detection transistor 3;
9, a grounding transistor that grounds the base of the constant current transistor 41 of the VCO 24;
and 42 are diodes for applying a forced voltage to the base of the first transistor 43 of the second DC amplifier 36 when the oscillation stop switch 38 is turned on. When receiving an FM stereo broadcast, the switch 38 for stopping oscillation is turned off, and the FM stereo composite signal applied to the input terminal 31 is
The 19KHz stereo pilot signal is sent to phase comparator 3.
4, the phase is compared with the 19KHz output signal of the second frequency divider 29. Then, a signal corresponding to the phase difference is passed through the low-pass filter 35 and the DC amplifier 36 .
Since the voltage is applied to the positive and negative variable reactance circuits 26 and 27 that determine the oscillation frequency of the VCO 24, the oscillation frequency of the VCO 24 changes, and the
It is synchronized with the 19KHz stereo pilot signal. Further, the 19KHz stereo pilot signal is synchronously detected by a synchronous detector 32 to generate a signal corresponding to the level of the pilot signal, which is amplified by a first DC amplifier 33 and applied to a stereo display. Display indicates that stereo reception is in progress. Furthermore, the voltage applied to the input terminal 31 is
The stereo sum signal (L+R) and stereo difference signal (L-R) in the FM stereo composite signal are:
Since the signal is applied to the decoder 37 and demodulated using the 38KHz switching signal obtained from the first frequency divider 28, left and right stereo signals L and R are generated at the left and right output terminals 44 and 45, respectively. Next, in order to receive AM broadcasting, when the oscillation stop switch 38 is closed, the voltage of the first power supply 46, which is the power supply for the synchronous detector 32 and the phase comparator 34 , is
The voltage Vs of the second power supply 47, which is greater than Vr, is applied to point A via the switch 38, turning on the detection transistor 39, and also turning on the shorting transistor 40, thereby grounding the base of the constant current transistor 41 of the VCO 24. . Therefore, the VCO 24 immediately stops oscillating, and the first to third frequency dividers 28 to 3
0 also immediately stops operating. Further, the voltage Vs applied to point A turns on the first transistor 48 of the first DC amplifier 33 and turns off the second transistor 49, so that the stereo display turns off.
Further, the voltage Vs applied to the point A is applied to the base of the first transistor 43 of the second DC amplifier 36 via the diode 42. The voltage
When Vs is applied, the second DC amplifier 36 is forced to be driven, the first transistor 43 is turned on, and the second transistor 50 is turned off. Therefore, the collector current of the first transistor 43 is inverted by the first current inverting circuit 51 and supplied to the negative variable reactance circuit 27. If there is no signal path connecting point A and the base of the first transistor 43 of the second DC amplifier 36 , the state of the second DC amplifier 36 will not be determined when the oscillation stop switch 38 is turned on. That is, when the Q output of the third frequency divider 30 is "H", the bases of the first and second transistors 43 and 50 of the second DC amplifier 36 have the same voltage, and the Q output of the third frequency divider 30 becomes "H". When the output is "L" and the Q output of the second frequency divider 29 is "H",
The first transistor 43 of the second DC amplifier 36
becomes higher than the base voltage of the second transistor 50, when the Q output of the third frequency divider 30 is "L" and the output of the second frequency divider 29 is "H", the second DC The base voltage of the second transistor 50 of the amplifier 36 becomes higher than the base voltage of the first transistor 43. Therefore, when the Q output of the third frequency divider 30 is "L" and the output of the second frequency divider 29 is "H", the drawback described in connection with FIG. 2 occurs. However, in the present invention, since a forced voltage is applied to the base of the first transistor 43 of the second DC amplifier 36 using the diode 42, the second DC amplifier 36
The state of is uniquely determined. In order to receive the FM stereo broadcast again, when the oscillation stop switch 38 is turned off, the detection transistor 39 is turned off, and the shorting transistor 40 is also turned off, so that the VCO 24 immediately resumes oscillation.
At that time, due to the existence of the capacitor of the low-pass filter 35, the offset voltage of the second DC amplifier 36 does not disappear, and the first transistor 43 is turned on and the second
Since the transistor 50 remains off,
First, the negative variable reactance circuit 27 operates, and the parallel resonance impedance of the solid-state resonator 25 increases. Therefore, the voltage level of the oscillation signal of the VCO 24 also increases, the PLL circuit responds rapidly, and the VCO 24 immediately synchronizes with the 19KHz stereo pilot signal. Therefore, the decoder 37 also becomes operational immediately, and the stereo operation is started immediately after the oscillation of the VCO 24 is stopped. Note that the voltage Vs of the second power supply 47 is the same as that of the first power supply 46.
It is necessary to set the value to be at least V _BE larger than the voltage Vr of . Furthermore, when applying the offset voltage to the second DC amplifier 36 , instead of using the diode 42, the base is connected to point A and the collector is connected to the power supply (+
V _CC ), the emitter of the second DC amplifier 36
An NPN transistor connected to the base of the transistor 43 may be used, and by doing so, the current flowing from the second power supply 47 becomes small.
As the second power supply 47 and the oscillation stop switch 38, an output port of a microcomputer or the like that generates a control signal when receiving AM can be directly used. (F) Effects of the invention As described above, according to the invention, there is an advantage that the time required for the receiver to start stereo operation after the oscillation stop of the VCO is canceled can be greatly shortened. Incidentally, according to actual measurements, the above-mentioned time was conventionally 3 to 4 seconds, but in the present invention, the stereo operation could be started in about 0.6 to 0.8 seconds.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing a stereo multiplex circuit using a PLL circuit, Fig. 2 is a circuit diagram showing a conventional stereo multiplex circuit, and Fig. 3 is a circuit diagram showing an embodiment of the present invention. It is. Explanation of main drawing numbers, 24...VCO, 25...solid resonator, 26...positive variable reactance circuit,
27...Negative variable reactance circuit, 28,2
9, 30... Frequency divider, 32 ... Synchronous detector, 34
...Phase detector, 36 ...Second DC amplifier, 38
...oscillation stop switch, 42...diode.

Claims (1)

[Scope of utility model registration request] Contains a VCO whose oscillation frequency is set by a solid-state resonator and positive and negative variable reactance circuits
In a stereo multiplex circuit including a PLL circuit, a DC amplifier supplies a control signal to the positive and negative variable reactance circuits;
comprising a stopping means for stopping the oscillation of the VCO, and an offset means for applying an offset voltage to the DC amplifier in response to the stopping operation of the stopping means,
A stereo multiplex circuit characterized in that the offset voltage has a polarity that provides a control signal to the negative variable reactance circuit.