JPS5850655Y2 - PLL multiplex demodulation circuit - Google Patents

Description

[Detailed description of the invention] The present invention relates to the structure of a PLL multiplex demodulation circuit for a stereo receiver, and in particular, the oscillation frequency monitor circuit, a device for stopping the voltage controlled oscillator (VCO killer), and the switching of a 38KHz signal. It is related to the device.

In the PLL multiplex demodulation circuit of a stereo receiver, the oscillation frequency of the voltage controlled oscillator (VCO) is set to 76
Must be fixed to KH2.

The oscillation frequency is adjusted by adjusting the resistance value of an externally connected resistor.

Once adjusted, stable oscillation can be repeated by the operation of the PLL.

During adjustment, the resistance is adjusted by monitoring the 19KH2 signal, which is the frequency-divided output of the VCO.

PLL multiplex demodulation circuits are increasingly integrated into single chips.

As the integration of circuits progresses, terminals for connection with the outside will become necessary, but since there is a limit to the number of terminals, it is desirable to minimize the number of terminals.

In particular, the terminal only for monitoring the 19 KHz signal as described above becomes an unnecessary terminal that will not be used after adjustment.

The overall number of pins must be increased due to the unnecessary terminals, or other pins must be removed.

For this reason, conventionally, when a terminal for monitoring the 19KH2 signal is provided, a terminal for a device (VCO killer) for stopping the oscillation of the VCO is excluded.

In this case, the VCO killer should be an external transistor,
It will have to be made up of resistors.

Conversely, if you exclude the terminal that monitors the 19KH2 signal, v
The frequency must be monitored at the input terminal of the CO, which tends to cause changes in the oscillation frequency, and requires monitoring with a high impedance measurement circuit.

The present invention aims to eliminate the above-mentioned drawbacks and to provide a PLL multiplex demodulation circuit suitable for integration into an integrated circuit with a small number of pins.

The PLL multiplex demodulation circuit according to the present invention has 19
The above purpose is achieved by making the terminal for monitoring the KHz signal and the terminal for cO killer common.

Embodiments of the present invention will be described below with reference to FIG.

VCOll oscillates at 76KHz.

Although not shown, this oscillation section operates at a fixed frequency based on the principle of PLL.

The output of VCOll is frequency-divided by a divider 12 to 38 KHz, and further divided to 19 KHz by a divider 13.

This 19KH2 signal is, for example, 10, +2V from IV.
is set to the level of

This output is connected to a resistor R5 and a resistor R6 to obtain the first reference voltage source.
The voltage is divided between +0.1V and arbitrarily set to a level of +1.45V in this case.

When this signal is applied from the midpoint to the base of transistor Q3, 19KHz from the emitter of transistor Q3,
A signal with a level of +0.75■ is obtained from OV.

This emitter electrode is connected to terminal 14.

Normally, a signal output of 19 KHz and 0 to 0.75 V is obtained at the terminal 14.

By monitoring the signal appearing on this terminal pin 14, the oscillation frequency of the VCOll can be adjusted.

On the other hand, the emitter of the transistor Q3 is connected to the output terminal 14, and a resistor R is connected to obtain the second and third reference voltage sources.
It is connected to a voltage dividing resistor formed from 1tR2 and resistor R3tR4.

The connection point between resistors R1 and R2, which provides the second reference voltage source, is connected to the base of the transistor Ql used for the CO killer, and the connection point between resistors R3 and R4, which provides the third reference voltage source, is forced into stereo. The transistors Q2 are connected to the bases of transistors Q2 for switching from a mono state to a monaural state.

Both the CO killer transistor Ql and the forced monaural circuit transistor Q2 are set not to operate at the normal output of the transistor Q3, which is O to 0.75V in the above example.

That is, even if the resistance values of the resistors R1 to R4 are at the maximum potential (0.75 V in the above case), the transistor Qt.

Make sure that Q2 does not operate.

Next, the operation of the vCO killer and forced monaural circuit, which is performed depending on the level of the DC voltage input from the terminal 14, will be explained.

When a DC voltage exceeding 0.75V is applied to terminal 14, transistor Q3 stops operating.

Further, the voltage is increased to operate the transistors Ql and Q2, thereby operating the CO killer and the forced monaural circuit.

■Since the forced monaural circuit may operate even if the CO killer does not operate, the voltage of the third reference voltage source is set to a value lower than the voltage of the second reference voltage source, and the transistor Q
2 is made to operate at a lower voltage than transistor Q1.

The voltage applied from terminal 14 is divided by resistor R3 and resistor R4 and applied to the base of transistor Q2.

When transistor Q2 turns on at a predetermined voltage, 38K
It operates to turn off the Hz switch 16.

When the 38 KHz switch 16 is turned off, no 38 KHz signal is sent to the demodulated sound from the terminal 15, so that only a monaural signal based on the main carrier component is obtained as the output of the demodulator.

When the voltage applied to the terminal 14 is further increased, the resistance R1
The voltage divided by the resistor R2 and applied to the base of the transistor Q1 also increases, and the transistor Ql is also turned on.

When transistor Q1 operates, the oscillation of the VCO is stopped.

That is, the output of the VCO, which normally oscillates with a 76 KHz trigger waveform, is fixed at a constant voltage level and stops oscillating.

Of course, in this case, the transistor Q of the forced monaural circuit
2 is also on, and operates to turn off the 38KHz switch 16 as well.

Note that the transistor Q3, whose base is connected to the frequency divider that obtains the 19KH2 signal, does not necessarily need to be used to operate as a demodulation circuit, but in order to reduce the influence on other circuits, the transistor Q3 can be used. It is better to apply the emitter follower output to the terminal 14.

Transistors Ql, Q2 and transistor Q3 are never activated at the same time; when Q3 is turned on and produces an output at terminal 14, transistors Q1. Q2 is turned off and does not operate.

Conversely, when transistors Ql, Q2, or only Q2 are turned on, transistor Q3 is turned off and does not operate.

Therefore, the output terminal of the transistor Q3 and the bypass application terminal to the bases of the transistors Ql and Q2 are in such a relationship that when one is necessary, the other is unnecessary.

By utilizing this and appropriately determining the resistors R1 to R6, the terminal 14 can play either role.

According to the present invention, the terminal 14 can control the oscillation frequency of CO by 76
It is first used as a monitor terminal for tuning to KHz, and after the CO oscillation frequency is determined, it can be used as a VCO killer and forced monaural circuit terminal.

This makes it possible to reduce the number of terminal pins of an integrated PLL multiplex demodulation circuit or to obtain an element with additional functions.

Furthermore, there is no adverse effect on operating characteristics, and an extremely reliable PLL multiplex demodulation circuit can be obtained.

[Brief explanation of the drawing]

FIG. 1 shows a circuit diagram of an embodiment of the present invention. 11... Voltage controlled oscillator, 12, 13...
...Frequency divider, 14... terminal, Ql, Q2,
Q3...Transistor, R1-R6...
·resistance.

Claims (1)

[Scope of utility model registration request] a voltage controlled oscillation circuit that oscillates at a predetermined frequency; a circuit system that passes the output from the voltage controlled oscillation circuit through a 10th frequency divider and a second divider to obtain a 19KH2 signal;
a first reference voltage source to which a second signal is supplied; a first transistor bypassed by the first reference voltage source; and second and third transistors connected in parallel to the emitter of the first transistor. a reference voltage source, a second transistor biased by the second reference voltage source to cut off the output of the voltage controlled oscillation circuit, and a second transistor biased by the third reference voltage source to block the output of the first branching circuit; a third transistor for controlling the output and forcing the monaural reception state, and obtaining a 19 KHz signal from the connection point between the emitter of the first transistor and the second and third reference voltage sources; , by applying a DC voltage having a higher potential than the first reference voltage source to the connection point, the first transistor is cut off, and the level of the DC voltage is set to a predetermined value. 2. A PLL multiplex demodulation circuit comprising a circuit that operates both the second transistor and the third transistor to set the monaural receiving state, or operates only the third transistor to set the forced monaural receiving state.