JPH0350451B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to changing the lock range of a PLL circuit, and particularly to a PLL circuit suitable for use in a stereo multiplex circuit of an FM stereo receiver.

(b) Prior art On page 360 of "'85 Sanyo Semiconductor Handbook Monolithic Bipolar Integrated Circuit Edition" published on March 20, 1985, there is a description of an IC (integrated circuit) equipped with a PLL circuit as shown in Figure 2. ) LA3350 is listed. In Figure 2, the voltage applied to input terminal 1 is
The phase of the 19KHz stereo pilot signal is compared with the output signal of the frequency divider circuit 3 in the phase comparator circuit 2. The DC signal corresponding to the phase difference generated at the output end of the phase comparator circuit 2 is amplified by the DC amplifier circuit 4 and then applied to the VCO 5.
The output signal of 5 and the output signal of frequency divider circuit 3 are as follows.
It is synchronized with the 19KHz stereo pilot signal.

Therefore, the 38KHz signal obtained by dividing the output signal of the VCO 5 can be used as a signal for demodulating the left and right stereo signals L and R, and the 19KHz signal can be used as a signal for stereo display. It can be used.

(c) Problems to be Solved by the Invention However, the PLL circuit as shown in Fig. 2 has the risk of generating large phase jitter, and it is difficult to demodulate the output signal of the PLL circuit having phase jitter in the stereo multiplex circuit. When used for
There was a problem that stereo distortion and stereo separation worsened. That is, in the PLL circuit shown in FIG. 2, when the stereo sum signal (L+R) is applied to the input terminal 1 along with the stereo pilot signal, and the level of the stereo sum signal becomes large, the phase comparator circuit 2 enters an incomplete switching state. , and a differential component occurs. When the differential component is amplified by the DC amplifier circuit 4 and applied to the VCO 5, the VCO 5 is modulated and phase jitter occurs, resulting in the above-mentioned characteristic deterioration. Further, the phase jitter also affects the pilot signal detection circuit of the stereo multiplex circuit, causing a problem of malfunction of stereo display.

(d) Means for Solving the Problems The present invention has been made in view of the above points, and includes a synchronous detection circuit that synchronously detects an input signal of a phase comparator circuit using an output signal of a frequency dividing circuit, and A lamp trigger circuit that generates an output signal for lighting a stereo display lamp according to the output signal of the detection circuit, and a control circuit that controls the gain of the DC amplifier circuit according to the output signal of the lamp trigger circuit,
The present invention is characterized in that when the PLL circuit locks onto the input signal and an output signal is generated from the lamp trigger circuit, the gain of the DC amplifier circuit is reduced by the control circuit.

(E) Effect According to the present invention, when comparing the phases of the input signal and the output signal of the frequency dividing circuit that divides the output signal of the VCO, the phases of the two signals do not match, and the PLL
When the circuit is not locked, the gain of the DC amplifier circuit can be set high to widen the lock range and to sufficiently widen the capture range. Further, in a state where the phases of the two signals match, the PLL circuit is locked, and an output signal is generated from the lamp trigger circuit, the gain of the DC amplifier circuit is lowered and the lock range is narrowed,
It is possible to measure the improvement of phase jitter. Furthermore, even if the phases of the two signals match and the PLL circuit locks, if the input signal is in a weak electric field and the lamp trigger circuit does not generate an output signal, the gain of the DC amplifier circuit is increased to widen the lock range. death,
It is possible to prevent the lock from slipping off.

(F) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention.
6 is an input terminal to which, for example, an FM stereo detection output signal is applied as an input signal; 7 is a VCO having a free-run frequency of 76 KHz; 8 is a frequency dividing circuit that divides the output signal of the VCO 7; 9 is a frequency divider for dividing the output signal of the VCO 7; a phase comparator circuit that compares the phase of the 19KHz stereo pilot signal of the frequency divider circuit 8 with the 19KHz frequency divided signal of the frequency divider circuit 8; 10 is a DC amplification circuit that amplifies the output signal of the phase comparator circuit 9 and applies it to the VCO 7;
11 is a synchronous detection circuit that synchronously detects the stereo pilot signal contained in the input signal using the frequency divided signal of the frequency dividing circuit 8; 12 is a stereo display lamp 13 according to the output signal of the synchronous detection circuit 11;
14 is a control circuit that controls the gain of the DC amplifier circuit 10 in accordance with the output signal of the lamp trigger circuit 12.

Phase comparison circuit 9, DC amplifier circuit 10, VCO 7
The frequency dividing circuit 8 and the frequency dividing circuit 8 constitute a normal PLL circuit, and PLL control is performed so that the phase of the output signal of the VCO 7 matches the phase of the input signal, but the details thereof will be omitted.

However, if the input signal applied to the input terminal 6 is a monaural signal, the PLL circuit will not lock because there is no 19KHz stereo pilot signal. Further, since the output signal of the synchronous detection circuit 11 is not generated, the stereo display lamp 13 is turned off and the control circuit 14 is not operated.

On the other hand, when the input signal is a stereo signal, the phase of the 19KHz stereo pilot signal in the stereo signal and the output signal of the frequency divider circuit 8 is compared in the phase comparator circuit 9, and PLL control is started. Said
At the start of PLL control, the PLL circuit is not yet locked, so the stereo pilot signal and the output signal of the frequency divider circuit 8 are out of phase, and the output signal of the synchronous detection circuit 11 is not generated.
Therefore, the output signal of the lamp trigger circuit 12 is not generated, the stereo display lamp 13 remains off, and the control circuit 14 does not operate. As a result, the gain of the DC amplifier circuit 10 becomes a relatively high first predetermined value, and the capture range of the PLL circuit can be kept wide. When the PLL control continues and the PLL circuit locks onto the stereo pilot signal in the input signal, the output signal of the frequency divider circuit 8 becomes synchronized with the stereo pilot signal, and the output signal of the synchronous detection circuit 11 is generated. When the output signal is generated, an output signal of the lamp trigger circuit 12 is generated accordingly, and the stereo indicator lamp 13 lights up to indicate that a stereo signal is being received. At the same time, the control circuit 14 operates to set the gain of the DC amplifier circuit 10 to a second predetermined value lower than the first predetermined value. When the gain of the DC amplifier circuit 10 decreases, the level of the control signal applied to the VCO 7 decreases, and accordingly, the level of unnecessary differential components generated from the phase comparator circuit 9 also decreases, eliminating phase jitter. . As a result, characteristic deterioration can be prevented,
Malfunctions of stereo display can also be prevented. Furthermore, PLL
When the circuit is locked, it does not matter if the capture range becomes narrower, so no new drawbacks will arise due to lowering the gain of the DC amplifier circuit 10. Furthermore, even when the PLL circuit locks on the stereo pilot signal, in a weak electric field where the level of the pilot signal is low, the output signal of the synchronous detection circuit 11 becomes low and the threshold of the lamp trigger circuit 12 becomes low. Since the voltage is below the level, the output signal of the lamp trigger circuit 12 is not generated and the stereo display lamp 13 is not lit.
In addition, the control circuit 14 also does not operate, and the DC amplifier circuit 1
A gain of 0 is the first predetermined value. Therefore, PLL
The lock range of the circuit becomes large, and loss of lock due to noise generated in a weak electric field can be prevented.
Incidentally, since the output signal of the lamp trigger circuit 12 is not generated, the receiver is not in a stereo reception state, and the output signal of the VCO 7 is not used for stereo demodulation, so phase jitter occurs in the output signal of the VCO 7. There is no problem either.

FIG. 3 shows a specific circuit for controlling the gain of the DC amplifier circuit. When the PLL circuit is not locked, no signal is applied to the input terminal 15, and the input transistor 16 constituting the control circuit 14 is not applied to the input terminal 15. And the current mirror circuit 17 is off.
Therefore, the output signal of the phase comparison circuit 9 is amplified by a DC amplifier circuit 10 including a pair of differentially connected transistors 18 and 19, and is output from an output terminal 20.
Applied to VCO7. At this time, since the gain of the DC amplifier circuit 10 is set to the first predetermined value, a wide capture range can be ensured. PLL
When the circuit is locked, an output signal is generated from the lamp trigger circuit 12, and an "H" signal is applied to the input terminal 15. Therefore, the input transistor 16 and the current mirror circuit 17 are turned on, the voltage drop across the resistor 21 increases, the emitter current of the current source transistor 22 decreases, and the mutual conductance (Gm) of the DC amplifier circuit 10 decreases. The gain decreases. As a result, the phase jitter of VCO7 is reduced,
Various characteristics are improved.

(G) Effects of the Invention As described above, according to the present invention, when the PLL circuit is not locked, the gain of the DC amplifier circuit can be maintained high, so a wide lock range and capture range can be secured. Also,
When the PLL circuit locks and an output signal is generated from the lamp trigger circuit, the gain of the DC amplifier circuit can be reduced, narrowing the lock range.
It is possible to improve VCO phase jitter, improve characteristics such as stereo distortion and stereo separation, and prevent malfunctions in stereo display. Furthermore, during weak electric field stereo reception where no output signal is generated from the lamp trigger circuit even if the PLL circuit is locked, the gain of the DC amplifier circuit can be increased to ensure a wide lock range, preventing lock loss due to noise, and reducing the electric field. When the strength returns to normal, stereo reception can be performed immediately.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional PLL circuit, and FIG.
The figure is a circuit diagram showing a specific example of the circuit shown in FIG. 7...VCO, 8...Frequency divider circuit, 9...Phase comparison circuit,
10... DC amplifier circuit, 11... Synchronous detection circuit, 12
...Lamp trigger circuit, 14...Control circuit.

Claims (1)

[Claims] 1. A phase comparator circuit that compares the phase of the input signal and the output signal of a frequency divider circuit that divides the output signal of the VCO and generates an output signal according to the phase difference, and a phase comparator circuit that amplifies the output signal of the phase comparator circuit. , a DC amplifier circuit that controls the oscillation frequency of the VCO by its output signal, and a synchronous detection circuit that synchronously detects the input signal using the output signal of the frequency dividing circuit; The lamp includes a lamp trigger circuit that generates an output signal for lighting a stereo display lamp according to an output signal, and a control circuit that controls the gain of the DC amplifier circuit according to the output signal of the lamp trigger circuit. During stereo reception when an output signal is generated from the trigger circuit, the gain of the DC amplifier circuit is reduced to narrow the lock range, and at the same time during monaural reception and weak electric field stereo reception when no output signal is generated from the lamp trigger circuit, the lock range is widened and locked. A PLL circuit characterized by preventing disconnection.