JP2011120038A - Video detection circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a video detection circuit in which, when an over-modulation state is detected, a video signal is prevented from being returned, and drifting in the VCO oscillation frequency of a PLL circuit is reduced. <P>SOLUTION: The video detection circuit includes: a PLL circuit for producing a reproduction carrier wave based on a video modulation signal (PIF signal) obtained by amplitude-modulating a carrier wave in accordance with a video signal; a VDET 23 which synchronizing-detects the video signal from the video modulation signal while using the reproduction carrier wave; a comparator 33 for detecting an over-modulation state where a video modulation degree of the video modulation signal exceeds a predetermined modulation degree threshold; and an inversion and switch circuit 34 for inverting the video modulation signal and outputting it to an APC 24 of a PLL circuit when the over-modulation state is detected by the comparator 33. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a video detection circuit that demodulates a video signal from a signal obtained by amplitude-modulating a carrier wave, and more particularly to a video detection circuit that supports an overmodulation state.

  A television broadcast receiver receives a television broadcast signal, down-converts the received signal into an intermediate frequency signal (IF signal: Intermediate Frequency), and demodulates a video signal, a color signal, and an audio signal from the IF signal.

FIG. 4 is a diagram showing a configuration of a conventional video intermediate frequency signal processing circuit (VIF circuit: Video Intermediate Frequency). The VIF circuit is a circuit that demodulates a video signal including luminance information from a video modulation signal (PIF signal) down-converted to an intermediate frequency.
As shown in FIG. 4, the VIF circuit includes an input terminal 1, an amplifier 2, a detector (VDET) 3, an automatic phase adjuster (APC) 4, a voltage controlled oscillator (VCO) 5, A phase shifter 6, an APC filter 7, a video amplifier (VAMP) 8, an output terminal 9, an automatic gain controller (AGC) 10, a sound trap circuit 11, and a comparator 12 are configured.

  A PIF signal is input from the input terminal 1. The PIF signal is amplified by the amplifier 2 and input to the VDET 3 and the APC 4. The APC 4, VCO 5 and phase shifter 6 constitute a phase-locked loop circuit (PLL circuit) and regenerate a carrier wave based on the inputted PIF signal. The phase shifter 6 generates two signals having a phase difference of ± 45 ° with respect to the signal generated by the VCO 5, returns one to the APC 4, and outputs the other to the VDET 3. The PLL circuit performs control so that the phase difference between the two signals input to the APC 4 is 90 °.

The APC 4 mixes an input signal having a phase difference of 90 °, and outputs a current I _APC corresponding to the phase shift amount δ between the phase difference between the two signals and the target value of 90 °. An APC filter 7 is connected to the output end of the APC 4. The APC filter 7 is an integrating circuit composed of a resistor and a capacitor, and cuts a high frequency component contained in the output signal of the _{APC 4} and smoothes the current I _APC temporally to generate a control voltage for the VCO 5.

  When the phase difference between the PIF signal input from the amplifier 2 to the APC 4 and the signal input from the phase shifter 6 to the APC 4 is controlled by the PLL circuit to be + 90 °, the signal input from the phase shifter 6 to the VDET 3 Becomes a reproduced carrier wave having the same frequency as the carrier wave of the PIF signal and a phase difference of 0 °. The VDET 3 receives the regenerated carrier wave from the phase shifter 6, mixes the PIF signal input from the amplifier 2 and the regenerated carrier wave, and extracts and outputs a video signal from the PIF signal. The extracted video signal is input to the VAMP 8 and the sound trap circuit 11.

  The sound trap circuit 11 includes a filter circuit that removes the audio carrier signal detected by being superimposed on the video signal. The VAMP 8 performs differential amplification between the video signal filtered by the sound trap circuit 11 and the reference potential directly input from the VDET 3 and outputs the result from the output terminal 9.

  The video signal output from the VAMP 8 is input to the AGC 10. The AGC 10 controls the gain of the amplifier 2 on the input side in accordance with the intensity of the output video signal, and adjusts the intensity of the output video signal within a proper level range.

  The comparator 12 determines overmodulation of the video signal. A video signal adjusted to an appropriate level is input to one input terminal of the comparator 12, and a predetermined reference potential corresponding to a threshold value for determining overmodulation is input to the other input terminal. As will be described later, the APC 4 is configured to control the loop gain of the PLL circuit in accordance with the determination result of the comparator 12.

  In Japan, for example, a value of 87.5% is set by the standard for terrestrial broadcasting in Japan, and a modulation state exceeding this is called overmodulation. Here, among various video media and broadcasts in other countries, there are some that generate an overmodulated PIF signal. In the overmodulation state, the amplitude of the PIF signal becomes minute and it becomes difficult to synchronize the PLL. In addition, in the overmodulation state exceeding 100% (hereinafter referred to as the strong overmodulation state), the video signal is less than 100%. Therefore, there is a problem that correct gradations cannot be reproduced on the screen.

  FIG. 5 is a schematic diagram of an example of a PIF signal and a video signal for explaining the aliasing. The original video signal 40 is an envelope connecting peaks of the PIF signal 41 having the same phase. In the period 42 in which the degree of video modulation exceeds 100% and the period 43 in which the degree of video modulation is less than 100%, the polarities of the PIF signal 41 are reversed. When such a PIF signal 41 is input to the APC 4, the PLL circuit follows the 180 ° phase shift caused by this inversion.

  As a result, the phase of the reproduced carrier wave input to VDET 3 is also shifted by 180 °, and in the period 42, the lower envelope indicated by the dotted line is detected as the video signal 44. In this way, since the video signal with the video modulation degree exceeding 100% is folded down around the line of 100%, this part becomes an unnatural video that becomes darker as the video modulation degree increases. End up.

In order to prevent this aliasing, the above-described conventional circuit is configured such that the _{APC 4} switches the output current I _APC to a weak value or 0 during overmodulation based on the determination result of the comparator 12. As a result, the loop gain of the PLL circuit is suppressed, and the PLL circuit is prevented from following a phase shift of 180 ° when the polarity of the PIF signal 41 is reversed, thereby preventing aliasing. (See Patent Documents 1 and 2)

  As another VIF circuit for preventing aliasing, a circuit that inverts the carrier wave generated by the VCO 5 during overmodulation and demodulates the video signal in the same way as during normal modulation is known. (See Patent Document 3)

JP 2008-11128 A JP 2009-55495 A JP 2007-336328 A

  The above-described conventional VIF circuit maintains the phase relationship between the PIF signal and the reproduced carrier wave in the locked state of the PLL circuit before the overmodulation state by suppressing the loop gain in the overmodulation state. However, if the loop gain of the PLL circuit is suppressed, the oscillation of the VCO 5 may be free-run, and for example, the drift of the oscillation frequency of the VCO 5 due to a change in the control voltage of the VCO 5 due to the discharge of the APC filter 7 may be stopped. become unable.

  For this reason, the phase relationship between the PIF signal and the reproduced carrier wave is not always suitably maintained in the overmodulation state. As a result, the phase of the regenerative carrier wave supplied to VDET3 fluctuates, and the accuracy of the video signal demodulated by VDET3 is lowered, resulting in a deterioration in image quality.

  In addition, the VIF circuit that inverts the carrier of the VCO 5 in the overmodulation state has a problem that the voltage of the APC 4 is greatly affected when the carrier is inverted, and buzz and image disturbance cannot be suppressed.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a video detection circuit capable of demodulating a suitable video signal even in an overmodulation state.

  The video detection circuit of the present invention includes a phase-locked loop circuit that generates a regenerated carrier wave based on a video modulation signal whose amplitude is modulated according to a video signal, and the video signal from the video modulation signal using the regenerated carrier wave. A detection circuit for synchronously detecting a signal, an overmodulation detection circuit for detecting an overmodulation state in which a video modulation degree of the video modulation signal exceeds a predetermined modulation degree threshold, and an overmodulation state detected by the overmodulation detection circuit An inverting switch circuit that inverts the video modulation signal and outputs the inverted signal to the automatic phase adjustment circuit of the phase-locked loop circuit.

  According to the video detection circuit of the present invention, when an overmodulation state is detected, an inversion circuit that inverts the video modulation signal and supplies it to the automatic phase adjustment circuit of the phase locked loop circuit is provided. Even at this time, there is no phase shift between the video modulation signal and the reproduced carrier wave. As a result, the video signal can be prevented from being folded.

  In addition, since the gain of the phase lock loop circuit is not suppressed as in the prior art, the drift of the VCO oscillation frequency of the phase lock loop circuit can be reduced.

  Further, since the video modulation signal is inverted when an overmodulation state is detected, the modulation degree of the video modulation signal is close to 100% and sufficiently small at this time. Thereby, there is little influence on APC (automatic phase adjustment circuit), and Buzz and disturbance of a picture are controlled.

1 is a schematic circuit diagram of a video detection circuit according to an embodiment of the present invention. It is a circuit diagram of the overmodulation detection circuit of the embodiment of the present invention. It is a circuit diagram of the inverting switch circuit of the embodiment of the present invention. It is a circuit diagram of the conventional video detection circuit. It is a wave form chart of an example of a PIF signal and a video signal explaining return of a video signal.

As shown in FIG. 1, an image detection circuit (VIF circuit) according to an embodiment of the present invention includes an input terminal 21, an amplifier 22, a detector (VDET) 23, an automatic phase adjuster (APC) 24, a voltage Voltage controlled oscillator (VCO) 25, phase shifter 26, APC filter 27, video amplifier (VAMP) 28, output terminal 29, automatic gain adjuster (AGC) 30, sound trap circuit 31, low-pass A filter (LPF) 32, a comparator 33, an inverting switch circuit 34, a sync separation circuit 35, an I ² C bus 36 and a register 37 are included.

  This VIF circuit can be configured as part of a semiconductor integrated circuit that processes television broadcast signals, for example.

  A PIF signal is input from the input terminal 21. The PIF signal is amplified by the amplifier 22 and input to the VDET 23 and the inverting switch circuit 34. The comparator 33 (an example of an “overmodulation detection circuit”) compares the video signal output from the VDET 23 with a reference potential Vref corresponding to a predetermined modulation degree threshold. The predetermined modulation degree threshold is preferably 100% in order to cope with a strong overmodulation state in which the folding of the video signal occurs as described above. In the present embodiment, among the pair of video signals output from the VDET 23, the video signal on the low potential side (for example, the video signal 40 in FIG. 5) is used as the video signal.

  Since the audio carrier signal is superimposed on the video signal output from the VDET 23, in order to eliminate this influence, the audio carrier signal is preferably removed through the LPF 32 and then input to the comparator 33. .

  When the video signal exceeds the predetermined modulation degree threshold by the comparator 33, the output of the comparator 33 becomes H level, and it is determined that it is in an overmodulation state. In this case, the inverting switch circuit 34 inverts the PIF signal according to the output of the comparator 33. The inverted PIF signal is input to the APC 24.

  On the other hand, when the video signal is less than the predetermined modulation degree threshold, the output of the comparator 33 is at the L level, and it is determined that the normal state. In response to the output of the comparator 33, the inverting switch circuit 34 is turned off. That is, the PIF signal is input to the APC 24 as it is without being inverted. In this case, the comparator 33 preferably has a hysteresis characteristic in order to stabilize against noise or the like.

  The APC 24, the VCO 25, and the phase shifter 26 form a phase-locked loop circuit (PLL circuit), and a carrier wave based on the PIF signal (inverted PIF signal in the case of an overmodulation state) input through the inverting switch circuit 34. Play. The phase shifter 26 generates two signals having a phase difference of ± 45 ° with respect to the signal generated by the VCO 25, returns one to the APC 24, and outputs the other to the VDET 23. The PLL circuit performs control so that the phase difference between the two signals input to the APC 24 is 90 °.

The APC 24 mixes an input signal having a phase difference of 90 °, and outputs a current I _APC corresponding to a phase shift amount δ between the phase difference between both signals and a target value of 90 °. An APC filter 27 is connected to the output end of the APC 24. The APC filter 27 is an integrating circuit composed of a resistor and a capacitor, and cuts a high frequency component included in the output signal of the _APC 24 and smoothes the current I _APC temporally to generate a control voltage for the VCO 25.

  The phase difference between the PIF signal input to the APC 24 from the amplifier 22 through the inverting switch circuit 34 (the inverted PIF signal in the case of an overmodulation state) and the signal input from the phase shifter 26 to the APC 24 is + 90 ° by the PLL circuit. If the control is performed, the signal input from the phase shifter 26 to the VDET 23 becomes a reproduced carrier wave having the same frequency as the carrier wave of the PIF signal and a phase difference of 0 °.

  The VDET 23 receives the regenerated carrier wave from the phase shifter 26, mixes the PIF signal input from the amplifier 22 and the regenerated carrier wave, and extracts and outputs a video signal from the PIF signal. The extracted video signal is input to the VAMP 28 and the sound trap circuit 31.

  The sound trap circuit 31 includes a filter circuit that removes an audio carrier signal detected by being superimposed on the video signal. The VAMP 28 amplifies the difference between the video signal filtered by the sound trap circuit 31 and the reference potential Vref output from the VDET 23 and outputs the amplified signal from the output terminal 29. In this case, it is preferable to use not the one video signal of the pair of video signals output from the VDET 23 but the center DC potential of the pair of video signals as the reference potential Vref. This is because it is sufficient to provide one sound trap circuit 31.

  The video signal output from the VAMP 28 is input to the AGC 30. The AGC 30 controls the gain of the amplifier 22 on the input side in accordance with the intensity of the output video signal, and adjusts the intensity of the output video signal within the appropriate level range.

  Thus, according to the VIF circuit of the present embodiment, the IF signal from the amplifier 22 is input to the APC 24 as it is in the normal state by providing the comparator 33 and the inverting switch circuit 34. In the modulation state, the IF signal inverted by the inverting switch circuit 34 is input to the APC 24, so that the folding of the video signal in the overmodulation state as shown in FIG. 5 is prevented.

  This is because, in the overmodulation state in which the modulation degree of the video signal exceeds 100%, as described above, the PIF signal is inverted and a phase shift of 180 ° occurs. However, according to the VIF circuit of this embodiment, the PIF The signal is further inverted to eliminate the phase shift. As a result, there is no phase shift of the reproduced carrier wave input to the VDET 23, and the phase difference between the PIF signal input to the VDET 23 and the reproduced carrier wave is maintained at 0 °.

  And according to the VIF circuit of this embodiment, since the gain of the phase lock loop is not suppressed as in the prior art, the drift of the oscillation frequency of the VCO 25 of the phase lock loop can be reduced.

  Further, since the PIF signal is inverted when an overmodulation state is detected, the modulation degree of the video modulation signal is close to 100% and sufficiently small at this time. Thereby, there is little influence on APC24 and Buzz and disturbance of a picture are controlled.

  Further, the comparator 33 is used to detect the overmodulation state by comparing the two outputs of the VDET 23 (the reference potential Vref and one video signal), so that the signal delay, the sound trap circuit 31 and the VAMP 28, There is no need to consider the offset voltage, and it is possible to easily cope with a sudden change in the video signal. Although this advantage is eliminated, the comparator 12 of the conventional VIF circuit can be used instead of the comparator 33.

  The inverting switch circuit 34 inverts the PIF signal in accordance with the output of the comparator 33. In addition to this condition, the reason why the PIF signal is inverted when the following conditions 1 to 3 are satisfied is described below. Is more preferable. When these conditions are absent, the inverting switch circuit 34 is off and does not invert the PIF signal. That is, the PIF signal is input to the APC 24 as it is.

  Condition 1 is that the PIF signal is above a certain level based on the AGC voltage of the AGC 30. In this case, the AGC voltage is compared with a predetermined threshold by a comparator, and the control signal S1 is output when the PIF signal is equal to or higher than a certain level based on the comparison result by the comparator. This is because, in a weak electric field with a low signal level, noise becomes relatively large, and the inverting switch circuit 34 may malfunction.

  Condition 2 is a video period in which a video signal has arrived. This is because signals in periods other than the video period are not overmodulated. In the example of FIG. 5, the inverting switch circuit 34 is turned on in the video signal period 50. Is configured to turn off.

  Condition 3 is that the PLL circuit is not in the reverse lock state. When the PLL circuit erroneously locks in phase at 270 °, the video signal output from the VDET 23 outputs a waveform that is inverted with reference to the reference potential Vref. In the example of the present embodiment, it is inverted to the high potential side with respect to the reference potential Vref. (Actually, the AGC 30 also malfunctions and the power supply potential Vcc is limited, so a beautiful inverted waveform is not obtained.)

  Therefore, when such an inversion lock state is established, the inversion switch circuit 34 is configured to be turned off so that the PLL circuit locks to a normal PIF signal phase that is not inverted. This is because in the inverted lock state, normal signal demodulation is not performed for one horizontal period until the next synchronization signal arrives, and horizontal line noise is generated on the screen.

  In this case, when the control signal S3 (the video signal output from the VAMP 28) is compared with a predetermined inversion lock threshold (set higher than the reference potential Vref), the output level of the VAMP 28 exceeds the predetermined inversion lock threshold. The inversion switch circuit 34 is preferably configured to be turned off when it is determined that the inversion lock state is established. The inversion lock threshold is set to a potential higher than the reference potential Vref.

The inverting switch circuit 34 is preferably configured to be able to be switched on / off in accordance with a control signal S4 from a signal bus, preferably the I ² C bus 36, from the viewpoint of improving user convenience. .

  That is, when the inverting switch circuit 34 is set to ON, the inverting switch circuit 34 inverts the PIF signal according to the comparison result of the comparator 33 when the conditions 1 to 3 are satisfied. On the other hand, when the inverting switch circuit 34 is set to OFF, the inverting switch circuit 34 does not perform the inverting operation even if the comparison result condition of the comparator 33 and the above conditions 1 to 3 are satisfied. That is, the PIF signal is input to the APC 24 as it is without being inverted.

[Specific configuration example of comparator and inverting switch circuit]
Hereinafter, specific configuration examples of the comparator 33 and the inverting switch circuit 34 will be described with reference to FIGS. In the circuit diagram of FIG. 1, the control signals S1 to S4 are input to the inverting switch circuit 34. However, in the circuit configuration example described here, the comparator 33 and the comparator 51 are controlled by the control signals S1 to S4. It has become.

As shown in FIG. 2, when the control of the above-described conditions 1 and 2 and the control of the inverting switch circuit 34 by the control signal S4 from the I ² C bus 36 are performed, the comparator 33 is controlled by the control signals S1, S2, and S4. Be controlled. When the inverting switch circuit 34 is controlled according to the condition 3, another comparator 51 is added.

When either of the conditions 1 and 2 is not satisfied (the level of the video signal is less than a certain level or outside the video period), or the comparator 33 receives the control signal S4 from the I ² C bus 36, When the inverting switch circuit 34 is set to OFF, its output is fixed at the L level. That is, the comparator 33 is turned off. In this case, the level of the reference potential Vref input to the comparator 33 is changed to Vref ′ so that the output of the comparator 33 is fixed at the L level. (Vref '> Vref)

On the other hand, when the conditions 1 and 2 are satisfied and the inverting switch circuit 34 is turned on by the control signal S4 from the I ² C bus 36, the comparator 33 is output from the VDET 23 as described above. And a reference potential Vref corresponding to a predetermined modulation degree threshold. The comparator 33 outputs an H level when the video signal exceeds the modulation degree threshold, and the comparator 33 outputs an L level when the video signal is smaller than the modulation degree threshold.

  The added comparator 51 corresponds to the condition 3 and compares the control signal S3 (video signal output from the VAMP 28) with a predetermined inversion lock threshold generated by the voltage source 52. When the control signal S3 exceeds the inversion lock threshold, the output of the comparator 51 is inverted from H level to L level.

  The outputs of the two comparators 33 and 51 are input to the AND circuit 53 and output from the AND circuit 53 as the control signal C1 of the inverting switch circuit 34. Another control signal C2 of the inverting switch circuit 34 is output as a signal obtained by inverting the control signal C1 by the inverter 54.

  FIG. 3 is a specific circuit diagram of the inverting switch circuit 34. The inverting switch circuit 34 is a circuit that inverts or passes the PIF signal from the amplifier 22 in accordance with the control signals C1 and C2, and includes NPN transistors Q1 to Q6, load resistors R1 and R2, and output terminals. 55, including a constant current source 56.

  The inverting switch circuit 34 includes differential transistors Q1 and Q2 and switching transistors Q3, Q4, Q5, and Q6. The collector of the transistor Q4 is the collector of the transistor Q6, and the collector of the transistor Q5 is the transistor Q3. Are cross-connected to each collector.

  The PIF signal is a pair of differential signals, and the pair of differential signals is applied to the bases of the transistors Q1 and Q2, respectively. The control signal C1 is applied to the bases of the transistors Q3 and Q6. The control signal C2 is applied to the common base of the transistors Q4 and Q5.

  When the control signal C1 is at the H level and the control signal C2 is at the L level, the transistors Q3 and Q6 are turned on and the transistors Q4 and Q5 are turned off. As a result, an inverted PIF signal is output from the output terminal 55. On the other hand, when the control signal C1 is L level and the control signal C2 is H level, the transistors Q3 and Q6 are turned off and the transistors Q4 and Q5 are turned on. As a result, the PIF signal is output from the output terminal 55 without being inverted.

The above operations are summarized as follows. That is, when the conditions 1 to 3 are satisfied and the inverting switch circuit 34 is turned on by the control signal S4 from the I ² C bus 36, the output of the comparator 51 becomes H level, and the comparator 33 Turns on. When the comparator 33 detects an overmodulation state, the output of the comparator 33 becomes H level, so that the control signal C1 becomes H level and the control signal C2 becomes L level. Thereby, the inverting switch circuit 34 inverts the PIF signal.

On the other hand, if any one of the conditions 1 to 3 is not satisfied or the inverting switch circuit 34 is set to OFF by the control signal S4 from the I ² C bus 36, one of the comparator 33 and the comparator 51 Since the output becomes L level, the control signal C1 becomes L level and the control signal C2 becomes H level. Thereby, the inverting switch circuit 34 outputs the PIF signal as it is without being inverted, that is, the PIF signal.

In other words, when the inverting switch circuit 34 is turned on by the control signal S4 from the I ² C bus 36, the comparator 33 is turned on on condition that the conditions 1 to 3 are satisfied. When the inverting switch circuit 34 is set to OFF by the control signal S4 from the I ² C bus 36, even if the conditions 1 to 3 are satisfied, the comparator 33 is in the OFF state and inverts the PIF signal. Output as is. The inverting switch circuit 34 outputs the PIF signal as it is without inverting it.

21 Input Terminal 22 Amplifier 23 Detector 24 APC 25 VCO 26 Phase Shifter 27 APC Filter 28 VAMP 29 Output Terminal 30 AGC
31 Sound Trap Circuit 32 LPF 33 Comparator 34 Inverting Switch Circuit 35 Sync Separation Circuit 36 I ² C Bus 37 Register

Claims (6)

A phase-locked loop circuit that generates a reproduced carrier wave based on a video modulation signal whose amplitude is modulated according to the video signal; and
A detection circuit for synchronously detecting the video signal from the video modulation signal using the reproduced carrier wave;
An overmodulation detection circuit for detecting an overmodulation state in which the video modulation degree of the video modulation signal exceeds a predetermined modulation degree threshold;
And an inverting switch circuit that inverts the video modulation signal and outputs it to the automatic phase adjustment circuit of the phase-locked loop circuit when an overmodulation state is detected by the overmodulation detection circuit. circuit.   The overmodulation detection circuit includes a comparator that compares the video signal output from the detection circuit with a reference potential corresponding to the predetermined modulation degree threshold, and when the video signal exceeds the reference potential, The video detection circuit according to claim 1, wherein the overmodulation state is detected.   3. The inverting switch circuit is configured to output the video modulation signal to the automatic phase adjustment circuit without inverting the video modulation signal when the video modulation signal is less than a certain level. The video detection circuit described.   The inversion switch circuit is configured to output the video modulation signal to the automatic phase adjustment circuit without inversion during a period other than the video signal period in which the video signal arrives. Item 4. The video detection circuit according to any one of Items 1 to 3.   5. The inversion switch circuit is configured to output the video modulation signal to the automatic phase adjustment circuit without inversion when the phase lock loop circuit is in an inversion lock state. The video detection circuit according to any one of the above.   6. The video detection circuit according to claim 1, wherein the inverting switch circuit is configured to be capable of on / off switching in accordance with a control signal from a signal bus.

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