JP3024913B2 - Synchronous signal processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization signal processing circuit in a television receiver, and more particularly to a synchronization signal processing circuit in a television receiver. A synchronous signal processing circuit.

[0002]

2. Description of the Related Art FIG. 8 is a block diagram showing an electrical configuration of a synchronization signal processing circuit 1 in a typical prior art vehicle-mounted television receiver. The horizontal synchronization signal separated by the synchronization separation circuit from the composite video signal demodulated by the detection circuit is input from a terminal P1.

The input horizontal synchronizing signal is compared in the phase comparator 2 with a phase difference between the input horizontal synchronizing signal and an output horizontal synchronizing signal output from the terminal P3 to a driving circuit for the deflection coil, as will be described later. An error signal corresponding to the phase difference is output from the phase comparator 2, smoothed by a low-pass filter (LPF) 3, and then input to the voltage-controlled oscillator 4.

The voltage-controlled oscillator 4 outputs an oscillation signal having a frequency corresponding to the input voltage. However, when the frequency of the input horizontal synchronizing signal input to the terminal P1 and the frequency of the output horizontal synchronizing signal output from the terminal P3 are fo, oscillation is performed at a frequency of 2fo. The oscillating signal from the voltage controlled oscillator 4 is frequency-divided by a frequency divider 5 to １ ／, and then output to the terminal P3 and to the phase comparator 2. In this way, a so-called phase lock loop (abbreviated PLL) is formed, an automatic frequency control (abbreviated AFC) operation is realized, and a stable output horizontal synchronizing signal is created.

[0005]

In the synchronous signal processing circuit 1 as described above, when the composite video signal is shown in FIG.
Electric field strength level is 30 dB as shown before time α1
Although a relatively stable horizontal synchronizing signal as shown in FIG. 9 (2) can be obtained with a medium electric field to a weak electric field of about μV, the electric field is cut off from the weak electric field as indicated by reference numeral α2 in FIG. 9 (1). Is frequently repeated, AF
The C operation becomes unstable, and reference sign α in FIG.
There is a problem that the synchronization disorder occurs as shown in FIG. 3 and as shown in FIG.

[0006] Once the above-mentioned synchronization disorder occurs,
When the reception state returns to a good state and the time constant of the LPF 3 is large and the response speed of the AFC operation is low,
The time required to synchronize the output horizontal synchronization signal with the input horizontal synchronization signal becomes longer. At this time, LPF
If the time constant of (3) is reduced to increase the response speed of the AFC operation, there is a problem that it becomes easy to react to an impulse-like disturbance of the input horizontal synchronization signal, and the synchronization disturbance easily occurs.

Another prior art for solving such a problem is disclosed in Japanese Patent Publication No. 54-13143. This prior art is configured to switch the time constant of the low-pass filter between when a weak electric field is input from an antenna and when a strong input is made from a video tape recorder.

However, the switching operation is performed in response to the RFAGC voltage to the high-frequency amplifier circuit, so that there is a problem that the response speed is low.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a synchronous circuit capable of reducing synchronization disturbance with high responsiveness even in a situation where a weak electric field and a radio wave cutoff frequently occur such that the extraction of a synchronization signal becomes unstable. It is to provide a signal processing circuit.

[0010]

According to the present invention, there is provided a phase comparator for comparing an input horizontal synchronization signal input from a synchronization separation circuit with an output horizontal synchronization signal and outputting an error signal corresponding to a phase difference between the two. A low-pass filter that smoothes and outputs an error signal from the phase comparator, and a voltage-controlled oscillator that oscillates at a frequency corresponding to the output voltage from the low-pass filter and creates the output horizontal synchronization signal. A synchronization signal processing circuit, provided in association with the low-pass filter, for changing a time constant of the low-pass filter, and a horizontal synchronization signal or a vertical synchronization signal from the synchronization separation circuit, and reset by a predetermined frequency. A counter for counting at a time, comparing means for comparing a predetermined value with a value immediately before the count value is reset, and Image deterioration detecting means for detecting image deterioration due to lack of at least one of the horizontal synchronizing signal and vertical synchronizing signal or a timing shift, and the deterioration is detected in response to a detection result of the image deterioration detecting means. A synchronizing signal processing circuit including a control unit for increasing the time constant of the low-pass filter by the time constant changing unit. Further, the time constant changing means of the present invention includes an IFAGC signal for controlling the gain of the intermediate frequency amplification circuit corresponding to the intermediate frequency signal level or the demodulated video signal level, in the detection result of the video deterioration detecting means. It is characterized by being level-converted and provided accordingly.

[0011]

According to the present invention, the input horizontal synchronizing signal separated by the sync separation circuit from the composite video signal detected by the detection circuit is applied to one input of a phase comparator forming a phase lock loop. An output horizontal synchronizing signal output to a drive circuit for a deflection coil of a cathode ray tube or the like is input to the other input of the phase comparator. The phase comparator compares the input horizontal sync signal with the output horizontal sync signal,
An error signal corresponding to the phase difference between the two is output. The error signal is smoothed in a low-pass filter and applied to a voltage-controlled oscillator. Therefore, the voltage-controlled oscillator oscillates at a frequency corresponding to the error signal level to generate the output horizontal synchronizing signal. The AFC operation is realized by the PLL thus formed.

In the synchronous signal processing circuit formed as described above, according to the present invention, for example, a resistor interposed in series with a signal line and a capacitor interposed in parallel between the signal line and a ground line are used. In connection with the low-pass filter realized by the integrating circuit, the time-constant changing means realized by, for example, a resistor inserted in parallel with the resistor or the like so that the time constant of the low-pass filter can be changed. Provided.

The degree of deterioration of the video signal is detected by the video deterioration detecting means. The image deterioration detecting means detects the deterioration of the image signal based on at least one of the input horizontal synchronizing signal and the input vertical synchronizing signal missing or a timing shift. In particular, according to the present invention, the counter is reset by the horizontal synchronizing signal or the vertical synchronizing signal from the synchronizing separation circuit, and the count value immediately before resetting of the counter is compared with a predetermined value by comparing means. The image deterioration caused by the lack of the horizontal synchronization signal or the vertical synchronization signal from the separation circuit or the timing shift is detected by the image deterioration detection means, and the time constant of the low-pass filter is increased by the control means when the image is deteriorated. Deterioration can be detected quickly. This is particularly preferable in an in-vehicle television receiver or the like.

When the deterioration of the video signal is detected in this way,
The control means causes the time constant changing means to increase the time constant of the low-pass filter. As a result, the time constant of the low-pass filter increases, and thus the loop gain of the PLL decreases, and even if the input horizontal synchronization signal is disturbed in synchronization, the output horizontal synchronization signal can be output stably. When the deterioration of the video signal is improved, the time constant of the low-pass filter is reduced, the loop gain of the PLL is reduced, and the output horizontal synchronizing signal can be quickly followed by stabilizing the output horizontal synchronizing signal. Further, by detecting the deterioration detection from the lack or the timing shift of the input horizontal synchronizing signal or the input vertical synchronizing signal, the deterioration detection can be quickly performed.

Preferably, the time constant changing means includes an IFAGC signal for controlling a gain of the intermediate frequency amplifier circuit, which is a value corresponding to an intermediate frequency signal level or a demodulated video signal level, of the detecting means. The level is converted according to the detection result and given. Therefore, the IFAGC signal that changes the gain of the intermediate frequency amplifier circuit in accordance with the electric field strength level has a level corresponding to the degree of deterioration of the video signal. You can set a constant.

[0016]

FIG. 1 is a block diagram showing an electric configuration of a synchronous signal processing circuit 11 according to one embodiment of the present invention. FIG. 2 is a block diagram of an in-vehicle television receiver 12 provided with the synchronous signal processing circuit 11. FIG. 3 is a block diagram illustrating an electrical configuration. The received signal received by the antenna 13 is input from the tuning circuit 14 to the high-frequency amplifier circuit 15 and amplified, and then, via the tuning circuit 16, a signal component near the frequency band of the broadcast station to be received is mixed by the mixer. 17 is input. The mixer 17
Further, a local oscillation signal corresponding to the reception frequency from the local oscillation circuit 18 is input to the. This local oscillation circuit 1
The oscillation frequency of 8 and the tuning frequencies of the tuning circuits 14 and 16 are controlled by a control circuit 19.

When the television broadcast wave is transmitted in the upper sideband system, the intermediate frequency signal from the mixer 17 is filtered by a filter 20 realized by a high-pass filter, so that a desired band component is filtered. Circuit 2
After being amplified by 1, it is input to the video detection circuit 22. The composite video signal demodulated by the video detection circuit 22 is amplified by the video amplification circuit 23 and then input to the color demodulation circuit 24 and the synchronization signal processing circuit 11. by this,
From the color demodulation circuit 24, the video signals of the three primary colors RGB are demodulated and, for example, when the display device 25 is a cathode ray tube, is input to the cathode. The synchronization signal demodulated by the synchronization signal processing circuit 11 is input to a circuit for driving a deflection coil of the display device 25, for example.

On the other hand, an audio intermediate frequency signal is also extracted from the intermediate frequency amplifier circuit 21, and this audio intermediate frequency signal is amplified by an audio intermediate frequency amplifier circuit 26 and then input to an audio detection circuit 27. The audio signal demodulated by the audio detection circuit 27 is amplified by an audio amplification circuit 28, and then is applied to a speaker 29 to be acousticized.

The output from the video amplifier circuit 23 is
The luminance level detection circuit 31 detects the luminance level from the composite video signal and supplies the detection result to the detection circuit 32. The detection circuit 32 smoothes the output corresponding to the brightness level from the brightness level detection circuit 31 and provides the output to the intermediate frequency control circuit 33. The intermediate frequency control circuit 33 outputs, from the input output of the detection circuit 32, an IFAGC signal whose level decreases as the luminance level decreases, and increases the gain of the intermediate frequency amplifier circuit 21. When the input electric field intensity level to the input terminal 13 becomes about 50 dBμV or less, the gain of the intermediate frequency amplification circuit 21 is increased, and the IFAGC operation by the weak electric field detection is performed.

The output from the detection circuit 32 is supplied to a high frequency control circuit 34 via the intermediate frequency control circuit 33. The high frequency control circuit 34
An RFAGC signal whose level becomes higher as the input electric field strength level becomes higher is output. For example, when the tuning degree of the high frequency amplifier circuit 15 is lowered, for example, when the input electric field strength level becomes 50 dBμV or more, a strong electric field is generated. And performs an RFAGC operation to suppress the antenna input level in order to suppress distortion in the mixing circuit 17 and the like.

Referring to FIG. 1, the composite video signal demodulated by the video detection circuit 22 is input to a sync separation circuit 41 from an input terminal P11, and an input horizontal and vertical sync signal is extracted. The phase difference between the extracted input horizontal synchronization signal and the output horizontal synchronization signal output from the output terminal P13 to the driving circuit of the deflection coil and the like is compared in the phase comparator 42 as described later. An error signal corresponding to the phase difference is output from the phase comparator 42 and smoothed by the LPF 43.
4 is input.

The voltage controlled oscillator 44 outputs an oscillation signal having a frequency corresponding to the input voltage. However,
When the frequency of the input horizontal synchronization signal extracted by the synchronization separation circuit 41 and the frequency of the output horizontal synchronization signal output from the output terminal P13 are fo, oscillation is performed at a frequency of 2fo. An oscillation signal from the voltage controlled oscillator 44 is divided by a frequency divider 45
After being frequency-divided by で, the signal is output to the output terminal P13 and is also provided to the phase comparator 42. Thus, a so-called PLL is formed, the AFC operation is realized, and a stable output horizontal synchronizing signal is created.

On the other hand, the input vertical synchronizing signal extracted by the synchronizing separation circuit 41 is supplied to a counter 47 through a gate circuit 46.
Has been entered. In response to the output from the gate circuit 46, that is, when the input vertical synchronizing signal is input, the counter 47 resets its count value and counts the pulse of the oscillation signal from the voltage controlled oscillator 44. . The counter 47 operates the gate circuit 46 for a predetermined period from the input timing of the input vertical synchronization signal.
To the gate circuit 46.
Prohibits the input of the input vertical synchronization signal from being accepted for the predetermined period. This function is used to disable the input and stabilize the period of the vertical synchronization signal even if the input vertical synchronization signal input at a substantially constant period is input within the predetermined period due to the influence of a reflected wave or the like. belongs to.

The gate circuit 46 activates the counter 48 via the counter 47 in accordance with the predetermined period and the input vertical synchronizing signal. When the counter 48 is started, the output of the output vertical synchronizing signal from the counter 48 to the output terminal P14 to the drive circuit of the deflection coil or the like is started, and when the count value of the counter 48 reaches a predetermined value, The output of the output vertical synchronization signal is stopped. In this way, even for a vertical synchronization signal that is less frequent than the horizontal synchronization signal, an output generated based on the input horizontal synchronization signal is used in order to suppress the influence of the lack of the input vertical synchronization signal. The vertical synchronizing signal is configured to be output at a substantially constant cycle.

The synchronization signal processing circuit 1 thus configured
1, in the present invention, a time constant changing circuit 51 and a deterioration detecting circuit 71 are further provided in association with the LPF 43. The time constant changing circuit 51 responds to whether or not the deterioration of the video signal is detected by the deterioration detection circuit 71 which is a detecting means for detecting the deterioration of the video signal, and responds to the weak electric field from the intermediate frequency control circuit 33. The level of the IFAGC signal, whose level is lowered, is
3 to change the time constant of the LPF 43.

FIG. 3 is an electric circuit diagram showing a specific configuration of the LPF 43 and the time constant changing circuit 51 provided in connection therewith. The LPF 43 includes a resistor R1 interposed in series with a signal line 52 from the phase comparator 42 to the voltage controlled oscillator 44, and a capacitor C1 interposed between the signal line 52 and a ground line. This is realized by an integrating circuit.

On the other hand, the time constant changing circuit 51 includes a current limiting resistor R2 and a photocoupler 53. The output from the deterioration detection circuit 71 is applied to the anode of the light emitting diode D1 of the photocoupler 53 via the current limiting resistor 52, and the light emitting diode D1 emits light at a light amount corresponding to the level of the IFAGC signal.
In response, the resistance of the resistor R3 of the photocoupler 53 connected in parallel with the resistor R1 changes.

FIG. 4 shows the state of the change of the IFAGC voltage with respect to the electric field intensity level. That is, when the electric field intensity level decreases and the gain of the intermediate frequency amplification circuit 21 needs to be increased, the level of the IFAGC signal is increased. Becomes lower. This IFAGC signal is supplied to the deterioration detection circuit 71.
As described later, a signal whose voltage level decreases as the electric field strength level increases is input to the diode D1 of the photocoupler 53. by this,
When the resistance values of the resistors R1 and R3 are indicated by the same reference numerals, the combined resistance value represented by R1 · R3 / (R1 + R3) becomes low. Therefore, the time constant of the LPF 43 decreases, that is, the cutoff frequency increases as shown in FIG. 5, and the loop gain of the PLL decreases. Thus, when the electric field strength level is high, the AFC operation can be performed at a high response speed, and when the electric field strength level is low, the loop gain of the PLL becomes small, and the PLL is stable against the lack of the input horizontal synchronization signal. By performing the AFC operation, an output horizontal synchronizing signal can be obtained.

In this way, when the input horizontal synchronizing signal is disturbed, the time constant of the LPF 43 is increased, so that the occurrence of synchronizing disturbance to the output horizontal synchronizing signal can be suppressed. Converges, the time constant of the LPF 43 becomes smaller, and the output horizontal synchronizing signal can be quickly followed with good responsiveness.

FIG. 6 is a block diagram showing a specific configuration of the deterioration detection circuit 71. The deterioration detection circuit 71 includes a horizontal synchronization detection unit 72, a vertical synchronization detection unit 73, an AND gate 74, and a level conversion circuit 61. The horizontal synchronization detection unit 72 includes a free counter 75 to which the horizontal synchronization signal from the synchronization separation circuit 41 is provided, an inversion buffer 76 to which the horizontal synchronization signal is also provided,
A comparator 77 to which an output from the free counter 75 is provided;
And a comparator 79 to which an output from the flip-flop 78 is provided.
A that adds the outputs from the comparators 77 and 79 and outputs
The configuration includes an ND gate 80 and setting circuits 81 and 82.

From the synchronization separation circuit 41, FIG.
Is input to the reset terminal R11 of the free counter 75. As a result, the free counter 75 is reset as shown in FIG. 7 (2), and restarts the counting operation based on the color burst frequency of 3.579545 MHz, for example, 14.31818 MHz, which is four times the frequency, for example. An output representing the count value of the free counter 75 is provided to the input terminal A11 of the comparator 77. A reference value obtained by adding a redundant value N to a count value 910 corresponding to one horizontal synchronization period is input from the setting circuit 81 to another input terminal B11 of the comparator 77. Therefore, in FIG.
As shown by 1, when the horizontal synchronizing signal is lost at time t1 and the count value of the free counter 75 exceeds 910 and increases by the redundant value N, the comparison is made at time t2 as shown in FIG. A low-level output is derived from the unit 77 and is applied to one input of an AND gate 80.

On the other hand, the horizontal synchronizing signal from the synchronizing separation circuit 41 also
After the polarity inversion is performed as shown in (4), it is supplied to the clock input terminal CK11 of the flip-flop 78. The count value from the free counter 75 is given to the input terminal D11 of the flip-flop 78. Therefore, in this flip-flop 78, the count value of the free counter 75 latched in response to the horizontal synchronizing signal is normally a value close to the count value 910, but is indicated by reference numeral β2 in FIG. As described above, when the timing of the horizontal synchronization signal shifts due to multipath, fading, or the like, the value becomes smaller than the value 910.

This latch output is applied to one input terminal A12 of comparator 79. Further, a reference value corresponding to the value obtained by subtracting the redundant value N from the count value 910 from the setting circuit 82 is given to the other input terminal B12 of the comparator 79. 7
As shown in (5), at time t4, which is earlier than the time t3 when the original horizontal synchronizing signal is input by the redundancy value N,
If noise is input before, AND from that time t5
A low-level output is derived from the other input of the gate 80. Therefore, from the AND gate 80, FIG.
Is output to the AND gate 74. In this way, the deterioration of the video signal is detected due to the lack of the horizontal synchronization signal or the timing shift of the horizontal synchronization signal.

The vertical synchronization detecting section 73 has the same configuration as that of the horizontal synchronization detecting section 72. Corresponding portions are denoted by the same reference numerals with the suffix a. However, in the comparators 77 and 79, the input terminals B11a and B12a
Each of the setting circuits 81a and 82a sets a value obtained by adding or subtracting a redundant value to or from a count value 20475 corresponding to one water direct synchronization cycle.

The flip-flops 78 and 78a are
The count value provided for a plurality of bits and latched by each flip-flop 78, 78a is:
The digital data is supplied to comparators 79 and 79a.

In this manner, from the output of the AND gate 74, the deterioration of the video signal can be detected from the missing pulse or the timing shift of the horizontal synchronizing signal or the vertical synchronizing signal.

The output from the AND gate 74 is input to the level conversion circuit 61. This level conversion circuit 61
Two variable resistors 62, 63 and their movable pieces 62a,
The output voltage from 63a is applied to individual contacts 64a, 64, respectively.
b. The IFA is connected to one terminal of each of the variable resistors 62 and 63.
The GC signal is supplied, and the other terminal is grounded. The movable piece 62a of the variable resistor 62 is displaced to the one terminal side.
The signal is output at almost the same voltage. On the other hand, the movable piece 63a of the variable resistor 63 is displaced to the other terminal side, so that the IFAGC signal is output with its level suppressed.

The change-over switch 64 sets the AN to a low level when the lack of the input horizontal synchronizing signal or the input vertical synchronizing signal or the timing shift is not detected and during a strong electric field.
In response to the high-level output from the D gate 74, the node 64b becomes conductive, and the IFAGC signal is suppressed and output from the common node 64c to the time constant changing circuit 51. On the other hand, when the input horizontal synchronizing signal or the input vertical synchronizing signal is lost or the timing shift is detected, A
When a low level output is derived from the ND gate 74,
It conducts to the individual contact 64a and outputs the IFAGC signal almost as it is.

In this way, the level of the above-mentioned IFAGC voltage is converted, and when the deterioration of the video signal is detected, the IFAGC signal is output to the time constant changing circuit 51 as it is, and the resistance value of the resistor R3 in the time constant changing circuit 51 is changed. By increasing the value, the loop gain of the PLL can be reduced, and a stable AFC operation can be performed.

As described above, by detecting the deterioration of the video signal from the missing pulse or the timing shift of the input horizontal synchronizing signal and the vertical synchronizing signal, it is possible to detect immediately when the deterioration occurs, and to detect the deterioration of the AGC signal. The response speed can be improved as compared with the case where deterioration detection is performed. Further, the IFAGC signal also corresponds to the degree of deterioration, so that the time constant of the LPF 43 can be set more accurately.

[0041]

As described above, according to the present invention, the time constant related to the low-pass filter constituting the phase lock loop for performing the AFC operation for obtaining the stable output horizontal synchronization signal following the input horizontal synchronization signal is obtained. When the deterioration of the video signal is detected by the deterioration detecting means from the lack of at least one of the input horizontal synchronizing signal and the input vertical synchronizing signal or the timing shift, the time constant changing means outputs the time constant of the low-pass filter. When the deterioration of the video signal is detected, the time constant of the low-pass filter becomes large, and therefore the loop gain of the PLL becomes small. Can be output stably, and when the deterioration of the video signal is improved, the time constant of the low-pass filter becomes smaller. Is the loop gain of the PLL is decreased, quickly follow to the input horizontal synchronizing signal output horizontal sync signal can be stabilized. In particular, according to the present invention, the counter is reset by the horizontal or vertical synchronization signal from the synchronization separation circuit, and the count value immediately before the reset of the counter is compared with a predetermined value by comparing means. Is detected, it is possible to quickly detect the deterioration of the received video, which is particularly preferable for an in-vehicle television receiver or the like.

Further, the deterioration can be detected promptly by performing the deterioration detection based on the missing or timing shift of the input horizontal synchronization signal or the input vertical synchronization signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an electrical configuration of a synchronization signal processing circuit 11 according to one embodiment of the present invention.

FIG. 2 is a block diagram showing an electrical configuration of a television receiver 12 in which the synchronization signal processing circuit 11 is used.

FIG. 3 shows an LPF 43 in the synchronization signal processing circuit 11;
5 is an electric circuit diagram showing a specific configuration of a time constant changing circuit 51. FIG.

FIG. 4 is a graph showing a change in an IFAGC signal level from an intermediate frequency control circuit 33 with respect to an electric field intensity level.

FIG. 5 shows the LP with respect to a change in the IFAGC signal level.
It is a graph which shows the change of the cutoff frequency of F43.

FIG. 6 is a block diagram showing a specific configuration of a deterioration detection circuit 71.

FIG. 7 is a timing chart for explaining the operation of the deterioration detection circuit 71.

FIG. 8 is a block diagram showing an electrical configuration of a synchronization signal processing circuit 1 in a typical prior art vehicle-mounted television receiver.

FIG. 9 is a waveform diagram for explaining synchronization disturbance due to lack of a synchronization signal in the synchronization signal processing circuit 1;

FIG. 10 is a diagram illustrating an example of a display image when the synchronization disorder occurs.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Synchronous signal processing circuit 12 Television receiver 21 Intermediate frequency amplification circuit 22 Video detection circuit 31 Brightness level detection circuit 32 Detection circuit 33 Intermediate frequency control circuit 34 High frequency control circuit 41 Synchronization separation circuit 42 Phase comparator 43 LPF 44 Voltage control type Oscillator 45 Divider 46 Gate circuit 47, 48 Counter 51 Time constant changing circuit 53 Photocoupler 71 Degradation detection circuit 72 Horizontal synchronization detection unit 73 Vertical synchronization detection unit

Continuation of front page (56) References JP-A-2-302190 (JP, A) JP-A-1-147969 (JP, A) JP-A-55-141833 (JP, A) JP-A-58-187077 (JP) JP-A-50-114116 (JP, A) JP-A-58-204677 (JP, A) JP-A-3-117177 (JP, A) JP-A-58-210770 (JP, A) 62-152558 (JP, U) JP-A-1-97673 (JP, U) JP-B-59-38792 (JP, B2) JP-B-61-32869 (JP, B2) JP-B-57-502084 (JP, U) A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H04N 5/05 H04N 5/44

Claims (2)

(57) [Claims] 1. A phase comparator for comparing an input horizontal synchronization signal input from a synchronization separation circuit with an output horizontal synchronization signal, and outputting an error signal corresponding to a phase difference between the two. A low-pass filter for smoothing and outputting an error signal, and a voltage-controlled oscillator for oscillating at a frequency corresponding to an output voltage from the low-pass filter to generate the output horizontal synchronization signal; A time constant changing means provided in association with the filter to change a time constant of the low-pass filter; a counter reset by a horizontal synchronization signal or a vertical synchronization signal from a synchronization separation circuit and counting at a predetermined frequency; Comparing means for comparing the value thus obtained with the value immediately before the count value is reset, and a horizontal synchronizing signal or Video degradation detection means for detecting video degradation due to lack of at least one of the direct synchronization signals or a timing shift; and responding to a detection result of the video degradation detection means, wherein when the degradation is detected, the time constant Control means for increasing the time constant of the low-pass filter by changing means. 2. An IFAGC signal for controlling a gain of an intermediate frequency amplifying circuit corresponding to an intermediate frequency signal level or a demodulated video signal level, said time constant changing means includes:
2. The synchronization signal processing circuit according to claim 1, wherein a level is converted and applied in accordance with a detection result of said video deterioration detecting means.