JPH08116466A - Synchronizing signal processing circuit - Google Patents

Abstract

PURPOSE: To reduce disturbance in synchronization in the synchronizing signal processing circuit for an on-vehicle television receiver in which a weak electric field strength or interruption of radio waves takes place frequently. CONSTITUTION: A composite video signal from a terminal P11 is delayed in a line memory 32 by one line via an A/D converter 31 and outputted from a terminal P12 via a D/A converter 33. Furthermore, a video signal is given alternately to a delay memory M1 or M2 via switches SW0, SW1 for each line and stored therein and the video signal of one preceding line is given to a correlation device 37 via a switch SW2. Furthermore, the video signal is given to the correlation device 37 via a delay memory M3. A deviation of two lines is obtained by the correlation device 37 and counters C1-C3 and a horizontal synchronizing signal received via a synchronizing separator circuit 34 and an AFC circuit 35 is adjusted by a timing adjustment circuit 36 and the result is outputted from a terminal P13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing signal processing circuit in a television receiver, and more particularly, it is preferably implemented in an on-vehicle television receiver in which a weak electric field and radio wave interruption frequently occur. And a synchronous signal processing circuit.

[0002]

2. Description of the Related Art FIG. 12 is a block diagram showing an electrical configuration of a sync signal processing circuit 1 in a typical conventional vehicle-mounted television receiver. The horizontal and vertical sync signals separated by the sync separation circuit from the composite video signal demodulated by the detection circuit are input terminals P respectively.
It is input from 1, P2.

The phase difference between the input horizontal synchronizing signal input and the output horizontal synchronizing signal output from the output terminal P3 to the driving circuit of the deflection coil is compared in the phase comparator 2 as described later. . From this phase comparator 2,
An error signal corresponding to the phase difference is output, smoothed by a low pass filter (abbreviated as LPF) 3, and then input to a voltage controlled oscillator 4.

The voltage controlled oscillator 4 outputs an oscillation signal having a frequency corresponding to the input voltage. However, the frequencies of the input horizontal synchronizing signal input to the input terminal P1 and the output horizontal synchronizing signal output from the output terminal P3 are fo
Then, oscillation is performed at a frequency of 2fo. The oscillating signal from the voltage controlled oscillator 4 is divided by the frequency divider 5 into 1/2 and then output to the output terminal P3.
It is given to the phase comparator 2. Thus, a so-called phase lock loop (abbreviated as PLL) is formed, automatic frequency control (abbreviated as AFC) operation is realized, and a stable output horizontal synchronizing signal is created.

On the other hand, the vertical synchronizing signal input from the input terminal P2 is input to the counter 7 via the gate circuit 6. The counter 7 resets the count value in response to the output from the gate circuit 6, that is, when the vertical synchronizing signal is input, and counts the number of pulses of the oscillation signal from the voltage controlled oscillator 4. . The counter 7 outputs a prohibition signal to the gate circuit 6 for a predetermined period from the input timing of the vertical synchronization signal, whereby the gate circuit 6 prohibits the input of the vertical synchronization signal for the predetermined period. To do. This function is for stabilizing the cycle of the vertical synchronizing signal by invalidating the input even if the vertical synchronizing signal input at a substantially constant cycle is input within the predetermined period due to the influence of a reflected wave or the like. It is a thing.

The gate circuit 6 activates the counter 8 via the counter 7 in response to the predetermined period and the input vertical synchronizing signal. When the counter 8 is activated, the output of the vertical synchronizing signal from the counter 8 to the output terminal P4 is started to the deflection coil drive circuit and the like, and when the count value of the counter 8 reaches a predetermined value, The output of the vertical synchronizing signal is stopped. In this way, the vertical sync signal generated based on the horizontal sync signal is suppressed even in the case of the vertical sync signal, which is less frequent than the horizontal sync signal, in order to suppress the influence of the missing vertical sync signal. The signal is configured to be output at a substantially constant period.

[0007]

In the synchronizing signal processing circuit 1 as described above, when the composite video signal is shown in FIG. 13A, the electric field strength level is 30 as shown before time α1.
In a medium electric field to weak electric field of about dB μV, a relatively stable horizontal synchronizing signal and vertical synchronizing signal as shown in FIG. 13 (2) can be obtained.
In the situation where the electric wave interruption as indicated by the reference numeral α2 is frequently repeated, the AFC operation becomes unstable,
There is a problem that synchronization disturbance occurs as shown by reference numeral α3 in FIG. 13 (2) and as shown in FIG.

As another conventional technique, Japanese Patent Laid-Open No. 4-68 is known.
670 is mentioned. In this conventional technique, an input synchronizing signal is used as an external synchronizing signal, an internal synchronizing signal is always created in response to the external synchronizing signal, and when the external synchronizing signal is lost, the internal synchronizing signal is switched to. It is a thing.

However, since this prior art also uses the synchronizing signal in the received composite video signal, if this synchronizing signal is frequently lost, there is a problem that stable operation cannot be performed.

An object of the present invention is to provide a synchronization signal processing circuit capable of reducing synchronization disturbance even in a situation where a weak electric field and radio wave interruption frequently occur such that synchronization signal extraction becomes unstable. Is to provide.

[0011]

According to the present invention, there are provided first and second counters which are reset when a horizontal synchronizing signal included in a composite video signal is input to start a counting operation, and a predetermined line of the video signal. In one horizontal scanning period, a memory capable of storing the video signal from a predetermined first value to a second value of the count value of the first counter, and an image of a line next to the predetermined line. The signal is sequentially checked against the stored contents of the memory in accordance with the counting operation of the second counter, and a correlator that outputs a count value when the correlation between both lines becomes maximum and a correlator A synchronizing signal processing circuit, comprising: a correction unit that corrects and outputs the timing of the horizontal synchronizing signal according to the difference between a count value and the first value. Further, the correlator of the present invention, the level of each pixel of the video signal of a predetermined line stored in the memory,
Comparing means for comparing the level of each pixel of the video signal of the next line for each count operation of the second counter, and calculation for obtaining the sum of the level difference of each pixel between the predetermined line and the next line. Means and latch means for latching the value of the second counter when the sum total becomes the minimum value. Still further, the correlator of the present invention counts the level of each pixel of the video signal of the next line to the level of each pixel of the video signal of the predetermined line stored in the memory. Comparing means for comparing each of them, computing means for obtaining the number of pixels whose comparison results in the comparing means match, and latch means for latching the value of the second counter when the number of pixels becomes the maximum value. It is characterized by including. Further, the correlator of the present invention provides a first calculating means for obtaining an average level of all the video signals of a predetermined line stored in a memory, and a video signal of the predetermined line of the video signal of the next line. The average level calculated by the second calculation means is the highest among the average level calculated by the second calculation means, which calculates the average level for the corresponding number of pixels for each count operation of the second counter, and the average level calculated by the first calculation means. Latching means for latching the value of the second counter when the values are close to each other. Furthermore, the correlator of the present invention is the first correlator corresponding to the pixel of the maximum level of the video signal stored in the memory.
The correcting means includes first comparing means for obtaining the value of the counter and second comparing means for obtaining the value of the second counter corresponding to the maximum level pixel of the video signal of the next line.
It is characterized in that the timing of the horizontal synchronizing signal is corrected and output according to the difference between the value obtained by the second comparing means and the value obtained by the first comparing means. Further, the correlator of the present invention comprises first comparing means for obtaining the value of the first counter corresponding to the minimum level pixel of the video signal stored in the memory, and the minimum level pixel of the video signal of the next line. And a second comparing means for obtaining the value of the second counter corresponding to the above, wherein the correcting means corresponds to the difference between the value obtained by the second comparing means and the value obtained by the first comparing means, It is characterized in that the timing of the horizontal synchronizing signal is corrected and output.

[0012]

According to the present invention, two counters, a first counter and a second counter, are provided, and these counters are reset after reset in response to a horizontal synchronizing signal included in the composite video signal detected by the detection circuit. Start the counting operation. The count value of the first counter is given to a memory, and the memory predetermines the count value of the first counter in one horizontal scanning period of a predetermined line of the video signal, for example, a line near the center of the screen. For example, the video signal is stored from the first value to the second value corresponding to the central portion of the screen.

On the other hand, the count value of the second counter is input to a correlator, and the correlator outputs the video signal of the line next to the predetermined line of the memory in accordance with the counting operation of the second counter. The stored contents, that is, the video signal in the predetermined area on the predetermined line is sequentially checked. From the check result, the count value of the second counter when the correlation between the two lines becomes maximum is output.

Specifically, the correlator counts the level of each pixel of the video signal of a predetermined line stored in the memory for each pixel and the level of each pixel of the video signal of the next line in the second counter. Comparison for each operation, that is, a comparison means compares the video signal of the next line that is sequentially input with the count operation with the video signal of a predetermined line, and the comparison result of the level difference for each pixel for each count operation The value of the second counter when the correlation becomes maximum can be obtained by latching the value of the second counter when the sum is at the minimum value with the latching means.

That is, for example, when the vertical stripe pattern is displayed on the screen and the synchronization signal is not disturbed, the correlation between the predetermined line and the next line is maximized and latched. The count value of the second counter becomes equal to the first value of the first counter. The correction means corrects the timing of the horizontal synchronization signal and outputs it, corresponding to the difference between the count value output from the correlator and the first value.

Therefore, the deviation of the synchronization signal can be detected from the deviation of the image based on the video signal component occupying most of the period of the video signal, and the weak electric field and the radio wave interruption frequently occur. However, the occurrence of synchronization disorder can be suppressed.

Further, preferably, the correlator comprises: the comparing means; a calculating means for obtaining the number of pixels whose comparison results in the comparing means match; and a second counter when the number of pixels becomes the maximum value. It may be configured to include a latch means for latching a value. Still more preferably, the correlator determines a first average level of all the pixels of the video signal of the predetermined line stored in the memory.
In the calculation means and the video signal of the next line, when the video signal of the next line is input, the average level of the number of pixels corresponding to the video signal of the predetermined line is counted by the second counter. The second computing means that sequentially obtains the response and the average level sequentially obtained by the second computing means is the first
Latch means for latching the value of the second counter when the value is closest to the average level obtained by the arithmetic means may be provided and configured.

Furthermore, the first correlator obtains the maximum level of the video signal stored in the memory, that is, the value of the first counter corresponding to the white pixel, that is, the first pixel from the left end of the image. The comparing means and the second comparing means for obtaining the value of the second counter corresponding to the maximum level pixel of the video signal of the next line, that is, the number of the pixel from the left end of the screen, and the first and second comparing means. A correction unit for correcting the timing of the horizontal synchronization signal according to the difference in the values obtained by the second comparison unit may be provided and configured. Furthermore, instead of the maximum level, the minimum level, that is, black pixels may be compared.

[0019]

1 is a block diagram showing the electrical construction of a sync signal processing circuit 11 according to an embodiment of the present invention, and FIG. 2 shows an on-vehicle television receiver 12 equipped with the sync signal processing circuit 11. It is a block diagram which shows an electric constitution. The reception signal received by the antenna 13 is input from the tuning circuit 14 to the high-frequency amplifier circuit 15 and amplified, and then further passed through the tuning circuit 16 to mix the signal components near the frequency band of the broadcasting station to be received. 17 is input. The mixer 17
Further, a local oscillation signal corresponding to the reception frequency from the local oscillation circuit 18 is input to. This local oscillator circuit 1
The oscillation frequency of 8 and the tuning frequencies of the tuning circuits 14 and 16 are controlled by the control circuit 19.

When the television broadcast wave is transmitted in the upper sideband system, the intermediate frequency signal from the mixer 17 has a desired band component filtered by the filter 21 realized by a high pass filter, and the intermediate frequency signal is amplified. Circuit 2
After being amplified by 2, it is input to the video detection circuit 23. The composite video signal demodulated by the video detection circuit 23 is input to the color demodulation circuit 24 and the sync signal processing circuit 11. As a result, the color demodulation circuit 24 outputs RGB signals.
The video signals of the three primary colors are demodulated, and, for example, the display device 2
When 5 is a cathode ray tube, it is input to the cathode. The synchronization signal demodulated by the synchronization signal processing circuit 11 is input to the display device 25, for example, a circuit for driving a deflection coil.

On the other hand, an audio intermediate frequency signal is also extracted from the intermediate frequency amplifying circuit 22, the audio intermediate frequency signal is amplified by the audio intermediate frequency amplifying circuit 26, and then input to the audio detecting circuit 27. The audio signal demodulated by the audio detection circuit 27 is amplified by the audio amplification circuit 28 and then given to the speaker 29 to be sonicated.

Referring to FIG. 1, the video signal detected by the video detection circuit 23 is analog / input from the input terminal P11.
After being input to the digital (A / D) converter 31 and converted into a digital signal, and delayed by one horizontal scanning period in the line memory 32, that is, 63.5 μsec, the digital / analog (D / A) converter 33 It is restored to an analog signal and input to the color demodulation circuit 24 from the output terminal P12. In this way, the video component of the video signal is delayed by the one horizontal scanning period and then input to the color demodulation circuit 24. The analog / digital converter 31, the line memory 32, and the digital / analog converter 33 are driven based on the system clock supplied from the control circuit 19 or the like in FIG. 1 via the input terminal P15.

The composite video signal from the input terminal P11 is applied to the sync separation circuit 34 to extract the horizontal sync signal and the vertical sync signal, and the horizontal sync signal is input to the AFC circuit 35. The AFC circuit 35 includes a phase comparator for comparing the phase difference between the horizontal sync signal input from the sync separation circuit 34 and the horizontal sync signal to be output from the AFC circuit 35, and the phase output from the phase comparator. The LPF that smoothes the error output corresponding to the phase difference, the voltage-controlled oscillator that oscillates the signal of the frequency corresponding to the output voltage of the LPF, and the output from the voltage-controlled oscillator are set so as to correspond to the horizontal synchronizing frequency. , A frequency divider that divides the frequency into 1/2 and outputs the frequency divided.

The horizontal synchronizing signal from the AFC circuit 35 is input to the timing adjusting circuit 36. The timing adjustment circuit 36 further adjusts the timing of the horizontal synchronizing signal after the AFC operation as described later, and then supplies the horizontal synchronizing signal from the output terminal 13 to the display device 25 as well as a gate circuit and two counters. In response to the vertical sync signal separated by the sync separation circuit 34, the vertical sync signal is created based on the horizontal sync signal,
It is given to the display device 25 from the output terminal P14.

The video signal converted into a digital signal by the analog / digital converter 31 is also switched by the switch SW0.
Are alternately input to the two delay memories M1 and M2 via the changeover switch SW1 every horizontal scanning cycle.
When one of the delay memories M1 and M2 is being written with the changeover switch SW1 being conducting, the stored content is read from the other side to the correlator 37 via the changeover switch SW2. . In connection with this correlator 37, the delay memories M1, M2 are also
Is provided with a delay memory M3 configured in the same manner as
The video signal from the analog / digital converter 31 is input to the correlator 37 via the delay memory M3. Therefore, the correlator 37 is supplied with the video signal from the delay memory M1 or M2 for the previous one horizontal scanning period, and as will be described later, the video signal input from the delay memory M3 is checked to correlate the two. Desired.

The correlator 37 is reset in response to the horizontal synchronizing signal output from the AFC circuit 35, and is output from the counter C2 which performs a counting operation in a cycle equal to the conversion cycle of the analog / digital converter 31. The count value is input. Further, a counter C1 similar to the counter C2 is provided, the counter C1 is reset in response to the horizontal synchronizing signal, and performs a counting operation at a cycle equal to the conversion cycle of the analog / digital converter 31, During a period of a predetermined count value A1 to A2, the switch SW0 is turned on and the analog / digital converter 3
1 and the changeover switch SW1 are connected, and the count value A1 is given to the timing counter C3.

The correlator 37 is a delay memory M1 or M2.
The video signal of the next line input via the delay memory M3 is sequentially checked with the video signal of the line previous by one horizontal scanning cycle input from the counter C2 when the correlation between the two is highest. The count value B1 of the above is output to the timing counter C3. Timing counter C3
Calculates the difference between the count value A1 of the counter C1 and the count value B1 of the counter C2, and outputs the difference to the timing adjustment circuit 36. The timing adjusting circuit 36 delays or accelerates the output timing of the horizontal synchronizing signal to be output to the output terminal P13 by the time obtained by multiplying the count value difference A1-B1 by the count cycle T, and outputs the delayed timing. Along with this, the timing of the vertical synchronizing signal to be output to the output terminal P14 is also delayed or advanced. The timing counter C3 and the timing adjusting circuit 36 are
Compensating means.

FIG. 3 is a block diagram showing a concrete configuration of the correlator 37. The correlator 37 has n subtractors K
1, K2, ..., Kn and absolute value calculators J1, J2
, Jn and n-1 adders H1, H2, ..., H (n
-1), a comparator 41, and latch circuits 42 and 43.

The delay memories M1 and M2 have memory cells D1, D2, ..., Dn so as to be able to store n pixels, and an nth-order delay circuit is provided from the memory cells Dn to D1. Operate. The video signal from the analog / digital converter 31 is first input to the memory cells Dn of the delay memories M1 and M2, and every time the subsequent video signal is digitally converted and input, the input video signal is The memory contents in each of the memory cells D1 to Dn are updated in this manner during the period in which the switches SW0 are sequentially turned on and the video signals are sequentially input while being sequentially shifted to the memory cell D1 side. Similarly, the delay memory M3 is also composed of n memory cells G1, G2, ..., Gn,
The video signal input from the analog / digital converter 31 is sequentially shifted from the memory cell Gn side to the G1 side for each digital conversion.

Each of the memory cells D1 to Dn, G1 to Gn
The stored contents of are input to the correlator 37, and the subtractors K1 to Kn as the comparison means calculate the difference in the stored contents of the corresponding cells, that is, the level difference for each pixel. The calculation results are calculated into absolute values in absolute value calculators J1 to Jn and then added in adders H1 to H (n-1) to calculate the sum of them. The absolute value calculators J1 to Jn and the adders H1 to H (n-1) form a calculator.

The sum of the level differences for each pixel thus obtained is one input D1 of the comparator 41 and the latch circuit 42.
Has been entered in and. The other input E1 of this comparator 41
, The level latched by the latch circuit 42 is input to the comparator 41, and the comparator 41 inputs the levels lower than the level latched by the latch circuit 42 to the adders H1 to H (n-1). Output from the high level to the latch circuits 42 and 43. As a result, the contents stored in the latch circuit 42 are added to the adders H1 to H1.
The minimum value of the level input from (n-1) is stored.

A counter C2 is provided to the latch circuit 43.
Of the adder H1 from the latch circuit 43 to the timing counter C3.
The count value at the timing when the input level from ~ H (n-1) reaches the minimum value is latched and output. The comparator 41 and the latch circuits 42 and 43 are
It constitutes a latch means. In this way, the correlator 37 outputs the video signal of the current line input to the delay memory M3,
When the difference from the previous video signal for one horizontal scanning period stored in the delay memories M1 and M2 is the smallest, it is determined that the correlation is the largest, and the count value of the second counter C2 is transferred to the timing counter C3. Output.

That is, in the delay memories M1 and M2, 63.5 in the predetermined line L1 of the display screen shown in FIG.
In the horizontal scanning period of μsec, as shown in FIG. 5A, for example, several tens of μsec elapses from the time t1 when the count value of the counter C1 reset by the horizontal synchronization signal becomes A1 at the timing shown by time t0. The level of each pixel until time t2 when the corresponding count value A2 is reached is stored in the memory cells D1 to Dn.

On the other hand, to the delay memory M3, the level of the video signal of the line next to the predetermined line L1 shown by reference numeral L2 in FIG. 4 is as shown in FIG. 5 (2).
The counter C2 is reset and then sequentially read at the synchronization timing of the time t0, and the stored contents of the memory cells G1 to Gn are constantly updated. Changeover switch SW1
Of the memory contents D1 to Dn of the delay memory M1M2 fixed by switching to the other delay memory side, the delay memory M3 being sequentially updated.
The stored contents of the corresponding memory cells G1 to Gn are checked, and from the check result, the time t1a, which is the data input period at the time when the correlation has the smallest value, as described above.
Count values B1 and B2 of the counter C2 corresponding to t2a
Among them, the count value B1 and the count value A1 are compared by the timing counter C3.

As a result, when the horizontal synchronizing signal of the predetermined line indicated by reference numeral L1 in FIG. 4 is shown in FIG. 6A, the reference numeral L2 is added to the horizontal synchronizing signal of the predetermined line.
When the horizontal synchronizing signal of the next line indicated by (1) advances by the period corresponding to the count value A1-B1 as shown in FIG. 6B, the timing adjusting circuit 36 causes the horizontal synchronizing signal from the AFC circuit 35 to count the horizontal synchronizing signal. Value A1-B1 and counter C
It is delayed by the integrated value of the count cycle T of 1 and C2 and output to the output terminal P13.

Further, the horizontal synchronizing signal created based on the newly created horizontal synchronizing signal is output to the output terminal P14. Further, the video signal output to the output terminal P12 is delayed by one horizontal scanning cycle in the line memory 32. Therefore, the video signal of the next line L2 is horizontally adjusted on the line L2 adjusted by the timing adjustment circuit 36. It will be output in agreement with the synchronization signal.

As described above, in the sync signal processing circuit 11 according to the present invention, the horizontal sync signals having a short output period are not compared with each other, but the correlation between the video signal of the predetermined line L1 and the video signal of the next line L2 is determined. Since the amount of deviation of the horizontal synchronization signal when it becomes the maximum is calculated and the horizontal synchronization signal is corrected, the synchronization disturbance can be suppressed even in a situation where a weak electric field and radio wave interruption frequently occur.

FIG. 7 shows a correlator 37a according to another embodiment of the present invention.
FIG. 4 is a block diagram showing the electrical configuration of this embodiment, and this embodiment is similar to the embodiment shown in FIG. In this embodiment, the absolute value calculator J1 to
The output of Jn is given to one input of the comparators P1 to Pn, and the other input of these comparators P1 to Pn is
The reference voltage Vref from the reference voltage source 44 is given. The absolute value calculators J1 to Jn, the comparators P1 to Pn, and the reference voltage source 44 constitute a calculation means, and each comparator P
1 to Pn derive high level outputs to lines Q1 to Qn when the outputs from the absolute value calculators J1 to Jn are less than the reference voltage Vref, that is, when there is almost no level difference between corresponding pixels. .

Each of the lines Q1 to Qn has a comparator 41a.
Input D2 and the latch circuit 42a. From the latch circuit 42a, the comparator 41
The maximum value of the number of high-level lines is output to the other input E2 of a, and the comparator 41a outputs lines Q1 to Q1.
When the number of high-level lines of Qn becomes larger than the number of lines input from the latch circuit 42a, a high-level output is derived to the latch circuit 42a to store the number of lines at that time. The latch circuit 43 stores the count value of the counter C2 at that time. In this way, the correlation may be obtained from the number of pixels in which the corresponding pixels match each other.

FIG. 8 is a block diagram showing the electrical construction of a correlator 37b according to still another embodiment of the present invention, in which parts corresponding to those in the above-mentioned embodiment are designated by the same reference numerals. In this embodiment, the contents stored in the memory cells D1 to Dn are stored in the adder R.
1 to R (n-1), the total sums thereof are added, and then the divider 47 divides by the number of pixels n to obtain an average level for each pixel. Has been entered in the input of. Corresponding to this, the memory cells G1 to G
The stored contents of n are added by adders S1 to S (n-1) to obtain the sum thereof, and then the average value is calculated by the divider 48, and the average value is given to the other input of the subtractor 49. ing. The adders R1 to R (n-1) and the divider 47 form a first calculating means, and the adders S1 to S (n-1) and the divider 48 form a second calculating means.

The subtractor 49 subtracts the average level calculated by the divider 48 from the average level calculated by the divider 47, and the subtraction result is calculated by the absolute value calculator 50 into an absolute value, and then the comparator. It is given to one input D3 of 41 and is inputted to the latch circuit 42. This comparator 4
The output from the latch circuit 42 is applied to the other input E3 of 1 and the comparator 41 operates as an absolute value calculator 50.
When the output from the latch circuit 42 becomes smaller than the output of the latch circuit 42, a high level output is derived, the stored content of the latch circuit 42 is updated, and the count value of the counter C2 is latched by the latch circuit 43 and output to the timing counter C3. Let

Therefore, in this correlator 37b, the average level of all the video signals stored in the delay memories M1 and M2 over all pixels and the average level of all the video signals stored in the delay memory M3 over all pixels are the highest. The value of the second counter C2 when the values are close to each other is latched and output. Also in this case, the correlation between the video signals of the delay memories M1 and M2 and the video signal of the delay memory M3 can be obtained.

FIG. 9 shows a correlator 37c according to another embodiment of the present invention.
It is a block diagram showing the electrical configuration of the above, and the same reference numerals are attached to the portions corresponding to the above-mentioned embodiments. In this embodiment, from the stored contents of the memory cells D1 to Dn, the n-1th-order maximum value calculators U1 to U (n-1) sequentially select large values, and thus the maximum value is selected and the subtractor is selected. 49
Given to one input of. On the other hand, the memory cell G
Similarly, from the stored contents of 1 to Gn, the maximum values are calculated by the n-1th-order maximum value calculators V1 to V (n-1),
It is given to the other input of the subtractor 49.

As shown in FIG. 10, the maximum value calculator U1 comprises a comparator 51 and a multiplexer 52. The outputs from the memory cell D1 and the maximum value calculator U2 are input to the comparator 51, respectively. When the output level on the memory cell D1 side is higher than the output level on the maximum value calculator U2 side, the comparator 51 outputs the same. , High level output is applied to the input terminal W3 of the multiplexer 52.

The multiplexer 52 has two individual contacts W
1, W2 and a single common contact W0. The output of the memory cell D1 is applied to one individual contact W1 and the maximum value calculator U is applied to the other individual contact W2.
Two outputs are provided. From the common contact W0, the subtracter 4
The output to 9 is derived. The multiplexer 52 conducts the common contact W0 to the individual contact W1 side when the input terminal W3 is at the high level, and conducts to the individual contact W2 side when the input terminal W3 is at the low level.

Therefore, of the outputs from memory cell D1 or maximum value calculator U2, the larger output is derived to subtractor 49. The remaining maximum value calculators U2 to U (n-1) and V1 to V (n-1) are also configured similarly to the maximum value calculator U1.

The subtractor 49 calculates the difference between the maximum value on the delay memory M1 and M2 side and the maximum value on the delay memory M3 side, and the difference is calculated by the absolute value calculator 50 and then compared. It is input to one input D4 of the container 41 and is also supplied to the latch circuit 42. The output of the latch circuit 42 is given to the other input E4 of the comparator 41,
When the input value becomes smaller than the value latched by the latch circuit 42, the comparator 41 derives a high level output to the latch circuit 42 and the latch circuit 43 to update the stored contents of the latch circuits 42, 43. .

Therefore, in the correlator 37c, the maximum values of the stored contents of the delay memories M1 and M2 and the stored contents of the delay memory M3, that is, the levels of colors close to white are compared with each other, and the pixels having the maximum levels are compared. The shift amount of the synchronization signal is obtained by the shift between the two, and the correlation may be obtained in this way.

FIG. 11 is a block diagram showing the electrical construction of a correlator 37d according to still another embodiment of the present invention. This embodiment is similar to the embodiment shown in FIG. 9 and the corresponding parts are not shown. The same reference numerals are attached. In the embodiment shown in FIG. 9, the storage contents of the memory cells D1 to Dn are the maximum value calculators U1 to U.
While the maximum values of them were obtained in (n-1),
In this embodiment, the minimum value is calculated by the minimum value calculators W1 to W (n-1) and given to one input of the subtractor 49. Similarly, in the above-mentioned embodiments, the memory cells G1 to
In the memory contents of Gn, those maximum values are obtained by the maximum value calculators V1 to V (n-1), whereas in the present embodiment,
The minimum value is calculated by the minimum value calculators X1 to X (n-1) and given to the other input of the comparator 49.

In this way, the shift amount of the video signal may be obtained by the minimum value of the stored contents of each of the delay memories M1 and M2 and the delay memory M3, that is, the color close to black.

In each of the above-described embodiments, the correlation between the input video signal and the video signal one line before is obtained, but the correlation between adjacent lines is obtained using the frame memory. You may do it.

[0052]

As described above, according to the present invention, two counters for starting the counting operation after resetting in response to the horizontal synchronizing signal are provided, and one horizontal scanning period for a predetermined line, for example, a line near the center of the screen. In the first counter, the video signal is stored in the memory from the first value to the second value of the count value, and in the correlator, the video signal of the line next to the predetermined line is stored in the second counter. The contents stored in the memory are sequentially checked in accordance with the counting operation, and the correction means determines the timing of the horizontal synchronizing signal in accordance with the difference between the count value and the first value when the correlation between the two lines becomes maximum. Is corrected and output, it is possible to detect the deviation of the sync signal from the deviation of the video based on the video signal component that occupies most of the time period in the video signal, and the weak electric field and radio wave interruption frequently occur. Even in a situation such as raw, it is possible to suppress the occurrence of synchronization disturbance.

[Brief description of drawings]

FIG. 1 is a block diagram showing an electrical configuration of a sync signal processing circuit 11 according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an electrical configuration of a television receiver 12 in which the synchronization signal processing circuit 11 is used.

FIG. 3 is a correlator 37 in the synchronization signal processing circuit 11.
3 is a block diagram showing a specific configuration of FIG.

FIG. 4 is a diagram showing an example of a display screen for explaining the operation of the correlator 37.

FIG. 5 is a timing chart for explaining the operation of the correlator 37.

FIG. 6 is a waveform diagram for explaining a timing adjustment operation of a horizontal synchronization signal.

FIG. 7 is a block diagram showing an electrical configuration of a correlator 37a according to another embodiment of the present invention.

FIG. 8 is a block diagram showing an electrical configuration of a correlator 37b according to still another embodiment of the present invention.

FIG. 9 is a block diagram showing an electrical configuration of a correlator 37c of another embodiment of the present invention.

FIG. 10 is a maximum value calculator U1 in the correlator 37c.
3 is a block diagram showing a specific configuration of FIG.

FIG. 11 is a block diagram showing an electrical configuration of a correlator 37d according to still another embodiment of the present invention.

FIG. 12 is a block diagram showing an electrical configuration of a synchronization signal processing circuit 1 in a typical conventional vehicle-mounted television receiver.

FIG. 13 is a waveform diagram for explaining synchronization disorder due to a lack of a synchronization signal in the synchronization signal processing circuit 1.

FIG. 14 is a diagram showing an example of a display image when the synchronization disorder occurs.

[Explanation of symbols]

11 sync signal processing circuit 12 television receiver 23 video detection circuit 32 line memory 34 sync separation circuit 35 AFC circuit 36 timing adjustment circuit 37, 37a, 37b, 37c, 37d correlator 41, 41a; P1 to Pn comparator 42, 42a, 43 Latch circuit 47, 48 Divider 49, K1 to Kn Subtractor 50, J1 to Jn Absolute value calculator 9 C1, C2 Counter C3 Timing counter D1 to Dn, G1 to Gn Memory cells H1 to H (n-1 ), R1 to R (n-1), S1 to S
(N-1) Adder U1 to U (n-1), V1 to V (n-1) Maximum value calculator W1 to W (n-1), X1-X (n-1) Minimum value calculator

Claims (6)

[Claims] 1. First and second counters which are reset when a horizontal synchronizing signal included in a composite video signal is input to start a counting operation, and the first counter in a horizontal scanning period of a predetermined line of the video signal. A memory capable of storing the video signal from a predetermined first value to a second value of the count value of the 1 counter; and a video signal of the line next to the predetermined line, counted by the second counter. A correlator that sequentially checks the stored contents of the memory according to the operation and outputs a count value when the correlation between both lines becomes maximum, and a count value output from the correlator and the first value A synchronizing signal processing circuit for correcting and outputting the timing of the horizontal synchronizing signal in accordance with the difference between 2. The correlator sets the level of each pixel of the video signal of a predetermined line stored in the memory to each pixel and the level of each pixel of the video signal of the next line to the counting operation of the second counter. Comparing means for comparing each of them, computing means for obtaining the sum of the level differences of each pixel between the predetermined line and the next line, and a latch for latching the value of the second counter when the sum is the minimum value. The synchronizing signal processing circuit according to claim 1, further comprising: 3. The correlator sets the level of each pixel of the video signal of a predetermined line stored in the memory and the level of each pixel of the video signal of the next line to the counting operation of the second counter. Comparing means for comparing each of them, computing means for obtaining the number of pixels whose comparison results in the comparing means match, and latching means for latching the value of the second counter when the number of pixels becomes the maximum value. Claim 1 characterized by including.
The synchronization signal processing circuit described. 4. The correlator includes first computing means for obtaining an average level of all the video signals of a predetermined line stored in a memory, and the video signal of the predetermined line of the video signal of the next line. The second calculating means for obtaining the average level corresponding to the number of pixels for each counting operation of the second counter, and the average level obtained by the second calculating means in addition to the average level obtained by the first calculating means. 2. The synchronizing signal processing circuit according to claim 1, further comprising a latch unit that latches the value of the second counter when the value becomes the closest value. 5. The correlator comprises first comparing means for obtaining a value of a first counter corresponding to a maximum level pixel of the video signal stored in the memory, and a maximum level of the video signal of the next line. A second comparing means for obtaining a value of the second counter corresponding to the pixel, wherein the correcting means corresponds to a difference between the value obtained by the second comparing means and the value obtained by the first comparing means. 2. The synchronization signal processing circuit according to claim 1, wherein the timing of the horizontal synchronization signal is corrected and output. 6. The correlator comprises first comparing means for obtaining a value of a first counter corresponding to a pixel of the minimum level of the video signal stored in the memory, and a minimum level of the video signal of the next line. A second comparing means for obtaining a value of the second counter corresponding to the pixel, wherein the correcting means corresponds to a difference between the value obtained by the second comparing means and the value obtained by the first comparing means. 2. The synchronization signal processing circuit according to claim 1, wherein the timing of the horizontal synchronization signal is corrected and output.