JPH0526846Y2 - - Google Patents

Description

[Detailed description of the invention] This invention relates to a stereo demodulation device that combines a stereo composite signal with a switching signal obtained by multiplying a pilot signal included in a stereo composite signal, and separates left and right stereo signals from the stereo composite signal. .

FIG. 1 shows a conventional stereo demodulator. A stereo composite signal is applied to the input terminal 2 from an FM demodulation circuit (not shown), and this stereo composite signal is input to a phase-locked loop {PLL (Phase-Locked Loop) circuit} 6 via an amplifier 4. The signal is supplied to a stereo decoder 10 via a buffer amplifier 8. This stereo decoder 10 receives a pilot signal (19K) from the PLL circuit 6 as well as the stereo composite signal.
Hz), the stereo decoder 10 synthesizes the stereo composite signal and the 38KHz switching signal, separates the left and right stereo signals, and outputs the signals to the output terminals 12R, 1.
Left and right stereo signals are taken out individually to 2L.

Conventionally, in this stereo demodulator, variable resistors 14 and 16 are connected to output terminals 12R and 12L of the stereo decoder 10, respectively, in order to adjust the level of the stereo demodulated output.
The left and right stereo signals obtained from 16 are sent to amplifier 1.
The signal is output from output terminals 20R and 20L to a speaker or a headphone via the output terminal 8.

In such a stereo demodulator, two variable resistors are required for level adjustment, which increases the number of parts and prevents miniaturization in so-called headphone radios. This is not practical in a circuit configuration that requires a knob. Further, even in a simple portable radio receiver, adjusting the levels of left and right stereo signals generally requires a lot of effort.

By the way, if level adjustment is performed on the stereo composite signal before stereo demodulation, it is possible to simplify the level adjustment means, such as using a single variable resistor, compared to the case where the levels are adjusted individually for the left and right stereo signals. On the other hand, adjusting the level of the stereo composite signal also reduces the level of the pilot signal of the stereo composite signal, and the influence on stereo demodulation cannot be ignored. That is, if the level of the pilot signal is lowered, the signal-to-noise ratio becomes a problem, and the synchronization state of the phase-locked loop becomes unstable. As a result, the reliability of the stereo signal separation operation may decrease.

Therefore, an object of this invention is to provide a stereo demodulation device that can simplify level adjustment of left and right stereo signal levels without reducing the reliability of stereo demodulation.

That is, the stereo demodulator of this invention includes a phase-locked loop 6 that receives a stereo composite signal and generates a switching signal synchronized with a pilot signal in the stereo composite signal, and a variable resistor 26 on the input side of this phase-locked loop. a level adjustment circuit 22 which is installed and outputs the stereo composite signal from the input side of the phase-locked loop by adjusting it to an arbitrary amplitude level through the variable resistor; and a DC current of the stereo composite signal whose level has been adjusted by the level adjustment circuit. a level shift circuit 28 for shifting the level to an optimum level on the phase-locked loop side; and a stereo system for receiving the switching signal from the phase-locked loop and separating the stereo signal from the stereo composite signal that has been level-shifted through the level shift circuit. The present invention is characterized by comprising a coder 10.

Hereinafter, this invention will be described in detail with reference to embodiments shown in the drawings.

FIG. 2 shows an embodiment of the stereo demodulator of this invention, and the same parts as those of the stereo demodulator shown in FIG. 1 are given the same reference numerals. In the figure, the stereo composite signal given to input terminal 2 is the PLL
The signal is supplied to the circuit 6 and also to the level shift circuit 28 via the level adjustment circuit 22 inserted between this signal system and the reference potential point.
The level adjustment circuit 22 is configured to adjust the signal level, and the subsequent level shift circuit 28 is configured to shift the DC level after the signal level adjustment.
The output of this level shift circuit 28 is applied to the stereo decoder 10 together with the output switching signal of the PLL circuit 6.

The level adjustment circuit 22 arranged at the input section of the stereo composite signal of the stereo decoder 10 is configured by connecting a resistor 24 and a variable resistor 26 in series between the signal line where the input terminal 2 is formed and a reference potential point. has been done. When the stereo demodulator is formed of a monolithic integrated circuit, a reference potential point (GND) is set on the semiconductor substrate in order to cause the signal amplitude to swing largely around the substrate potential.

Then, the output terminal 12 of the stereo decoder 10
An amplifier 18 for extracting audio signals to the outside is directly connected to R and 12L.

With this configuration, the stereo composite signal applied to the input terminal 2 is directly applied to the PLL circuit 6,
The stereo decoder 10 includes a resistor 24 and a variable resistor 2.
A stereo composite signal whose level has been adjusted by 6 is provided via a level shift circuit 28. That is, the level of the stereo composite signal applied to the stereo decoder 10 can be adjusted by adjusting the position of the variable terminal of the variable resistor 26. As a result, the variable resistors 14 and 16 of the conventional circuit can be eliminated, and the desired level of audio output can be obtained by adjusting a single variable resistor 26. By unifying the variable resistor, the configuration can be simplified. can be achieved. Further, in this case, since the input level of the PLL circuit 6 can be used as a reference, the conventional amplifier 4 can be omitted at the input section of the PLL circuit 6.

Further, when such a stereo decoder is used for demodulating AM signals, the level adjustment circuit 22 can be similarly used for adjusting the level of audio output.

Furthermore, in such a stereo demodulator, if the reference potential point of the resistor 24 and variable resistor 26 is set on a semiconductor substrate in a monolithic integrated circuit, the amplitude of the input signal can be given based on the reference potential point. As a result, the dynamic range is expanded and stereo demodulation can be performed at low operating voltage.

FIG. 3 shows a specific circuit of the above embodiment. That is, the output of the FM demodulation circuit 29 is applied to the input terminal 2 via the coupling capacitor 30. The base of the transistor 32 of the level shift circuit 28 is connected to the variable terminal of the variable resistor 26 of the level adjustment circuit 22, and the collector of this transistor 32 is connected to the reference potential point, and the drive voltage is applied from the collector and the output of the power supply terminal 3. A transistor 36 and a resistor 38 are connected to the power supply line to which Vcc is applied.
is connected. A bias input terminal 40 is formed at the base of the transistor 36, and a constant bias voltage V _B is applied thereto.

The base of a transistor 42 is connected to the collector of the transistor 36.
has its emitter connected to a reference potential point via a resistor 44, and a current inversion circuit 46 is installed between its collector and the power supply line. That is, a transistor 48 serving as a diode with a common base and collector is connected between the power supply line and the collector of the transistor 42.
The bases of transistors 50 are commonly connected to the bases and collectors of transistors 8 and 8. This transistor 50 connects the power supply line and the base of the transistor 52.
The emitter of the transistor 52 is connected to a reference potential point via a resistor 54. The output of this level shift circuit 28 is taken out from the base and collector of the transistor 52 and is applied to the stereo decoder 10.

According to such a configuration, the level adjustment circuit 22
The stereo composite signal adjusted to a desired level by the variable resistor 26 is given to the stereo decoder 10 after its DC level is shifted by the level shift circuit 28.

Moreover, according to such a circuit configuration, stable operation can be obtained with a low operating voltage. To explain this operation, if a signal of 100 mVrms is applied to point A, a signal of 0.14 V _pp is superimposed on point B, and the collector-emitter of the PNP transistor 36 is superimposed on the point B between the power supply line and the reference potential point (GND). voltage V _CE ≒0.14V, signal voltage Vsignal≒0.14V,
Voltage drop of resistor 38 (3.6KΩ) V _R ≈0.14V and forward drop voltage of substrate PNP transistor
A voltage of 0.97V is required, which is the sum of V _F ≒0.55V, and this is the minimum operating voltage. When driving this stereo demodulator with V _CC = 1.5V,
It will be necessary to reduce the operating voltage to 0.90V, and it will be necessary to reduce the input level to achieve this. That is, if the signal level is adjusted and a signal of, for example, 50 mVrms is applied to point A in the above state, operation is possible up to V _CC ≈0.90 V using the same calculation as above. However, if the input signal level at the input section (point C) of the PLL circuit 6 is lowered, it may become impossible to distinguish between phase synchronization operation and stereo demodulation. Therefore, in order to ensure stable operation, the PLL circuit 6 is given a stereo composite signal whose level has not been adjusted, while the level shift circuit 28 on the input side of the stereo decoder 10 is given a signal level with an SN ratio. level adjustment circuit 2 to a level that can withstand power reduction.
2, and the level-adjusted DC level of the signal is shifted by the level shift circuit 28, thereby reducing the operating voltage.

In this case, since a variable resistor 26 is installed in such a level adjustment circuit 22, the audio signal level for driving a speaker etc. is controlled by the variable resistor 26.
Adjustment can be made using only 6, which also makes it possible to simplify the level adjustment system.

As described above, according to this invention, the pilot signal that is the basis of the stereo demodulation is extracted from the unleveled stereo composite signal,
Since the stereo demodulation operation is performed using a switching signal based on the pilot signal, the reliability of the stereo demodulation operation is not deteriorated. Furthermore, since the level of the stereo composite signal before stereo demodulation is adjusted by a single variable resistor, the circuit configuration can be simplified by using a single resistor, etc., compared with the adjustment of the playback level of the stereo signal after stereo demodulation. Moreover, since the DC level of the level-adjusted stereo composite signal is shifted to the optimum level on the stereo decoder side, the operating voltage of the stereo decoder can be reduced, and stable operation can be obtained at a low operating voltage, resulting in good stereo signal separation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional stereo demodulation device, FIG. 2 is a block diagram showing an embodiment of the stereo demodulation device of this invention, and FIG. 3 is a circuit diagram showing an embodiment of the stereo demodulation device of this invention. be. 6... Phase synchronization group, 10... Stereo decoder, 22... Level adjustment circuit, 26... Variable resistor, 28... Level shift circuit.

Claims (1)

[Claims for Utility Model Registration] A phase-locked loop that receives a stereo composite signal and generates a switching signal synchronized with a pilot signal in the stereo composite signal; a variable resistor installed on the input side of the phase-locked loop; a level adjustment circuit that adjusts and extracts the stereo composite signal to an arbitrary amplitude level from the input side of the phase-locked loop through the variable resistor; a level shift circuit for shifting to an optimum level on the loop side; and a stereo coder for receiving the switching signal from the phase-locked loop and separating the stereo signal from the stereo composite signal level-shifted through the level shift circuit. A stereo demodulator characterized by: