JPH01215122A - Phase synchronizing signal generating circuit - Google Patents

Abstract

PURPOSE:To realize the always stable control characteristic by detecting the period and controlling the entire loop gain so as to be constant. CONSTITUTION:A data period detection circuit 7 outputs a control signal 7a inversely proportional to the period of a data to a gain control circuit 6. The gain control circuit 6 uses a control signal 7a so as to control the amplitude of an output voltage 2a of a phase comparator 2 thereby making the gain of phase comparison constant at all times. The output signal 6a of the gain control circuit 6 is given to a loop filter 3 to output a voltage 3a corresponding to a phase error to a voltage controlled oscillator 4. Moreover, the clock pulse generated by the voltage controlled oscillator 4 is fed back to the phase comparator 2 and a data period detection circuit 7. Thus, the loop gain of the PLL circuit (phase synchronizing signal generating circuit) independently of the frequency of an input data and stable control characteristic is realized.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to loop characteristics of a phase synchronized signal generation circuit (hereinafter referred to as a PLL circuit) that generates a timing clock (hereinafter referred to as a clock) synchronized with an input digital signal. Regarding improvements.

[Conventional technology]

When recording and reproducing (or transmitting) digital signals, in order to eliminate the influence of phase fluctuations (jitter) contained in received data, it is necessary to generate a clock synchronized with the data and resynchronize it. It is desirable that this clock has a characteristic that it follows gradual frequency fluctuations of the input, but does not follow jitter caused by noise or the like. For this reason, measures have been taken to generate a clock synchronized with the reproduced data using a tank circuit, a PLL circuit, or the like. Especially P
The LL circuit has Q, which indicates the sharpness of center frequency setting and selection.
It is widely used because the values can be set freely.

FIG. 7 shows an example of a conventional PLL circuit configuration, and the principle of operation will be briefly explained below.

The input signal is N R7゜(
(Non Return to Zero) signal.

This is a method in which the input signal II 111 or "0" corresponds to the high level and low level of the signal amplitude.

Digital data 1a input from an input terminal 1 is converted into a continuous input clock lla by a continuous clock 41 circuit 11 composed of a tank circuit or the like. This input clock lla and the output clock 4a of the electrically controlled oscillator (VCO circuit) 4 are input to the phase comparator (PC) 2, and the phase difference -
An error voltage 2a proportional to is output to a loop filter (for example, a low-pass filter LPF) 3. As this phase comparator 2, for example, a multiplication type phase comparator or the like may be used.

The loop filter 3 passes only signals in a necessary band and outputs them to the voltage controlled oscillator 4, which oscillates an output clock 4a of a necessary frequency. This output clock is sent to a phase comparator 2 to form a feedback loop.

This circuit includes a tank circuit to make the input clock continuous, and has problems such as errors due to adjustment of the tuning frequency, aging, temperature changes, etc.

For this reason, a phase comparator as shown in FIG. 2 has been proposed which directly compares the input data [a] and the output clock 4a. The operation of this circuit will be explained using the signal waveform diagram in FIG.
and the original data 1a through an EOR circuit (exclusive OR circuit) 22
Enter. The output signal of this FOR circuit becomes a pulse indicating the conversion point of the input data, as shown in FIG. 3b.

Further, the reproduced data 1a is input to the rat circuit 23, latched by the output clock 4a, and this data and the original input data 1a are input to the FOR circuit 24. As a result, the target
A pulse C having a width proportional to the phase difference between the clock 1a and the clock is generated. Next, these two pulses b and c are input to the differential amplifier 25, and the phase error is converted into a voltage 2a.

This type of prior art includes 1, for example, Japanese Patent Application Laid-open No. 58-500.
54, JP-A-60-35862, etc.

[Problem to be solved by the invention]

In the phase comparator circuit shown in FIG. 2, a phase error signal is obtained only at a data conversion point, so the loop gain varies depending on the input data, resulting in poor responsiveness.

It also generates a sawtooth wave synchronized with the output clock,
There is a method of sampling and holding this at the pulse b indicating the conversion point of the input data described above.

Although this method eliminates the above-mentioned problem of loop gain fluctuation, it has the drawback that it is difficult to improve sample-hold detection accuracy at high frequencies of several MHz or more.

The object of the present invention is to eliminate the drawbacks of the above-mentioned prior art.

An object of the present invention is to provide a PLL circuit having good loop characteristics.

[Means to solve the problem]

The present invention provides stable control characteristics by controlling the loop gain in inverse proportion to the period of the data conversion point when configuring a PLL circuit using a phase comparator of the type shown in FIG. This is to realize the following.

[Effect]

FIG. 1 shows a basic configuration diagram of a PLL circuit according to the present invention,
The effect will be explained. The sensitivity of the phase comparator 2 is Kp, the sensitivity of the gain control circuit 6 is Kg, the transfer characteristic of the loop filter 3 is F(s), and the sensitivity of the voltage controlled oscillator 4 is Kv.

Here, s=jω, and Kp=Kg is a function of the repetition period of input data. This PLL circuit has constant repetitive data.

For example, data with the highest frequency (clock frequency f C
1/2 of k), the closed loop gain G (s) of the entire circuit is as follows.

Gap(s)=Kp-Kg” Kv-F(s)/s Now,
Gain Kp of phase comparator 2 and gain k of gain control circuit 6
When g is fixed (=1), the operation is exactly the same as the conventional PLL circuit. That is, the input frequency is ω8, and its phase is θ1. If the output frequency is ω0 and its phase is 00, the closed loop transfer function Gct(s) with respect to the phase is generally 1+ as a loop filter F(s).
A filter of the form sTx (lag lead filter) is used. A circuit example of this filter is shown in FIG. 8, and its frequency characteristics are shown in FIG. 9. This circuit is ωz (=1/Tz)
The following frequencies are passed, and from ω1 to ωz (= 1 /
Attenuates signals of frequencies up to T2). Here T 1
= (R1+Rx)C, T = RzC.

An example of open-loop frequency characteristics of a PLL circuit using this loop filter is shown by solid line A in FIGS. 10 and 11.

Normally, phase margin is 40 to 50 degrees and gain margin is 10 to 20 d.
It is set to about B. The closed loop characteristic in this case is expressed as
This is shown by solid line A in the figure.

The resonance height Mp value is about 2 to 3 dB.

Next, consider a case where the input data cycle is reduced to, for example, 115. At this time, if the phase comparator shown in FIG. 2 is used, the sensitivity Kp decreases to 115, so the open loop characteristic becomes as shown by the dotted line 8 in FIG. 10. As a result, the phase margin becomes very small, and the resonance height of the closed loop characteristic becomes very large as shown by the dotted line B in FIG. 12, causing a problem that the PLL circuit becomes unstable.

In order to deal with this problem, the present invention stabilizes the characteristics by adjusting the loop gain of the PLL circuit (increasing Kg by 5 in the above example) according to the cycle of input data.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. The digital signal 1a input to the input terminal 1 is sent to the phase comparator 2.
is input to the data cycle detection circuit 7. As a phase comparator, a circuit shown in FIG. 2 is used, and the phase difference between the data conversion point and the clock conversion point is converted into a voltage 2a, which is output to the gain control circuit 6. Further, the data cycle detection circuit 7 outputs a control signal 7a that is inversely proportional to the data repetition cycle to the gain control circuit 6. The gain control circuit 6 controls the amplitude of the output voltage 2a of the phase comparator 2 using a control signal 7a so that the gain of phase comparison is always constant. The output signal 6a of this gain control circuit 6 is input to the loop filter 3, and a voltage 3a corresponding to the phase error is output to the voltage controlled oscillator 4.

Further, the clock pulse generated by the voltage controlled oscillator 4 is fed back to the phase comparator 2 and the data period detection circuit 7. As a result, the PLT and the loop gain of the circuit can be optimized regardless of the repetition frequency of input data, and stable control characteristics can be achieved.

FIG. 4 shows an example of the data period detection circuit 7, and FIG. 5 shows its signal waveform diagram. Using input data 1a and clock pulse 4a, a pulse P corresponding to a data conversion point is generated. That is, the data delayed by the latch circuits 71 and 72 is input to the exclusive OR circuit 73 to generate a pulse p corresponding to the data conversion point. Further, the clock pulse is inputted to the counter 74, and a periodic pulse 74a having a constant period (for example, 8 clocks) is generated. The counter 75 uses this periodic pulse as a clear pulse.

The clock pulses 4a are counted only during the period when the pulse p is low. As a result, the output of the counter 75 is the digital data q(
When expressed as an analog value, a signal such as r is obtained. This data (for example, 4 bits) is output to the gain control circuit 4.

FIG. 6 shows an example of the gain control circuit 4. This circuit has the same configuration as a multiplication type D/A converter, that is, multiple resistors R
It can be configured from a switch SW.

The resistance values may be set in a proportional relationship of 1, 2, and 4.8, and the switch SW may be switched by the output signal 7a of the data cycle detection circuit 7. Note that the data cycle detection circuit 7 and the gain control circuit 4 can also be realized by analog circuits.

As a result, even if the input data repetition period changes, the loop gain of the PLL circuit can always be kept constant.6 The operation of the loop filter 3 and voltage controlled oscillator 4 is the same as the conventional operation. Therefore, it is omitted.

Further, the loop filter 3 is not limited to the lag lead type, but can be similarly implemented even if it is a complete integral type.

〔Effect of the invention〕

As described above, according to the present invention, in a PLL circuit that extracts a clock from a signal whose repetition period changes, such as an NRZ signal, the repetition period can be detected to make the overall loop gain constant. It is confirmed that stable control characteristics can always be achieved by controlling the temperature.

Although the NRZ signal was described as an example, the NRZI signal and MF
It goes without saying that the present invention can be similarly applied to M signals, etc., as well as multivalued signals.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram of a phase comparator, Fig. 3 is a signal waveform diagram of the phase comparator, and Fig. 4 is a data period detection circuit diagram according to the present invention. , FIG. 5 is a signal waveform diagram of the data period detection circuit, FIG. 6 is a gain control circuit diagram according to the present invention, FIG. 7 is a conventional PLL circuit diagram, FIG. 8 is an example diagram of a loop filter, and FIG. 9 10 is a frequency characteristic diagram of the loop filter, FIG. 10 is a frequency characteristic diagram of open-loop gain, FIG. 11 is a frequency characteristic diagram of open-loop phase, and FIG. 12 is a frequency characteristic diagram of closed-loop gain. 2... Phase comparator, 3... Loop filter, 4...
...Voltage controlled oscillator, 6... Gain control circuit, 7...
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Claims (1)

[Claims] 1. In a phase synchronization signal generation circuit that generates a clock synchronized with an input digital signal, a phase comparator that generates an error voltage proportional to the phase difference between an input data conversion point and a clock conversion point. 1. A phase synchronization signal generation circuit comprising: and a circuit for controlling a loop gain according to a repetition period of data conversion points. 2. The phase synchronization signal generation circuit according to claim 1, wherein the gain is set so that the product of the sensitivity of the phase comparator and the sensitivity of the gain control circuit is approximately 1.