JPS6196571A - Signal reader - Google Patents

Abstract

PURPOSE:To restore unlocking, to suppress damage and to improve the possibility of reading properly data by making the time constant of a loop filter small when a field sink and the unlocking of a PLL circuit are detected. CONSTITUTION:When a field sink followed by a vertical sink where the input of a terminal 1 is in a data field is detected, an FS detection circuit 3 issues a signal to a time constant switching circuit 11 to switch the time constant of the loop filter 8 to a small value. As a result, the PLL circuit responds more quickly and is locked with a bit synchronizing signal at a high speed. When a drop-out occurs for a long time, the PLL circuit in a data section is unlocked due to some reasons, or locking of the PLL circuit during the field sink period is impossible, a synchronization monitor circuit 10 detects such cases. Then a signal is outputted to the time constant switching circuit 11, and the PLL circuit is quickly locked by switching the time constant of the filter 8 to a small value.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal reading device for reading signals reproduced from a recording medium in which digital data and image signals are recorded in a video format.

[Conventional technology]

When digital data is recorded on a recording medium and later reproduced, a clock signal is required to provide timing for reading the data. For this reason, the clock signal component is recorded together with the data at the time of recording, and the il raw time T
A self-clock system in which a clock signal is extracted using an LL circuit is common. For example, as disclosed in Vol. 24, No. 11, pages 36 to 37 of the magazine "Electronic Technology", in a 3.5-inch microfloppy disk, the beginning of the data field is A sink area is provided in which the PLL circuit is locked prior to reading data. PLL
It takes some time for the circuit to lock onto a signal of a predetermined frequency and phase, and this time becomes faster as the time constant of the loop filter included in the circuit is smaller. On the other hand, if the time constant of the loop filter is made smaller, the response becomes faster, so it becomes more susceptible to noise, disturbance, etc.

The screws may come off easily and become unstable. Therefore, in the sink area, the time constant is made small to lock the PLL circuit at high speed, and in the data area, the time constant is made large to prevent the lock from being lost due to noise, dropout, etc. Furthermore, when the modulation method is FM, the clock signal in the sink area is half of that when it is MFM, so the time constant of the loop filter is also switched.

[Problem that the invention seeks to solve]

However, in such a conventional signal reading device, P
Once the I and 5 circuits have been locked, if they become unlocked for some reason, it takes a long time to lock them again. Furthermore, if the sink area in the above example cannot be locked within a predetermined period for some reason, there is a drawback that it takes a long time to finally lock the area.

[Means for solving problems]

FIG. 1 shows the configuration of a signal reading device according to the present invention. In the figure, 1 is an input terminal to which an input signal is supplied,
It is connected to a separation circuit 2 that separates data from an input signal, and a detection circuit 3 that detects a field sync provided at the beginning of a field in which data is recorded from the input signal.

4 is a reading circuit for reading the digital data separated by the separation circuit 2; Reference numeral 5 denotes an extraction circuit for extracting the edges of the data separated by the separation circuit 2. The Tostable multivibrator 6 is triggered in synchronization with the edge extracted by the extraction circuit 5, and its output pulse is P L 5
The signal is supplied to the phase comparator 7 as a standard signal of the circuit.

8 is a loop filter (
9 is a voltage controlled oscillator controlled by the output of the loop filter 8, and a phase comparator 7
, loop filter 8, and voltage controlled oscillator 9 constitute a PLL circuit. The output of the voltage controlled oscillator 9 is sent to the reading circuit 4.
and is supplied to the phase comparator 7. 10 is a phase comparator 7
This is a monitoring circuit that is connected to, for example, the level of the phase error signal of the phase comparator 7 and monitors whether the PLL circuit is locked to a signal of a predetermined frequency and phase.

A switching circuit 11 receives the output of the detection circuit 3 or the monitoring circuit 10 and switches the time constant of the loop filter 8.

[Effect]

The operation will now be explained. The signal input from input terminal 1 is a video format signal. Therefore, for example, in the case of the NTSC system, two fields each consisting of 262.5 horizontal scanning lines constitute one frame, and a particle zinc (vertical synchronization signal) is provided at the beginning of each field for a predetermined number of lines. It is being If the field is a video field, an image signal (analog signal) is recorded following the particle zinc, and is similar to a normal television signal. If the field is a data field, the structure is as shown in FIG. 2, for example. That is, one line of field sync is provided following the particle zinc, the next four lines are control data blocks containing field codes, and nine data blocks of every 26 lines are formed.

Since the separating circuit 2 separates and outputs only the data from the data field among the fields, the image signal of the video field is not supplied to the reading circuit 4 and the extracting circuit 5. The extraction circuit 5 extracts edges of the separated data and triggers the monostable multivibrator 6 at the timing of the extracted edges. The output pulse of this monostable multivibrator 6 becomes the reference signal of the PLL circuit. The reference signal includes a component equal to the lock frequency, and the PLL circuit is frequency-synchronized to this clock frequency. In addition, the reference phase of the reference signal is determined by the data edge timing and the output pulse width of the monostable multivibrator 6, and the PLL
The circuit is phase locked to this reference phase. In this way P
Since the LL circuit locks to a predetermined frequency and phase and outputs a clock signal, the reading circuit 4 can read digital data based on the timing.

By the way, when what is input to the input terminal 1 is a data field, the 22nd line following the particle zinc serves as a field sync in which a pit synchronization signal is recorded. When this field sync is detected, the detection circuit 3 issues a signal to the switching circuit 11 to switch the time constant of the loop filter 8 to a smaller value. As a result, the PLL circuit has a faster response and quickly locks onto the bit synchronization signal. When the field sync is completed, the detection circuit 3 issues a signal to the switching circuit 11 again, and the loop filter 8
Switch the time constant to a value 4 times larger. Therefore, in the control data block including the field code 1 from the 23rd line to the 26th line following the field sync, and the data block section continuing 9 blocks every 26th line from the 27th line, the loop filter 8
The time constant of is switched to a large value. Therefore, the clock signal output from the voltage controlled oscillator 9 is stable during that time, and even if there is noise, drop error, etc., the PLL
Circuits are becoming less susceptible to them.

However, if dropout occurs for a relatively long period of time or due to other causes, the PLL circuit may lose lock during the data interval or may fail to lock during the field sync period. In such a case, the monitoring circuit 10 detects this and outputs a signal to the switching circuit 11. As a result, the loop filter 8
The time constant of is switched to a small value so that the PLL circuit quickly locks. After that, when the PLL circuit is locked, the monitoring circuit 10 issues a signal to the switching circuit j1 to switch the time constant of the loop filter 8 to a larger value.

〔effect〕

As described above, in the present invention, the lock state of the PLL circuit is monitored, and the time constant of the loop filter is switched to a small value not only during the field sync period but also when the lock is released. Even if the error occurs, it will be possible to recover quickly, minimize the damage during that time, and improve the probability that the data can be read accurately.

Furthermore, even if the lock cannot be achieved during the field sync period, the same effect can be obtained by quickly locking the lock.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a signal reading device of the present invention, and FIG. 2 is a schematic diagram of its signals. 2... Separation circuit 3... Detection circuit 4... Reading circuit 5... Extraction circuit 6... Monostable multivibrator 7... Phase comparator F (... Loop filter 9... Voltage controlled oscillator" 0...Monitoring circuit 11...Switching circuit or higher

Claims (1)

[Claims] (1) In a signal reading device that reads a playback signal from a recording medium in which digital data and an image signal are recorded as a video format signal, the digital data is recorded from the playback signal at the beginning of the data field. a detection circuit for detecting a field sync signal, a separation circuit for separating the digital data from the reproduced signal, an extraction circuit for extracting an edge of the digital data separated by the separation circuit, and an extraction circuit for extracting an edge of the digital data separated by the separation circuit; PL that extracts the clock signal from the edge
an L circuit, a reading circuit that reads the digital data separated by the separation circuit based on the clock signal extracted by the PLL circuit, and a monitoring circuit that monitors whether or not the PLL circuit is locked. , a switching circuit that switches a time constant of a loop filter of the PLL circuit, and when the detection circuit detects the field sync, controls the switching circuit to reduce the time constant of the loop filter, and the monitoring circuit A signal reading device characterized in that when detecting that the PLL circuit is unlocked, the switching circuit is controlled to reduce the time constant of the loop filter.